fix compilation after merge
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / sysdev / mpic_pasemi_msi.c
1 /*
2 * Copyright 2007, Olof Johansson, PA Semi
3 *
4 * Based on arch/powerpc/sysdev/mpic_u3msi.c:
5 *
6 * Copyright 2006, Segher Boessenkool, IBM Corporation.
7 * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 */
15
16 #undef DEBUG
17
18 #include <linux/irq.h>
19 #include <linux/bootmem.h>
20 #include <linux/msi.h>
21 #include <asm/mpic.h>
22 #include <asm/prom.h>
23 #include <asm/hw_irq.h>
24 #include <asm/ppc-pci.h>
25 #include <asm/msi_bitmap.h>
26
27 #include "mpic.h"
28
29 /* Allocate 16 interrupts per device, to give an alignment of 16,
30 * since that's the size of the grouping w.r.t. affinity. If someone
31 * needs more than 32 MSI's down the road we'll have to rethink this,
32 * but it should be OK for now.
33 */
34 #define ALLOC_CHUNK 16
35
36 #define PASEMI_MSI_ADDR 0xfc080000
37
38 /* A bit ugly, can we get this from the pci_dev somehow? */
39 static struct mpic *msi_mpic;
40
41
42 static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
43 {
44 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
45 mask_msi_irq(data);
46 mpic_mask_irq(data);
47 }
48
49 static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
50 {
51 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
52 mpic_unmask_irq(data);
53 unmask_msi_irq(data);
54 }
55
56 static struct irq_chip mpic_pasemi_msi_chip = {
57 .irq_shutdown = mpic_pasemi_msi_mask_irq,
58 .irq_mask = mpic_pasemi_msi_mask_irq,
59 .irq_unmask = mpic_pasemi_msi_unmask_irq,
60 .irq_eoi = mpic_end_irq,
61 .irq_set_type = mpic_set_irq_type,
62 .irq_set_affinity = mpic_set_affinity,
63 .name = "PASEMI-MSI",
64 };
65
66 static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
67 {
68 if (type == PCI_CAP_ID_MSIX)
69 pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
70
71 return 0;
72 }
73
74 static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
75 {
76 struct msi_desc *entry;
77 irq_hw_number_t hwirq;
78
79 pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
80
81 list_for_each_entry(entry, &pdev->msi_list, list) {
82 if (entry->irq == NO_IRQ)
83 continue;
84
85 hwirq = virq_to_hw(entry->irq);
86 irq_set_msi_desc(entry->irq, NULL);
87 irq_dispose_mapping(entry->irq);
88 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
89 hwirq, ALLOC_CHUNK);
90 }
91
92 return;
93 }
94
95 static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
96 {
97 unsigned int virq;
98 struct msi_desc *entry;
99 struct msi_msg msg;
100 int hwirq;
101
102 pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
103 pdev, nvec, type);
104
105 msg.address_hi = 0;
106 msg.address_lo = PASEMI_MSI_ADDR;
107
108 list_for_each_entry(entry, &pdev->msi_list, list) {
109 /* Allocate 16 interrupts for now, since that's the grouping for
110 * affinity. This can be changed later if it turns out 32 is too
111 * few MSIs for someone, but restrictions will apply to how the
112 * sources can be changed independently.
113 */
114 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
115 ALLOC_CHUNK);
116 if (hwirq < 0) {
117 pr_debug("pasemi_msi: failed allocating hwirq\n");
118 return hwirq;
119 }
120
121 virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
122 if (virq == NO_IRQ) {
123 pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
124 hwirq);
125 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
126 ALLOC_CHUNK);
127 return -ENOSPC;
128 }
129
130 /* Vector on MSI is really an offset, the hardware adds
131 * it to the value written at the magic address. So set
132 * it to 0 to remain sane.
133 */
134 mpic_set_vector(virq, 0);
135
136 irq_set_msi_desc(virq, entry);
137 irq_set_chip(virq, &mpic_pasemi_msi_chip);
138 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
139
140 pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
141 "addr 0x%x\n", virq, hwirq, msg.address_lo);
142
143 /* Likewise, the device writes [0...511] into the target
144 * register to generate MSI [512...1023]
145 */
146 msg.data = hwirq-0x200;
147 write_msi_msg(virq, &msg);
148 }
149
150 return 0;
151 }
152
153 int mpic_pasemi_msi_init(struct mpic *mpic)
154 {
155 int rc;
156
157 if (!mpic->irqhost->of_node ||
158 !of_device_is_compatible(mpic->irqhost->of_node,
159 "pasemi,pwrficient-openpic"))
160 return -ENODEV;
161
162 rc = mpic_msi_init_allocator(mpic);
163 if (rc) {
164 pr_debug("pasemi_msi: Error allocating bitmap!\n");
165 return rc;
166 }
167
168 pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
169
170 msi_mpic = mpic;
171 WARN_ON(ppc_md.setup_msi_irqs);
172 ppc_md.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
173 ppc_md.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
174 ppc_md.msi_check_device = pasemi_msi_check_device;
175
176 return 0;
177 }