2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/memblock.h>
27 #include <linux/log2.h>
28 #include <linux/slab.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/machdep.h>
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/fsl_pci.h>
37 static int fsl_pcie_bus_fixup
, is_mpc83xx_pci
;
39 static void quirk_fsl_pcie_header(struct pci_dev
*dev
)
43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev
, PCI_CAP_ID_EXP
))
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
);
49 if ((hdr_type
& 0x7f) != PCI_HEADER_TYPE_BRIDGE
)
52 dev
->class = PCI_CLASS_BRIDGE_PCI
<< 8;
53 fsl_pcie_bus_fixup
= 1;
57 static int fsl_indirect_read_config(struct pci_bus
*, unsigned int,
60 static int fsl_pcie_check_link(struct pci_controller
*hose
)
64 if (hose
->indirect_type
& PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK
) {
65 if (hose
->ops
->read
== fsl_indirect_read_config
) {
70 indirect_read_config(&bus
, 0, PCIE_LTSSM
, 4, &val
);
72 early_read_config_dword(hose
, 0, 0, PCIE_LTSSM
, &val
);
73 if (val
< PCIE_LTSSM_L0
)
76 struct ccsr_pci __iomem
*pci
= hose
->private_data
;
77 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
78 val
= (in_be32(&pci
->pex_csr0
) & PEX_CSR0_LTSSM_MASK
)
79 >> PEX_CSR0_LTSSM_SHIFT
;
80 if (val
!= PEX_CSR0_LTSSM_L0
)
87 static int fsl_indirect_read_config(struct pci_bus
*bus
, unsigned int devfn
,
88 int offset
, int len
, u32
*val
)
90 struct pci_controller
*hose
= pci_bus_to_host(bus
);
92 if (fsl_pcie_check_link(hose
))
93 hose
->indirect_type
|= PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
95 hose
->indirect_type
&= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
97 return indirect_read_config(bus
, devfn
, offset
, len
, val
);
100 static struct pci_ops fsl_indirect_pci_ops
=
102 .read
= fsl_indirect_read_config
,
103 .write
= indirect_write_config
,
106 static void __init
fsl_setup_indirect_pci(struct pci_controller
* hose
,
107 resource_size_t cfg_addr
,
108 resource_size_t cfg_data
, u32 flags
)
110 setup_indirect_pci(hose
, cfg_addr
, cfg_data
, flags
);
111 hose
->ops
= &fsl_indirect_pci_ops
;
114 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
116 #define MAX_PHYS_ADDR_BITS 40
117 static u64 pci64_dma_offset
= 1ull << MAX_PHYS_ADDR_BITS
;
119 static int fsl_pci_dma_set_mask(struct device
*dev
, u64 dma_mask
)
121 if (!dev
->dma_mask
|| !dma_supported(dev
, dma_mask
))
125 * Fixup PCI devices that are able to DMA to above the physical
126 * address width of the SoC such that we can address any internal
127 * SoC address from across PCI if needed
129 if ((dev
->bus
== &pci_bus_type
) &&
130 dma_mask
>= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS
)) {
131 set_dma_ops(dev
, &dma_direct_ops
);
132 set_dma_offset(dev
, pci64_dma_offset
);
135 *dev
->dma_mask
= dma_mask
;
139 static int setup_one_atmu(struct ccsr_pci __iomem
*pci
,
140 unsigned int index
, const struct resource
*res
,
141 resource_size_t offset
)
143 resource_size_t pci_addr
= res
->start
- offset
;
144 resource_size_t phys_addr
= res
->start
;
145 resource_size_t size
= resource_size(res
);
146 u32 flags
= 0x80044000; /* enable & mem R/W */
149 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
150 (u64
)res
->start
, (u64
)size
);
152 if (res
->flags
& IORESOURCE_PREFETCH
)
153 flags
|= 0x10000000; /* enable relaxed ordering */
155 for (i
= 0; size
> 0; i
++) {
156 unsigned int bits
= min(ilog2(size
),
157 __ffs(pci_addr
| phys_addr
));
162 out_be32(&pci
->pow
[index
+ i
].potar
, pci_addr
>> 12);
163 out_be32(&pci
->pow
[index
+ i
].potear
, (u64
)pci_addr
>> 44);
164 out_be32(&pci
->pow
[index
+ i
].powbar
, phys_addr
>> 12);
165 out_be32(&pci
->pow
[index
+ i
].powar
, flags
| (bits
- 1));
167 pci_addr
+= (resource_size_t
)1U << bits
;
168 phys_addr
+= (resource_size_t
)1U << bits
;
169 size
-= (resource_size_t
)1U << bits
;
175 /* atmu setup for fsl pci/pcie controller */
176 static void setup_pci_atmu(struct pci_controller
*hose
)
178 struct ccsr_pci __iomem
*pci
= hose
->private_data
;
179 int i
, j
, n
, mem_log
, win_idx
= 3, start_idx
= 1, end_idx
= 4;
180 u64 mem
, sz
, paddr_hi
= 0;
181 u64 offset
= 0, paddr_lo
= ULLONG_MAX
;
182 u32 pcicsrbar
= 0, pcicsrbar_sz
;
183 u32 piwar
= PIWAR_EN
| PIWAR_PF
| PIWAR_TGI_LOCAL
|
184 PIWAR_READ_SNOOP
| PIWAR_WRITE_SNOOP
;
185 const char *name
= hose
->dn
->full_name
;
189 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
190 if (in_be32(&pci
->block_rev1
) >= PCIE_IP_REV_2_2
) {
197 /* Disable all windows (except powar0 since it's ignored) */
198 for(i
= 1; i
< 5; i
++)
199 out_be32(&pci
->pow
[i
].powar
, 0);
200 for (i
= start_idx
; i
< end_idx
; i
++)
201 out_be32(&pci
->piw
[i
].piwar
, 0);
203 /* Setup outbound MEM window */
204 for(i
= 0, j
= 1; i
< 3; i
++) {
205 if (!(hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
))
208 paddr_lo
= min(paddr_lo
, (u64
)hose
->mem_resources
[i
].start
);
209 paddr_hi
= max(paddr_hi
, (u64
)hose
->mem_resources
[i
].end
);
211 /* We assume all memory resources have the same offset */
212 offset
= hose
->mem_offset
[i
];
213 n
= setup_one_atmu(pci
, j
, &hose
->mem_resources
[i
], offset
);
215 if (n
< 0 || j
>= 5) {
216 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i
);
217 hose
->mem_resources
[i
].flags
|= IORESOURCE_DISABLED
;
222 /* Setup outbound IO window */
223 if (hose
->io_resource
.flags
& IORESOURCE_IO
) {
225 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
227 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
228 "phy base 0x%016llx.\n",
229 (u64
)hose
->io_resource
.start
,
230 (u64
)resource_size(&hose
->io_resource
),
231 (u64
)hose
->io_base_phys
);
232 out_be32(&pci
->pow
[j
].potar
, (hose
->io_resource
.start
>> 12));
233 out_be32(&pci
->pow
[j
].potear
, 0);
234 out_be32(&pci
->pow
[j
].powbar
, (hose
->io_base_phys
>> 12));
236 out_be32(&pci
->pow
[j
].powar
, 0x80088000
237 | (ilog2(hose
->io_resource
.end
238 - hose
->io_resource
.start
+ 1) - 1));
242 /* convert to pci address space */
246 if (paddr_hi
== paddr_lo
) {
247 pr_err("%s: No outbound window space\n", name
);
252 pr_err("%s: No space for inbound window\n", name
);
256 /* setup PCSRBAR/PEXCSRBAR */
257 early_write_config_dword(hose
, 0, 0, PCI_BASE_ADDRESS_0
, 0xffffffff);
258 early_read_config_dword(hose
, 0, 0, PCI_BASE_ADDRESS_0
, &pcicsrbar_sz
);
259 pcicsrbar_sz
= ~pcicsrbar_sz
+ 1;
261 if (paddr_hi
< (0x100000000ull
- pcicsrbar_sz
) ||
262 (paddr_lo
> 0x100000000ull
))
263 pcicsrbar
= 0x100000000ull
- pcicsrbar_sz
;
265 pcicsrbar
= (paddr_lo
- pcicsrbar_sz
) & -pcicsrbar_sz
;
266 early_write_config_dword(hose
, 0, 0, PCI_BASE_ADDRESS_0
, pcicsrbar
);
268 paddr_lo
= min(paddr_lo
, (u64
)pcicsrbar
);
270 pr_info("%s: PCICSRBAR @ 0x%x\n", name
, pcicsrbar
);
272 /* Setup inbound mem window */
273 mem
= memblock_end_of_DRAM();
276 * The msi-address-64 property, if it exists, indicates the physical
277 * address of the MSIIR register. Normally, this register is located
278 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
279 * this property exists, then we normally need to create a new ATMU
280 * for it. For now, however, we cheat. The only entity that creates
281 * this property is the Freescale hypervisor, and the address is
282 * specified in the partition configuration. Typically, the address
283 * is located in the page immediately after the end of DDR. If so, we
284 * can avoid allocating a new ATMU by extending the DDR ATMU by one
287 reg
= of_get_property(hose
->dn
, "msi-address-64", &len
);
288 if (reg
&& (len
== sizeof(u64
))) {
289 u64 address
= be64_to_cpup(reg
);
291 if ((address
>= mem
) && (address
< (mem
+ PAGE_SIZE
))) {
292 pr_info("%s: extending DDR ATMU to cover MSIIR", name
);
295 /* TODO: Create a new ATMU for MSIIR */
296 pr_warn("%s: msi-address-64 address of %llx is "
297 "unsupported\n", name
, address
);
301 sz
= min(mem
, paddr_lo
);
304 /* PCIe can overmap inbound & outbound since RX & TX are separated */
305 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
306 /* Size window to exact size if power-of-two or one size up */
307 if ((1ull << mem_log
) != mem
) {
308 if ((1ull << mem_log
) > mem
)
309 pr_info("%s: Setting PCI inbound window "
310 "greater than memory size\n", name
);
314 piwar
|= ((mem_log
- 1) & PIWAR_SZ_MASK
);
316 /* Setup inbound memory window */
317 out_be32(&pci
->piw
[win_idx
].pitar
, 0x00000000);
318 out_be32(&pci
->piw
[win_idx
].piwbar
, 0x00000000);
319 out_be32(&pci
->piw
[win_idx
].piwar
, piwar
);
322 hose
->dma_window_base_cur
= 0x00000000;
323 hose
->dma_window_size
= (resource_size_t
)sz
;
326 * if we have >4G of memory setup second PCI inbound window to
327 * let devices that are 64-bit address capable to work w/o
328 * SWIOTLB and access the full range of memory
331 mem_log
= ilog2(mem
);
333 /* Size window up if we dont fit in exact power-of-2 */
334 if ((1ull << mem_log
) != mem
)
337 piwar
= (piwar
& ~PIWAR_SZ_MASK
) | (mem_log
- 1);
339 /* Setup inbound memory window */
340 out_be32(&pci
->piw
[win_idx
].pitar
, 0x00000000);
341 out_be32(&pci
->piw
[win_idx
].piwbear
,
342 pci64_dma_offset
>> 44);
343 out_be32(&pci
->piw
[win_idx
].piwbar
,
344 pci64_dma_offset
>> 12);
345 out_be32(&pci
->piw
[win_idx
].piwar
, piwar
);
348 * install our own dma_set_mask handler to fixup dma_ops
351 ppc_md
.dma_set_mask
= fsl_pci_dma_set_mask
;
353 pr_info("%s: Setup 64-bit PCI DMA window\n", name
);
358 /* Setup inbound memory window */
359 out_be32(&pci
->piw
[win_idx
].pitar
, paddr
>> 12);
360 out_be32(&pci
->piw
[win_idx
].piwbar
, paddr
>> 12);
361 out_be32(&pci
->piw
[win_idx
].piwar
, (piwar
| (mem_log
- 1)));
364 paddr
+= 1ull << mem_log
;
365 sz
-= 1ull << mem_log
;
369 piwar
|= (mem_log
- 1);
371 out_be32(&pci
->piw
[win_idx
].pitar
, paddr
>> 12);
372 out_be32(&pci
->piw
[win_idx
].piwbar
, paddr
>> 12);
373 out_be32(&pci
->piw
[win_idx
].piwar
, piwar
);
376 paddr
+= 1ull << mem_log
;
379 hose
->dma_window_base_cur
= 0x00000000;
380 hose
->dma_window_size
= (resource_size_t
)paddr
;
383 if (hose
->dma_window_size
< mem
) {
384 #ifndef CONFIG_SWIOTLB
385 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
386 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
389 /* adjusting outbound windows could reclaim space in mem map */
390 if (paddr_hi
< 0xffffffffull
)
391 pr_warning("%s: WARNING: Outbound window cfg leaves "
392 "gaps in memory map. Adjusting the memory map "
393 "could reduce unnecessary bounce buffering.\n",
396 pr_info("%s: DMA window size is 0x%llx\n", name
,
397 (u64
)hose
->dma_window_size
);
401 static void __init
setup_pci_cmd(struct pci_controller
*hose
)
406 early_read_config_word(hose
, 0, 0, PCI_COMMAND
, &cmd
);
407 cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
409 early_write_config_word(hose
, 0, 0, PCI_COMMAND
, cmd
);
411 cap_x
= early_find_capability(hose
, 0, 0, PCI_CAP_ID_PCIX
);
413 int pci_x_cmd
= cap_x
+ PCI_X_CMD
;
414 cmd
= PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
415 | PCI_X_CMD_ERO
| PCI_X_CMD_DPERR_E
;
416 early_write_config_word(hose
, 0, 0, pci_x_cmd
, cmd
);
418 early_write_config_byte(hose
, 0, 0, PCI_LATENCY_TIMER
, 0x80);
422 void fsl_pcibios_fixup_bus(struct pci_bus
*bus
)
424 struct pci_controller
*hose
= pci_bus_to_host(bus
);
425 int i
, is_pcie
= 0, no_link
;
427 /* The root complex bridge comes up with bogus resources,
428 * we copy the PHB ones in.
430 * With the current generic PCI code, the PHB bus no longer
431 * has bus->resource[0..4] set, so things are a bit more
435 if (fsl_pcie_bus_fixup
)
436 is_pcie
= early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
);
437 no_link
= !!(hose
->indirect_type
& PPC_INDIRECT_TYPE_NO_PCIE_LINK
);
439 if (bus
->parent
== hose
->bus
&& (is_pcie
|| no_link
)) {
440 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; ++i
) {
441 struct resource
*res
= bus
->resource
[i
];
442 struct resource
*par
;
447 par
= &hose
->io_resource
;
449 par
= &hose
->mem_resources
[i
-1];
452 res
->start
= par
? par
->start
: 0;
453 res
->end
= par
? par
->end
: 0;
454 res
->flags
= par
? par
->flags
: 0;
459 int __init
fsl_add_bridge(struct platform_device
*pdev
, int is_primary
)
462 struct pci_controller
*hose
;
463 struct resource rsrc
;
464 const int *bus_range
;
466 struct device_node
*dev
;
467 struct ccsr_pci __iomem
*pci
;
469 dev
= pdev
->dev
.of_node
;
471 if (!of_device_is_available(dev
)) {
472 pr_warning("%s: disabled\n", dev
->full_name
);
476 pr_debug("Adding PCI host bridge %s\n", dev
->full_name
);
478 /* Fetch host bridge registers address */
479 if (of_address_to_resource(dev
, 0, &rsrc
)) {
480 printk(KERN_WARNING
"Can't get pci register base!");
484 /* Get bus range if any */
485 bus_range
= of_get_property(dev
, "bus-range", &len
);
486 if (bus_range
== NULL
|| len
< 2 * sizeof(int))
487 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
488 " bus 0\n", dev
->full_name
);
490 pci_add_flags(PCI_REASSIGN_ALL_BUS
);
491 hose
= pcibios_alloc_controller(dev
);
495 /* set platform device as the parent */
496 hose
->parent
= &pdev
->dev
;
497 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
498 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
500 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
501 (u64
)rsrc
.start
, (u64
)resource_size(&rsrc
));
503 pci
= hose
->private_data
= ioremap(rsrc
.start
, resource_size(&rsrc
));
504 if (!hose
->private_data
)
507 fsl_setup_indirect_pci(hose
, rsrc
.start
, rsrc
.start
+ 0x4,
508 PPC_INDIRECT_TYPE_BIG_ENDIAN
);
510 if (in_be32(&pci
->block_rev1
) < PCIE_IP_REV_3_0
)
511 hose
->indirect_type
|= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK
;
513 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
514 /* For PCIE read HEADER_TYPE to identify controler mode */
515 early_read_config_byte(hose
, 0, 0, PCI_HEADER_TYPE
, &hdr_type
);
516 if ((hdr_type
& 0x7f) != PCI_HEADER_TYPE_BRIDGE
)
520 /* For PCI read PROG to identify controller mode */
521 early_read_config_byte(hose
, 0, 0, PCI_CLASS_PROG
, &progif
);
522 if ((progif
& 1) == 1)
528 /* check PCI express link status */
529 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
530 hose
->indirect_type
|= PPC_INDIRECT_TYPE_EXT_REG
|
531 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS
;
532 if (fsl_pcie_check_link(hose
))
533 hose
->indirect_type
|= PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
536 printk(KERN_INFO
"Found FSL PCI host bridge at 0x%016llx. "
537 "Firmware bus number: %d->%d\n",
538 (unsigned long long)rsrc
.start
, hose
->first_busno
,
541 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
542 hose
, hose
->cfg_addr
, hose
->cfg_data
);
544 /* Interpret the "ranges" property */
545 /* This also maps the I/O region and sets isa_io/mem_base */
546 pci_process_bridge_OF_ranges(hose
, dev
, is_primary
);
548 /* Setup PEX window registers */
549 setup_pci_atmu(hose
);
554 iounmap(hose
->private_data
);
555 /* unmap cfg_data & cfg_addr separately if not on same page */
556 if (((unsigned long)hose
->cfg_data
& PAGE_MASK
) !=
557 ((unsigned long)hose
->cfg_addr
& PAGE_MASK
))
558 iounmap(hose
->cfg_data
);
559 iounmap(hose
->cfg_addr
);
560 pcibios_free_controller(hose
);
563 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
565 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, quirk_fsl_pcie_header
);
567 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
568 struct mpc83xx_pcie_priv
{
569 void __iomem
*cfg_type0
;
570 void __iomem
*cfg_type1
;
574 struct pex_inbound_window
{
582 * With the convention of u-boot, the PCIE outbound window 0 serves
583 * as configuration transactions outbound.
585 #define PEX_OUTWIN0_BAR 0xCA4
586 #define PEX_OUTWIN0_TAL 0xCA8
587 #define PEX_OUTWIN0_TAH 0xCAC
588 #define PEX_RC_INWIN_BASE 0xE60
589 #define PEX_RCIWARn_EN 0x1
591 static int mpc83xx_pcie_exclude_device(struct pci_bus
*bus
, unsigned int devfn
)
593 struct pci_controller
*hose
= pci_bus_to_host(bus
);
595 if (hose
->indirect_type
& PPC_INDIRECT_TYPE_NO_PCIE_LINK
)
596 return PCIBIOS_DEVICE_NOT_FOUND
;
598 * Workaround for the HW bug: for Type 0 configure transactions the
599 * PCI-E controller does not check the device number bits and just
600 * assumes that the device number bits are 0.
602 if (bus
->number
== hose
->first_busno
||
603 bus
->primary
== hose
->first_busno
) {
605 return PCIBIOS_DEVICE_NOT_FOUND
;
608 if (ppc_md
.pci_exclude_device
) {
609 if (ppc_md
.pci_exclude_device(hose
, bus
->number
, devfn
))
610 return PCIBIOS_DEVICE_NOT_FOUND
;
613 return PCIBIOS_SUCCESSFUL
;
616 static void __iomem
*mpc83xx_pcie_remap_cfg(struct pci_bus
*bus
,
617 unsigned int devfn
, int offset
)
619 struct pci_controller
*hose
= pci_bus_to_host(bus
);
620 struct mpc83xx_pcie_priv
*pcie
= hose
->dn
->data
;
621 u32 dev_base
= bus
->number
<< 24 | devfn
<< 16;
624 ret
= mpc83xx_pcie_exclude_device(bus
, devfn
);
631 if (bus
->number
== hose
->first_busno
)
632 return pcie
->cfg_type0
+ offset
;
634 if (pcie
->dev_base
== dev_base
)
637 out_le32(pcie
->cfg_type0
+ PEX_OUTWIN0_TAL
, dev_base
);
639 pcie
->dev_base
= dev_base
;
641 return pcie
->cfg_type1
+ offset
;
644 static int mpc83xx_pcie_read_config(struct pci_bus
*bus
, unsigned int devfn
,
645 int offset
, int len
, u32
*val
)
647 void __iomem
*cfg_addr
;
649 cfg_addr
= mpc83xx_pcie_remap_cfg(bus
, devfn
, offset
);
651 return PCIBIOS_DEVICE_NOT_FOUND
;
655 *val
= in_8(cfg_addr
);
658 *val
= in_le16(cfg_addr
);
661 *val
= in_le32(cfg_addr
);
665 return PCIBIOS_SUCCESSFUL
;
668 static int mpc83xx_pcie_write_config(struct pci_bus
*bus
, unsigned int devfn
,
669 int offset
, int len
, u32 val
)
671 struct pci_controller
*hose
= pci_bus_to_host(bus
);
672 void __iomem
*cfg_addr
;
674 cfg_addr
= mpc83xx_pcie_remap_cfg(bus
, devfn
, offset
);
676 return PCIBIOS_DEVICE_NOT_FOUND
;
678 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
679 if (offset
== PCI_PRIMARY_BUS
&& bus
->number
== hose
->first_busno
)
684 out_8(cfg_addr
, val
);
687 out_le16(cfg_addr
, val
);
690 out_le32(cfg_addr
, val
);
694 return PCIBIOS_SUCCESSFUL
;
697 static struct pci_ops mpc83xx_pcie_ops
= {
698 .read
= mpc83xx_pcie_read_config
,
699 .write
= mpc83xx_pcie_write_config
,
702 static int __init
mpc83xx_pcie_setup(struct pci_controller
*hose
,
703 struct resource
*reg
)
705 struct mpc83xx_pcie_priv
*pcie
;
709 pcie
= zalloc_maybe_bootmem(sizeof(*pcie
), GFP_KERNEL
);
713 pcie
->cfg_type0
= ioremap(reg
->start
, resource_size(reg
));
714 if (!pcie
->cfg_type0
)
717 cfg_bar
= in_le32(pcie
->cfg_type0
+ PEX_OUTWIN0_BAR
);
719 /* PCI-E isn't configured. */
724 pcie
->cfg_type1
= ioremap(cfg_bar
, 0x1000);
725 if (!pcie
->cfg_type1
)
728 WARN_ON(hose
->dn
->data
);
729 hose
->dn
->data
= pcie
;
730 hose
->ops
= &mpc83xx_pcie_ops
;
731 hose
->indirect_type
|= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK
;
733 out_le32(pcie
->cfg_type0
+ PEX_OUTWIN0_TAH
, 0);
734 out_le32(pcie
->cfg_type0
+ PEX_OUTWIN0_TAL
, 0);
736 if (fsl_pcie_check_link(hose
))
737 hose
->indirect_type
|= PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
741 iounmap(pcie
->cfg_type0
);
748 int __init
mpc83xx_add_bridge(struct device_node
*dev
)
752 struct pci_controller
*hose
;
753 struct resource rsrc_reg
;
754 struct resource rsrc_cfg
;
755 const int *bus_range
;
760 if (!of_device_is_available(dev
)) {
761 pr_warning("%s: disabled by the firmware.\n",
765 pr_debug("Adding PCI host bridge %s\n", dev
->full_name
);
767 /* Fetch host bridge registers address */
768 if (of_address_to_resource(dev
, 0, &rsrc_reg
)) {
769 printk(KERN_WARNING
"Can't get pci register base!\n");
773 memset(&rsrc_cfg
, 0, sizeof(rsrc_cfg
));
775 if (of_address_to_resource(dev
, 1, &rsrc_cfg
)) {
777 "No pci config register base in dev tree, "
780 * MPC83xx supports up to two host controllers
781 * one at 0x8500 has config space registers at 0x8300
782 * one at 0x8600 has config space registers at 0x8380
784 if ((rsrc_reg
.start
& 0xfffff) == 0x8500)
785 rsrc_cfg
.start
= (rsrc_reg
.start
& 0xfff00000) + 0x8300;
786 else if ((rsrc_reg
.start
& 0xfffff) == 0x8600)
787 rsrc_cfg
.start
= (rsrc_reg
.start
& 0xfff00000) + 0x8380;
790 * Controller at offset 0x8500 is primary
792 if ((rsrc_reg
.start
& 0xfffff) == 0x8500)
797 /* Get bus range if any */
798 bus_range
= of_get_property(dev
, "bus-range", &len
);
799 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
800 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
801 " bus 0\n", dev
->full_name
);
804 pci_add_flags(PCI_REASSIGN_ALL_BUS
);
805 hose
= pcibios_alloc_controller(dev
);
809 hose
->first_busno
= bus_range
? bus_range
[0] : 0;
810 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
812 if (of_device_is_compatible(dev
, "fsl,mpc8314-pcie")) {
813 ret
= mpc83xx_pcie_setup(hose
, &rsrc_reg
);
817 fsl_setup_indirect_pci(hose
, rsrc_cfg
.start
,
818 rsrc_cfg
.start
+ 4, 0);
821 printk(KERN_INFO
"Found FSL PCI host bridge at 0x%016llx. "
822 "Firmware bus number: %d->%d\n",
823 (unsigned long long)rsrc_reg
.start
, hose
->first_busno
,
826 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
827 hose
, hose
->cfg_addr
, hose
->cfg_data
);
829 /* Interpret the "ranges" property */
830 /* This also maps the I/O region and sets isa_io/mem_base */
831 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
835 pcibios_free_controller(hose
);
838 #endif /* CONFIG_PPC_83xx */
840 u64
fsl_pci_immrbar_base(struct pci_controller
*hose
)
842 #ifdef CONFIG_PPC_83xx
843 if (is_mpc83xx_pci
) {
844 struct mpc83xx_pcie_priv
*pcie
= hose
->dn
->data
;
845 struct pex_inbound_window
*in
;
848 /* Walk the Root Complex Inbound windows to match IMMR base */
849 in
= pcie
->cfg_type0
+ PEX_RC_INWIN_BASE
;
850 for (i
= 0; i
< 4; i
++) {
851 /* not enabled, skip */
852 if (!in_le32(&in
[i
].ar
) & PEX_RCIWARn_EN
)
855 if (get_immrbase() == in_le32(&in
[i
].tar
))
856 return (u64
)in_le32(&in
[i
].barh
) << 32 |
857 in_le32(&in
[i
].barl
);
860 printk(KERN_WARNING
"could not find PCI BAR matching IMMR\n");
864 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
865 if (!is_mpc83xx_pci
) {
868 pci_bus_read_config_dword(hose
->bus
,
869 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0
, &base
);
877 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
878 static const struct of_device_id pci_ids
[] = {
879 { .compatible
= "fsl,mpc8540-pci", },
880 { .compatible
= "fsl,mpc8548-pcie", },
881 { .compatible
= "fsl,mpc8610-pci", },
882 { .compatible
= "fsl,mpc8641-pcie", },
883 { .compatible
= "fsl,qoriq-pcie-v2.1", },
884 { .compatible
= "fsl,qoriq-pcie-v2.2", },
885 { .compatible
= "fsl,qoriq-pcie-v2.3", },
886 { .compatible
= "fsl,qoriq-pcie-v2.4", },
887 { .compatible
= "fsl,qoriq-pcie-v3.0", },
890 * The following entries are for compatibility with older device
893 { .compatible
= "fsl,p1022-pcie", },
894 { .compatible
= "fsl,p4080-pcie", },
899 struct device_node
*fsl_pci_primary
;
901 void fsl_pci_assign_primary(void)
903 struct device_node
*np
;
905 /* Callers can specify the primary bus using other means. */
909 /* If a PCI host bridge contains an ISA node, it's primary. */
910 np
= of_find_node_by_type(NULL
, "isa");
911 while ((fsl_pci_primary
= of_get_parent(np
))) {
913 np
= fsl_pci_primary
;
915 if (of_match_node(pci_ids
, np
) && of_device_is_available(np
))
920 * If there's no PCI host bridge with ISA, arbitrarily
921 * designate one as primary. This can go away once
922 * various bugs with primary-less systems are fixed.
924 for_each_matching_node(np
, pci_ids
) {
925 if (of_device_is_available(np
)) {
926 fsl_pci_primary
= np
;
933 static int fsl_pci_probe(struct platform_device
*pdev
)
936 struct device_node
*node
;
937 #ifdef CONFIG_SWIOTLB
938 struct pci_controller
*hose
;
941 node
= pdev
->dev
.of_node
;
942 ret
= fsl_add_bridge(pdev
, fsl_pci_primary
== node
);
944 #ifdef CONFIG_SWIOTLB
946 hose
= pci_find_hose_for_OF_device(pdev
->dev
.of_node
);
949 * if we couldn't map all of DRAM via the dma windows
950 * we need SWIOTLB to handle buffers located outside of
951 * dma capable memory region
953 if (memblock_end_of_DRAM() - 1 > hose
->dma_window_base_cur
+
954 hose
->dma_window_size
)
955 ppc_swiotlb_enable
= 1;
959 mpc85xx_pci_err_probe(pdev
);
965 static int fsl_pci_resume(struct device
*dev
)
967 struct pci_controller
*hose
;
968 struct resource pci_rsrc
;
970 hose
= pci_find_hose_for_OF_device(dev
->of_node
);
974 if (of_address_to_resource(dev
->of_node
, 0, &pci_rsrc
)) {
975 dev_err(dev
, "Get pci register base failed.");
979 setup_pci_atmu(hose
);
984 static const struct dev_pm_ops pci_pm_ops
= {
985 .resume
= fsl_pci_resume
,
988 #define PCI_PM_OPS (&pci_pm_ops)
992 #define PCI_PM_OPS NULL
996 static struct platform_driver fsl_pci_driver
= {
1000 .of_match_table
= pci_ids
,
1002 .probe
= fsl_pci_probe
,
1005 static int __init
fsl_pci_init(void)
1007 return platform_driver_register(&fsl_pci_driver
);
1009 arch_initcall(fsl_pci_init
);