arch/powerpc/platforms/powermac/smp.c

   1 /*
   2  * SMP support for power macintosh.
   3  *
   4  * We support both the old "powersurge" SMP architecture
   5  * and the current Core99 (G4 PowerMac) machines.
   6  *
   7  * Note that we don't support the very first rev. of
   8  * Apple/DayStar 2 CPUs board, the one with the funky
   9  * watchdog. Hopefully, none of these should be there except
  10  * maybe internally to Apple. I should probably still add some
  11  * code to detect this card though and disable SMP. --BenH.
  12  *
  13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
  14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
  15  *
  16  * Support for DayStar quad CPU cards
  17  * Copyright (C) XLR8, Inc. 1994-2000
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  */
  24 #include <linux/kernel.h>
  25 #include <linux/sched.h>
  26 #include <linux/smp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/kernel_stat.h>
  29 #include <linux/delay.h>
  30 #include <linux/init.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/cpu.h>
  35 #include <linux/compiler.h>
  36
  37 #include <asm/ptrace.h>
  38 #include <linux/atomic.h>
  39 #include <asm/code-patching.h>
  40 #include <asm/irq.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/sections.h>
  44 #include <asm/io.h>
  45 #include <asm/prom.h>
  46 #include <asm/smp.h>
  47 #include <asm/machdep.h>
  48 #include <asm/pmac_feature.h>
  49 #include <asm/time.h>
  50 #include <asm/mpic.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/keylargo.h>
  53 #include <asm/pmac_low_i2c.h>
  54 #include <asm/pmac_pfunc.h>
  55
  56 #include "pmac.h"
  57
  58 #undef DEBUG
  59
  60 #ifdef DEBUG
  61 #define DBG(fmt...) udbg_printf(fmt)
  62 #else
  63 #define DBG(fmt...)
  64 #endif
  65
  66 extern void __secondary_start_pmac_0(void);
  67 extern int pmac_pfunc_base_install(void);
  68
  69 static void (*pmac_tb_freeze)(int freeze);
  70 static u64 timebase;
  71 static int tb_req;
  72
  73 #ifdef CONFIG_PPC_PMAC32_PSURGE
  74
  75 /*
  76  * Powersurge (old powermac SMP) support.
  77  */
  78
  79 /* Addresses for powersurge registers */
  80 #define HAMMERHEAD_BASE         0xf8000000
  81 #define HHEAD_CONFIG            0x90
  82 #define HHEAD_SEC_INTR          0xc0
  83
  84 /* register for interrupting the primary processor on the powersurge */
  85 /* N.B. this is actually the ethernet ROM! */
  86 #define PSURGE_PRI_INTR         0xf3019000
  87
  88 /* register for storing the start address for the secondary processor */
  89 /* N.B. this is the PCI config space address register for the 1st bridge */
  90 #define PSURGE_START            0xf2800000
  91
  92 /* Daystar/XLR8 4-CPU card */
  93 #define PSURGE_QUAD_REG_ADDR    0xf8800000
  94
  95 #define PSURGE_QUAD_IRQ_SET     0
  96 #define PSURGE_QUAD_IRQ_CLR     1
  97 #define PSURGE_QUAD_IRQ_PRIMARY 2
  98 #define PSURGE_QUAD_CKSTOP_CTL  3
  99 #define PSURGE_QUAD_PRIMARY_ARB 4
 100 #define PSURGE_QUAD_BOARD_ID    6
 101 #define PSURGE_QUAD_WHICH_CPU   7
 102 #define PSURGE_QUAD_CKSTOP_RDBK 8
 103 #define PSURGE_QUAD_RESET_CTL   11
 104
 105 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
 106 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
 107 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
 108 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
 109
 110 /* virtual addresses for the above */
 111 static volatile u8 __iomem *hhead_base;
 112 static volatile u8 __iomem *quad_base;
 113 static volatile u32 __iomem *psurge_pri_intr;
 114 static volatile u8 __iomem *psurge_sec_intr;
 115 static volatile u32 __iomem *psurge_start;
 116
 117 /* values for psurge_type */
 118 #define PSURGE_NONE             -1
 119 #define PSURGE_DUAL             0
 120 #define PSURGE_QUAD_OKEE        1
 121 #define PSURGE_QUAD_COTTON      2
 122 #define PSURGE_QUAD_ICEGRASS    3
 123
 124 /* what sort of powersurge board we have */
 125 static int psurge_type = PSURGE_NONE;
 126
 127 /* irq for secondary cpus to report */
 128 static struct irq_domain *psurge_host;
 129 int psurge_secondary_virq;
 130
 131 /*
 132  * Set and clear IPIs for powersurge.
 133  */
 134 static inline void psurge_set_ipi(int cpu)
 135 {
 136         if (psurge_type == PSURGE_NONE)
 137                 return;
 138         if (cpu == 0)
 139                 in_be32(psurge_pri_intr);
 140         else if (psurge_type == PSURGE_DUAL)
 141                 out_8(psurge_sec_intr, 0);
 142         else
 143                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
 144 }
 145
 146 static inline void psurge_clr_ipi(int cpu)
 147 {
 148         if (cpu > 0) {
 149                 switch(psurge_type) {
 150                 case PSURGE_DUAL:
 151                         out_8(psurge_sec_intr, ~0);
 152                 case PSURGE_NONE:
 153                         break;
 154                 default:
 155                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
 156                 }
 157         }
 158 }
 159
 160 /*
 161  * On powersurge (old SMP powermac architecture) we don't have
 162  * separate IPIs for separate messages like openpic does.  Instead
 163  * use the generic demux helpers
 164  *  -- paulus.
 165  */
 166 static irqreturn_t psurge_ipi_intr(int irq, void *d)
 167 {
 168         psurge_clr_ipi(smp_processor_id());
 169         smp_ipi_demux();
 170
 171         return IRQ_HANDLED;
 172 }
 173
 174 static void smp_psurge_cause_ipi(int cpu, unsigned long data)
 175 {
 176         psurge_set_ipi(cpu);
 177 }
 178
 179 static int psurge_host_map(struct irq_domain *h, unsigned int virq,
 180                          irq_hw_number_t hw)
 181 {
 182         irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq);
 183
 184         return 0;
 185 }
 186
 187 static const struct irq_domain_ops psurge_host_ops = {
 188         .map    = psurge_host_map,
 189 };
 190
 191 static int psurge_secondary_ipi_init(void)
 192 {
 193         int rc = -ENOMEM;
 194
 195         psurge_host = irq_domain_add_nomap(NULL, 0, &psurge_host_ops, NULL);
 196
 197         if (psurge_host)
 198                 psurge_secondary_virq = irq_create_direct_mapping(psurge_host);
 199
 200         if (psurge_secondary_virq)
 201                 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr,
 202                         IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL);
 203
 204         if (rc)
 205                 pr_err("Failed to setup secondary cpu IPI\n");
 206
 207         return rc;
 208 }
 209
 210 /*
 211  * Determine a quad card presence. We read the board ID register, we
 212  * force the data bus to change to something else, and we read it again.
 213  * It it's stable, then the register probably exist (ugh !)
 214  */
 215 static int __init psurge_quad_probe(void)
 216 {
 217         int type;
 218         unsigned int i;
 219
 220         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
 221         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
 222             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 223                 return PSURGE_DUAL;
 224
 225         /* looks OK, try a slightly more rigorous test */
 226         /* bogus is not necessarily cacheline-aligned,
 227            though I don't suppose that really matters.  -- paulus */
 228         for (i = 0; i < 100; i++) {
 229                 volatile u32 bogus[8];
 230                 bogus[(0+i)%8] = 0x00000000;
 231                 bogus[(1+i)%8] = 0x55555555;
 232                 bogus[(2+i)%8] = 0xFFFFFFFF;
 233                 bogus[(3+i)%8] = 0xAAAAAAAA;
 234                 bogus[(4+i)%8] = 0x33333333;
 235                 bogus[(5+i)%8] = 0xCCCCCCCC;
 236                 bogus[(6+i)%8] = 0xCCCCCCCC;
 237                 bogus[(7+i)%8] = 0x33333333;
 238                 wmb();
 239                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
 240                 mb();
 241                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 242                         return PSURGE_DUAL;
 243         }
 244         return type;
 245 }
 246
 247 static void __init psurge_quad_init(void)
 248 {
 249         int procbits;
 250
 251         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
 252         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
 253         if (psurge_type == PSURGE_QUAD_ICEGRASS)
 254                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 255         else
 256                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
 257         mdelay(33);
 258         out_8(psurge_sec_intr, ~0);
 259         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
 260         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 261         if (psurge_type != PSURGE_QUAD_ICEGRASS)
 262                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
 263         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
 264         mdelay(33);
 265         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
 266         mdelay(33);
 267         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
 268         mdelay(33);
 269 }
 270
 271 static int __init smp_psurge_probe(void)
 272 {
 273         int i, ncpus;
 274         struct device_node *dn;
 275
 276         /* We don't do SMP on the PPC601 -- paulus */
 277         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
 278                 return 1;
 279
 280         /*
 281          * The powersurge cpu board can be used in the generation
 282          * of powermacs that have a socket for an upgradeable cpu card,
 283          * including the 7500, 8500, 9500, 9600.
 284          * The device tree doesn't tell you if you have 2 cpus because
 285          * OF doesn't know anything about the 2nd processor.
 286          * Instead we look for magic bits in magic registers,
 287          * in the hammerhead memory controller in the case of the
 288          * dual-cpu powersurge board.  -- paulus.
 289          */
 290         dn = of_find_node_by_name(NULL, "hammerhead");
 291         if (dn == NULL)
 292                 return 1;
 293         of_node_put(dn);
 294
 295         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
 296         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
 297         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
 298
 299         psurge_type = psurge_quad_probe();
 300         if (psurge_type != PSURGE_DUAL) {
 301                 psurge_quad_init();
 302                 /* All released cards using this HW design have 4 CPUs */
 303                 ncpus = 4;
 304                 /* No sure how timebase sync works on those, let's use SW */
 305                 smp_ops->give_timebase = smp_generic_give_timebase;
 306                 smp_ops->take_timebase = smp_generic_take_timebase;
 307         } else {
 308                 iounmap(quad_base);
 309                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
 310                         /* not a dual-cpu card */
 311                         iounmap(hhead_base);
 312                         psurge_type = PSURGE_NONE;
 313                         return 1;
 314                 }
 315                 ncpus = 2;
 316         }
 317
 318         if (psurge_secondary_ipi_init())
 319                 return 1;
 320
 321         psurge_start = ioremap(PSURGE_START, 4);
 322         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
 323
 324         /* This is necessary because OF doesn't know about the
 325          * secondary cpu(s), and thus there aren't nodes in the
 326          * device tree for them, and smp_setup_cpu_maps hasn't
 327          * set their bits in cpu_present_mask.
 328          */
 329         if (ncpus > NR_CPUS)
 330                 ncpus = NR_CPUS;
 331         for (i = 1; i < ncpus ; ++i)
 332                 set_cpu_present(i, true);
 333
 334         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
 335
 336         return ncpus;
 337 }
 338
 339 static int __init smp_psurge_kick_cpu(int nr)
 340 {
 341         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
 342         unsigned long a, flags;
 343         int i, j;
 344
 345         /* Defining this here is evil ... but I prefer hiding that
 346          * crap to avoid giving people ideas that they can do the
 347          * same.
 348          */
 349         extern volatile unsigned int cpu_callin_map[NR_CPUS];
 350
 351         /* may need to flush here if secondary bats aren't setup */
 352         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
 353                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
 354         asm volatile("sync");
 355
 356         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
 357
 358         /* This is going to freeze the timeebase, we disable interrupts */
 359         local_irq_save(flags);
 360
 361         out_be32(psurge_start, start);
 362         mb();
 363
 364         psurge_set_ipi(nr);
 365
 366         /*
 367          * We can't use udelay here because the timebase is now frozen.
 368          */
 369         for (i = 0; i < 2000; ++i)
 370                 asm volatile("nop" : : : "memory");
 371         psurge_clr_ipi(nr);
 372
 373         /*
 374          * Also, because the timebase is frozen, we must not return to the
 375          * caller which will try to do udelay's etc... Instead, we wait -here-
 376          * for the CPU to callin.
 377          */
 378         for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
 379                 for (j = 1; j < 10000; j++)
 380                         asm volatile("nop" : : : "memory");
 381                 asm volatile("sync" : : : "memory");
 382         }
 383         if (!cpu_callin_map[nr])
 384                 goto stuck;
 385
 386         /* And we do the TB sync here too for standard dual CPU cards */
 387         if (psurge_type == PSURGE_DUAL) {
 388                 while(!tb_req)
 389                         barrier();
 390                 tb_req = 0;
 391                 mb();
 392                 timebase = get_tb();
 393                 mb();
 394                 while (timebase)
 395                         barrier();
 396                 mb();
 397         }
 398  stuck:
 399         /* now interrupt the secondary, restarting both TBs */
 400         if (psurge_type == PSURGE_DUAL)
 401                 psurge_set_ipi(1);
 402
 403         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
 404
 405         return 0;
 406 }
 407
 408 static struct irqaction psurge_irqaction = {
 409         .handler = psurge_ipi_intr,
 410         .flags = IRQF_PERCPU | IRQF_NO_THREAD,
 411         .name = "primary IPI",
 412 };
 413
 414 static void __init smp_psurge_setup_cpu(int cpu_nr)
 415 {
 416         if (cpu_nr != 0 || !psurge_start)
 417                 return;
 418
 419         /* reset the entry point so if we get another intr we won't
 420          * try to startup again */
 421         out_be32(psurge_start, 0x100);
 422         if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
 423                 printk(KERN_ERR "Couldn't get primary IPI interrupt");
 424 }
 425
 426 void __init smp_psurge_take_timebase(void)
 427 {
 428         if (psurge_type != PSURGE_DUAL)
 429                 return;
 430
 431         tb_req = 1;
 432         mb();
 433         while (!timebase)
 434                 barrier();
 435         mb();
 436         set_tb(timebase >> 32, timebase & 0xffffffff);
 437         timebase = 0;
 438         mb();
 439         set_dec(tb_ticks_per_jiffy/2);
 440 }
 441
 442 void __init smp_psurge_give_timebase(void)
 443 {
 444         /* Nothing to do here */
 445 }
 446
 447 /* PowerSurge-style Macs */
 448 struct smp_ops_t psurge_smp_ops = {
 449         .message_pass   = NULL, /* Use smp_muxed_ipi_message_pass */
 450         .cause_ipi      = smp_psurge_cause_ipi,
 451         .probe          = smp_psurge_probe,
 452         .kick_cpu       = smp_psurge_kick_cpu,
 453         .setup_cpu      = smp_psurge_setup_cpu,
 454         .give_timebase  = smp_psurge_give_timebase,
 455         .take_timebase  = smp_psurge_take_timebase,
 456 };
 457 #endif /* CONFIG_PPC_PMAC32_PSURGE */
 458
 459 /*
 460  * Core 99 and later support
 461  */
 462
 463
 464 static void smp_core99_give_timebase(void)
 465 {
 466         unsigned long flags;
 467
 468         local_irq_save(flags);
 469
 470         while(!tb_req)
 471                 barrier();
 472         tb_req = 0;
 473         (*pmac_tb_freeze)(1);
 474         mb();
 475         timebase = get_tb();
 476         mb();
 477         while (timebase)
 478                 barrier();
 479         mb();
 480         (*pmac_tb_freeze)(0);
 481         mb();
 482
 483         local_irq_restore(flags);
 484 }
 485
 486
 487 static void smp_core99_take_timebase(void)
 488 {
 489         unsigned long flags;
 490
 491         local_irq_save(flags);
 492
 493         tb_req = 1;
 494         mb();
 495         while (!timebase)
 496                 barrier();
 497         mb();
 498         set_tb(timebase >> 32, timebase & 0xffffffff);
 499         timebase = 0;
 500         mb();
 501
 502         local_irq_restore(flags);
 503 }
 504
 505 #ifdef CONFIG_PPC64
 506 /*
 507  * G5s enable/disable the timebase via an i2c-connected clock chip.
 508  */
 509 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
 510 static u8 pmac_tb_pulsar_addr;
 511
 512 static void smp_core99_cypress_tb_freeze(int freeze)
 513 {
 514         u8 data;
 515         int rc;
 516
 517         /* Strangely, the device-tree says address is 0xd2, but darwin
 518          * accesses 0xd0 ...
 519          */
 520         pmac_i2c_setmode(pmac_tb_clock_chip_host,
 521                          pmac_i2c_mode_combined);
 522         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 523                            0xd0 | pmac_i2c_read,
 524                            1, 0x81, &data, 1);
 525         if (rc != 0)
 526                 goto bail;
 527
 528         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
 529
 530         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
 531         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 532                            0xd0 | pmac_i2c_write,
 533                            1, 0x81, &data, 1);
 534
 535  bail:
 536         if (rc != 0) {
 537                 printk("Cypress Timebase %s rc: %d\n",
 538                        freeze ? "freeze" : "unfreeze", rc);
 539                 panic("Timebase freeze failed !\n");
 540         }
 541 }
 542
 543
 544 static void smp_core99_pulsar_tb_freeze(int freeze)
 545 {
 546         u8 data;
 547         int rc;
 548
 549         pmac_i2c_setmode(pmac_tb_clock_chip_host,
 550                          pmac_i2c_mode_combined);
 551         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 552                            pmac_tb_pulsar_addr | pmac_i2c_read,
 553                            1, 0x2e, &data, 1);
 554         if (rc != 0)
 555                 goto bail;
 556
 557         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
 558
 559         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
 560         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 561                            pmac_tb_pulsar_addr | pmac_i2c_write,
 562                            1, 0x2e, &data, 1);
 563  bail:
 564         if (rc != 0) {
 565                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
 566                        freeze ? "freeze" : "unfreeze", rc);
 567                 panic("Timebase freeze failed !\n");
 568         }
 569 }
 570
 571 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
 572 {
 573         struct device_node *cc = NULL;
 574         struct device_node *p;
 575         const char *name = NULL;
 576         const u32 *reg;
 577         int ok;
 578
 579         /* Look for the clock chip */
 580         while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
 581                 p = of_get_parent(cc);
 582                 ok = p && of_device_is_compatible(p, "uni-n-i2c");
 583                 of_node_put(p);
 584                 if (!ok)
 585                         continue;
 586
 587                 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
 588                 if (pmac_tb_clock_chip_host == NULL)
 589                         continue;
 590                 reg = of_get_property(cc, "reg", NULL);
 591                 if (reg == NULL)
 592                         continue;
 593                 switch (*reg) {
 594                 case 0xd2:
 595                         if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
 596                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 597                                 pmac_tb_pulsar_addr = 0xd2;
 598                                 name = "Pulsar";
 599                         } else if (of_device_is_compatible(cc, "cy28508")) {
 600                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
 601                                 name = "Cypress";
 602                         }
 603                         break;
 604                 case 0xd4:
 605                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 606                         pmac_tb_pulsar_addr = 0xd4;
 607                         name = "Pulsar";
 608                         break;
 609                 }
 610                 if (pmac_tb_freeze != NULL)
 611                         break;
 612         }
 613         if (pmac_tb_freeze != NULL) {
 614                 /* Open i2c bus for synchronous access */
 615                 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
 616                         printk(KERN_ERR "Failed top open i2c bus for clock"
 617                                " sync, fallback to software sync !\n");
 618                         goto no_i2c_sync;
 619                 }
 620                 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
 621                        name);
 622                 return;
 623         }
 624  no_i2c_sync:
 625         pmac_tb_freeze = NULL;
 626         pmac_tb_clock_chip_host = NULL;
 627 }
 628
 629
 630
 631 /*
 632  * Newer G5s uses a platform function
 633  */
 634
 635 static void smp_core99_pfunc_tb_freeze(int freeze)
 636 {
 637         struct device_node *cpus;
 638         struct pmf_args args;
 639
 640         cpus = of_find_node_by_path("/cpus");
 641         BUG_ON(cpus == NULL);
 642         args.count = 1;
 643         args.u[0].v = !freeze;
 644         pmf_call_function(cpus, "cpu-timebase", &args);
 645         of_node_put(cpus);
 646 }
 647
 648 #else /* CONFIG_PPC64 */
 649
 650 /*
 651  * SMP G4 use a GPIO to enable/disable the timebase.
 652  */
 653
 654 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
 655
 656 static void smp_core99_gpio_tb_freeze(int freeze)
 657 {
 658         if (freeze)
 659                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
 660         else
 661                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
 662         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
 663 }
 664
 665
 666 #endif /* !CONFIG_PPC64 */
 667
 668 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
 669 volatile static long int core99_l2_cache;
 670 volatile static long int core99_l3_cache;
 671
 672 static void core99_init_caches(int cpu)
 673 {
 674 #ifndef CONFIG_PPC64
 675         if (!cpu_has_feature(CPU_FTR_L2CR))
 676                 return;
 677
 678         if (cpu == 0) {
 679                 core99_l2_cache = _get_L2CR();
 680                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
 681         } else {
 682                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
 683                 _set_L2CR(0);
 684                 _set_L2CR(core99_l2_cache);
 685                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
 686         }
 687
 688         if (!cpu_has_feature(CPU_FTR_L3CR))
 689                 return;
 690
 691         if (cpu == 0){
 692                 core99_l3_cache = _get_L3CR();
 693                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
 694         } else {
 695                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
 696                 _set_L3CR(0);
 697                 _set_L3CR(core99_l3_cache);
 698                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
 699         }
 700 #endif /* !CONFIG_PPC64 */
 701 }
 702
 703 static void __init smp_core99_setup(int ncpus)
 704 {
 705 #ifdef CONFIG_PPC64
 706
 707         /* i2c based HW sync on some G5s */
 708         if (of_machine_is_compatible("PowerMac7,2") ||
 709             of_machine_is_compatible("PowerMac7,3") ||
 710             of_machine_is_compatible("RackMac3,1"))
 711                 smp_core99_setup_i2c_hwsync(ncpus);
 712
 713         /* pfunc based HW sync on recent G5s */
 714         if (pmac_tb_freeze == NULL) {
 715                 struct device_node *cpus =
 716                         of_find_node_by_path("/cpus");
 717                 if (cpus &&
 718                     of_get_property(cpus, "platform-cpu-timebase", NULL)) {
 719                         pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
 720                         printk(KERN_INFO "Processor timebase sync using"
 721                                " platform function\n");
 722                 }
 723         }
 724
 725 #else /* CONFIG_PPC64 */
 726
 727         /* GPIO based HW sync on ppc32 Core99 */
 728         if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
 729                 struct device_node *cpu;
 730                 const u32 *tbprop = NULL;
 731
 732                 core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
 733                 cpu = of_find_node_by_type(NULL, "cpu");
 734                 if (cpu != NULL) {
 735                         tbprop = of_get_property(cpu, "timebase-enable", NULL);
 736                         if (tbprop)
 737                                 core99_tb_gpio = *tbprop;
 738                         of_node_put(cpu);
 739                 }
 740                 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
 741                 printk(KERN_INFO "Processor timebase sync using"
 742                        " GPIO 0x%02x\n", core99_tb_gpio);
 743         }
 744
 745 #endif /* CONFIG_PPC64 */
 746
 747         /* No timebase sync, fallback to software */
 748         if (pmac_tb_freeze == NULL) {
 749                 smp_ops->give_timebase = smp_generic_give_timebase;
 750                 smp_ops->take_timebase = smp_generic_take_timebase;
 751                 printk(KERN_INFO "Processor timebase sync using software\n");
 752         }
 753
 754 #ifndef CONFIG_PPC64
 755         {
 756                 int i;
 757
 758                 /* XXX should get this from reg properties */
 759                 for (i = 1; i < ncpus; ++i)
 760                         set_hard_smp_processor_id(i, i);
 761         }
 762 #endif
 763
 764         /* 32 bits SMP can't NAP */
 765         if (!of_machine_is_compatible("MacRISC4"))
 766                 powersave_nap = 0;
 767 }
 768
 769 static int __init smp_core99_probe(void)
 770 {
 771         struct device_node *cpus;
 772         int ncpus = 0;
 773
 774         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
 775
 776         /* Count CPUs in the device-tree */
 777         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
 778                 ++ncpus;
 779
 780         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
 781
 782         /* Nothing more to do if less than 2 of them */
 783         if (ncpus <= 1)
 784                 return 1;
 785
 786         /* We need to perform some early initialisations before we can start
 787          * setting up SMP as we are running before initcalls
 788          */
 789         pmac_pfunc_base_install();
 790         pmac_i2c_init();
 791
 792         /* Setup various bits like timebase sync method, ability to nap, ... */
 793         smp_core99_setup(ncpus);
 794
 795         /* Install IPIs */
 796         mpic_request_ipis();
 797
 798         /* Collect l2cr and l3cr values from CPU 0 */
 799         core99_init_caches(0);
 800
 801         return ncpus;
 802 }
 803
 804 static int smp_core99_kick_cpu(int nr)
 805 {
 806         unsigned int save_vector;
 807         unsigned long target, flags;
 808         unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
 809
 810         if (nr < 0 || nr > 3)
 811                 return -ENOENT;
 812
 813         if (ppc_md.progress)
 814                 ppc_md.progress("smp_core99_kick_cpu", 0x346);
 815
 816         local_irq_save(flags);
 817
 818         /* Save reset vector */
 819         save_vector = *vector;
 820
 821         /* Setup fake reset vector that does
 822          *   b __secondary_start_pmac_0 + nr*8
 823          */
 824         target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
 825         patch_branch(vector, target, BRANCH_SET_LINK);
 826
 827         /* Put some life in our friend */
 828         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
 829
 830         /* FIXME: We wait a bit for the CPU to take the exception, I should
 831          * instead wait for the entry code to set something for me. Well,
 832          * ideally, all that crap will be done in prom.c and the CPU left
 833          * in a RAM-based wait loop like CHRP.
 834          */
 835         mdelay(1);
 836
 837         /* Restore our exception vector */
 838         *vector = save_vector;
 839         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 840
 841         local_irq_restore(flags);
 842         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
 843
 844         return 0;
 845 }
 846
 847 static void smp_core99_setup_cpu(int cpu_nr)
 848 {
 849         /* Setup L2/L3 */
 850         if (cpu_nr != 0)
 851                 core99_init_caches(cpu_nr);
 852
 853         /* Setup openpic */
 854         mpic_setup_this_cpu();
 855 }
 856
 857 #ifdef CONFIG_PPC64
 858 #ifdef CONFIG_HOTPLUG_CPU
 859 static int smp_core99_cpu_notify(struct notifier_block *self,
 860                                  unsigned long action, void *hcpu)
 861 {
 862         int rc;
 863
 864         switch(action) {
 865         case CPU_UP_PREPARE:
 866         case CPU_UP_PREPARE_FROZEN:
 867                 /* Open i2c bus if it was used for tb sync */
 868                 if (pmac_tb_clock_chip_host) {
 869                         rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1);
 870                         if (rc) {
 871                                 pr_err("Failed to open i2c bus for time sync\n");
 872                                 return notifier_from_errno(rc);
 873                         }
 874                 }
 875                 break;
 876         case CPU_ONLINE:
 877         case CPU_UP_CANCELED:
 878                 /* Close i2c bus if it was used for tb sync */
 879                 if (pmac_tb_clock_chip_host)
 880                         pmac_i2c_close(pmac_tb_clock_chip_host);
 881                 break;
 882         default:
 883                 break;
 884         }
 885         return NOTIFY_OK;
 886 }
 887
 888 static struct notifier_block __cpuinitdata smp_core99_cpu_nb = {
 889         .notifier_call  = smp_core99_cpu_notify,
 890 };
 891 #endif /* CONFIG_HOTPLUG_CPU */
 892
 893 static void __init smp_core99_bringup_done(void)
 894 {
 895         extern void g5_phy_disable_cpu1(void);
 896
 897         /* Close i2c bus if it was used for tb sync */
 898         if (pmac_tb_clock_chip_host)
 899                 pmac_i2c_close(pmac_tb_clock_chip_host);
 900
 901         /* If we didn't start the second CPU, we must take
 902          * it off the bus.
 903          */
 904         if (of_machine_is_compatible("MacRISC4") &&
 905             num_online_cpus() < 2) {
 906                 set_cpu_present(1, false);
 907                 g5_phy_disable_cpu1();
 908         }
 909 #ifdef CONFIG_HOTPLUG_CPU
 910         register_cpu_notifier(&smp_core99_cpu_nb);
 911 #endif
 912
 913         if (ppc_md.progress)
 914                 ppc_md.progress("smp_core99_bringup_done", 0x349);
 915 }
 916 #endif /* CONFIG_PPC64 */
 917
 918 #ifdef CONFIG_HOTPLUG_CPU
 919
 920 static int smp_core99_cpu_disable(void)
 921 {
 922         int rc = generic_cpu_disable();
 923         if (rc)
 924                 return rc;
 925
 926         mpic_cpu_set_priority(0xf);
 927
 928         return 0;
 929 }
 930
 931 #ifdef CONFIG_PPC32
 932
 933 static void pmac_cpu_die(void)
 934 {
 935         int cpu = smp_processor_id();
 936
 937         local_irq_disable();
 938         idle_task_exit();
 939         pr_debug("CPU%d offline\n", cpu);
 940         generic_set_cpu_dead(cpu);
 941         smp_wmb();
 942         mb();
 943         low_cpu_die();
 944 }
 945
 946 #else /* CONFIG_PPC32 */
 947
 948 static void pmac_cpu_die(void)
 949 {
 950         int cpu = smp_processor_id();
 951
 952         local_irq_disable();
 953         idle_task_exit();
 954
 955         /*
 956          * turn off as much as possible, we'll be
 957          * kicked out as this will only be invoked
 958          * on core99 platforms for now ...
 959          */
 960
 961         printk(KERN_INFO "CPU#%d offline\n", cpu);
 962         generic_set_cpu_dead(cpu);
 963         smp_wmb();
 964
 965         /*
 966          * Re-enable interrupts. The NAP code needs to enable them
 967          * anyways, do it now so we deal with the case where one already
 968          * happened while soft-disabled.
 969          * We shouldn't get any external interrupts, only decrementer, and the
 970          * decrementer handler is safe for use on offline CPUs
 971          */
 972         local_irq_enable();
 973
 974         while (1) {
 975                 /* let's not take timer interrupts too often ... */
 976                 set_dec(0x7fffffff);
 977
 978                 /* Enter NAP mode */
 979                 power4_idle();
 980         }
 981 }
 982
 983 #endif /* else CONFIG_PPC32 */
 984 #endif /* CONFIG_HOTPLUG_CPU */
 985
 986 /* Core99 Macs (dual G4s and G5s) */
 987 struct smp_ops_t core99_smp_ops = {
 988         .message_pass   = smp_mpic_message_pass,
 989         .probe          = smp_core99_probe,
 990 #ifdef CONFIG_PPC64
 991         .bringup_done   = smp_core99_bringup_done,
 992 #endif
 993         .kick_cpu       = smp_core99_kick_cpu,
 994         .setup_cpu      = smp_core99_setup_cpu,
 995         .give_timebase  = smp_core99_give_timebase,
 996         .take_timebase  = smp_core99_take_timebase,
 997 #if defined(CONFIG_HOTPLUG_CPU)
 998         .cpu_disable    = smp_core99_cpu_disable,
 999         .cpu_die        = generic_cpu_die,
1000 #endif
1001 };
1002
1003 void __init pmac_setup_smp(void)
1004 {
1005         struct device_node *np;
1006
1007         /* Check for Core99 */
1008         np = of_find_node_by_name(NULL, "uni-n");
1009         if (!np)
1010                 np = of_find_node_by_name(NULL, "u3");
1011         if (!np)
1012                 np = of_find_node_by_name(NULL, "u4");
1013         if (np) {
1014                 of_node_put(np);
1015                 smp_ops = &core99_smp_ops;
1016         }
1017 #ifdef CONFIG_PPC_PMAC32_PSURGE
1018         else {
1019                 /* We have to set bits in cpu_possible_mask here since the
1020                  * secondary CPU(s) aren't in the device tree. Various
1021                  * things won't be initialized for CPUs not in the possible
1022                  * map, so we really need to fix it up here.
1023                  */
1024                 int cpu;
1025
1026                 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
1027                         set_cpu_possible(cpu, true);
1028                 smp_ops = &psurge_smp_ops;
1029         }
1030 #endif /* CONFIG_PPC_PMAC32_PSURGE */
1031
1032 #ifdef CONFIG_HOTPLUG_CPU
1033         ppc_md.cpu_die = pmac_cpu_die;
1034 #endif
1035 }
1036
1037