2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
4 * iSeries specific routines for PCI.
6 * Based on code from pci.c and iSeries_pci.c 32bit
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/ide.h>
28 #include <linux/pci.h>
33 #include <asm/machdep.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/ppcdebug.h>
36 #include <asm/iommu.h>
38 #include <asm/iSeries/HvCallPci.h>
39 #include <asm/iSeries/HvCallXm.h>
40 #include <asm/iSeries/iSeries_irq.h>
41 #include <asm/iSeries/iSeries_pci.h>
42 #include <asm/iSeries/mf.h>
44 #include <asm/ppc-pci.h>
46 extern unsigned long io_page_mask
;
49 * Forward declares of prototypes.
51 static struct device_node
*find_Device_Node(int bus
, int devfn
);
52 static void scan_PHB_slots(struct pci_controller
*Phb
);
53 static void scan_EADS_bridge(HvBusNumber Bus
, HvSubBusNumber SubBus
, int IdSel
);
54 static int scan_bridge_slot(HvBusNumber Bus
, struct HvCallPci_BridgeInfo
*Info
);
56 LIST_HEAD(iSeries_Global_Device_List
);
58 static int DeviceCount
;
60 /* Counters and control flags. */
61 static long Pci_Io_Read_Count
;
62 static long Pci_Io_Write_Count
;
64 static long Pci_Cfg_Read_Count
;
65 static long Pci_Cfg_Write_Count
;
67 static long Pci_Error_Count
;
69 static int Pci_Retry_Max
= 3; /* Only retry 3 times */
70 static int Pci_Error_Flag
= 1; /* Set Retry Error on. */
72 static struct pci_ops iSeries_pci_ops
;
76 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
78 #define IOMM_TABLE_MAX_ENTRIES 1024
79 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
80 #define BASE_IO_MEMORY 0xE000000000000000UL
82 static unsigned long max_io_memory
= 0xE000000000000000UL
;
83 static long current_iomm_table_entry
;
88 static struct device_node
**iomm_table
;
89 static u8
*iobar_table
;
92 * Static and Global variables
94 static char *pci_io_text
= "iSeries PCI I/O";
95 static DEFINE_SPINLOCK(iomm_table_lock
);
98 * iomm_table_initialize
100 * Allocates and initalizes the Address Translation Table and Bar
101 * Tables to get them ready for use. Must be called before any
102 * I/O space is handed out to the device BARs.
104 static void iomm_table_initialize(void)
106 spin_lock(&iomm_table_lock
);
107 iomm_table
= kmalloc(sizeof(*iomm_table
) * IOMM_TABLE_MAX_ENTRIES
,
109 iobar_table
= kmalloc(sizeof(*iobar_table
) * IOMM_TABLE_MAX_ENTRIES
,
111 spin_unlock(&iomm_table_lock
);
112 if ((iomm_table
== NULL
) || (iobar_table
== NULL
))
113 panic("PCI: I/O tables allocation failed.\n");
117 * iomm_table_allocate_entry
119 * Adds pci_dev entry in address translation table
121 * - Allocates the number of entries required in table base on BAR
123 * - Allocates starting at BASE_IO_MEMORY and increases.
124 * - The size is round up to be a multiple of entry size.
125 * - CurrentIndex is incremented to keep track of the last entry.
126 * - Builds the resource entry for allocated BARs.
128 static void iomm_table_allocate_entry(struct pci_dev
*dev
, int bar_num
)
130 struct resource
*bar_res
= &dev
->resource
[bar_num
];
131 long bar_size
= pci_resource_len(dev
, bar_num
);
134 * No space to allocate, quick exit, skip Allocation.
139 * Set Resource values.
141 spin_lock(&iomm_table_lock
);
142 bar_res
->name
= pci_io_text
;
144 IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
;
145 bar_res
->start
+= BASE_IO_MEMORY
;
146 bar_res
->end
= bar_res
->start
+ bar_size
- 1;
148 * Allocate the number of table entries needed for BAR.
150 while (bar_size
> 0 ) {
151 iomm_table
[current_iomm_table_entry
] = dev
->sysdata
;
152 iobar_table
[current_iomm_table_entry
] = bar_num
;
153 bar_size
-= IOMM_TABLE_ENTRY_SIZE
;
154 ++current_iomm_table_entry
;
156 max_io_memory
= BASE_IO_MEMORY
+
157 (IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
);
158 spin_unlock(&iomm_table_lock
);
162 * allocate_device_bars
164 * - Allocates ALL pci_dev BAR's and updates the resources with the
165 * BAR value. BARS with zero length will have the resources
166 * The HvCallPci_getBarParms is used to get the size of the BAR
167 * space. It calls iomm_table_allocate_entry to allocate
169 * - Loops through The Bar resources(0 - 5) including the ROM
172 static void allocate_device_bars(struct pci_dev
*dev
)
174 struct resource
*bar_res
;
177 for (bar_num
= 0; bar_num
<= PCI_ROM_RESOURCE
; ++bar_num
) {
178 bar_res
= &dev
->resource
[bar_num
];
179 iomm_table_allocate_entry(dev
, bar_num
);
184 * Log error information to system console.
185 * Filter out the device not there errors.
186 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
187 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
188 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
190 static void pci_Log_Error(char *Error_Text
, int Bus
, int SubBus
,
191 int AgentId
, int HvRc
)
195 printk(KERN_ERR
"PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
196 Error_Text
, Bus
, SubBus
, AgentId
, HvRc
);
200 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
202 static struct device_node
*build_device_node(HvBusNumber Bus
,
203 HvSubBusNumber SubBus
, int AgentId
, int Function
)
205 struct device_node
*node
;
208 PPCDBG(PPCDBG_BUSWALK
,
209 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
210 Bus
, SubBus
, AgentId
, Function
);
212 node
= kmalloc(sizeof(struct device_node
), GFP_KERNEL
);
215 memset(node
, 0, sizeof(struct device_node
));
216 pdn
= kzalloc(sizeof(*pdn
), GFP_KERNEL
);
222 list_add_tail(&node
->Device_List
, &iSeries_Global_Device_List
);
224 pdn
->DsaAddr
= ((u64
)Bus
<< 48) + ((u64
)SubBus
<< 40) + ((u64
)0x10 << 32);
226 pdn
->DsaAddr
.DsaAddr
= 0;
227 pdn
->DsaAddr
.Dsa
.busNumber
= Bus
;
228 pdn
->DsaAddr
.Dsa
.subBusNumber
= SubBus
;
229 pdn
->DsaAddr
.Dsa
.deviceId
= 0x10;
230 pdn
->devfn
= PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId
), Function
);
235 * unsigned long __init find_and_init_phbs(void)
238 * This function checks for all possible system PCI host bridges that connect
239 * PCI buses. The system hypervisor is queried as to the guest partition
240 * ownership status. A pci_controller is built for any bus which is partially
241 * owned or fully owned by this guest partition.
243 unsigned long __init
find_and_init_phbs(void)
245 struct pci_controller
*phb
;
248 PPCDBG(PPCDBG_BUSWALK
, "find_and_init_phbs Entry\n");
250 /* Check all possible buses. */
251 for (bus
= 0; bus
< 256; bus
++) {
252 int ret
= HvCallXm_testBus(bus
);
254 printk("bus %d appears to exist\n", bus
);
256 phb
= (struct pci_controller
*)kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
259 pci_setup_pci_controller(phb
);
261 phb
->pci_mem_offset
= phb
->local_number
= bus
;
262 phb
->first_busno
= bus
;
263 phb
->last_busno
= bus
;
264 phb
->ops
= &iSeries_pci_ops
;
266 PPCDBG(PPCDBG_BUSWALK
, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
269 /* Find and connect the devices. */
273 * Check for Unexpected Return code, a clue that something
276 else if (ret
!= 0x0301)
277 printk(KERN_ERR
"Unexpected Return on Probe(0x%04X): 0x%04X",
284 * iSeries_pcibios_init
286 * Chance to initialize and structures or variable before PCI Bus walk.
288 void iSeries_pcibios_init(void)
290 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_init Entry.\n");
291 iomm_table_initialize();
292 find_and_init_phbs();
294 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_init Exit.\n");
298 * iSeries_pci_final_fixup(void)
300 void __init
iSeries_pci_final_fixup(void)
302 struct pci_dev
*pdev
= NULL
;
303 struct device_node
*node
;
306 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_fixup Entry.\n");
308 /* Fix up at the device node and pci_dev relationship */
309 mf_display_src(0xC9000100);
311 printk("pcibios_final_fixup\n");
312 for_each_pci_dev(pdev
) {
313 node
= find_Device_Node(pdev
->bus
->number
, pdev
->devfn
);
314 printk("pci dev %p (%x.%x), node %p\n", pdev
,
315 pdev
->bus
->number
, pdev
->devfn
, node
);
319 pdev
->sysdata
= (void *)node
;
320 PCI_DN(node
)->pcidev
= pdev
;
321 PPCDBG(PPCDBG_BUSWALK
,
322 "pdev 0x%p <==> DevNode 0x%p\n",
324 allocate_device_bars(pdev
);
325 iSeries_Device_Information(pdev
, DeviceCount
);
326 iommu_devnode_init_iSeries(node
);
328 printk("PCI: Device Tree not found for 0x%016lX\n",
329 (unsigned long)pdev
);
330 pdev
->irq
= PCI_DN(node
)->Irq
;
332 iSeries_activate_IRQs();
333 mf_display_src(0xC9000200);
336 void pcibios_fixup_bus(struct pci_bus
*PciBus
)
338 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
342 void pcibios_fixup_resources(struct pci_dev
*pdev
)
344 PPCDBG(PPCDBG_BUSWALK
, "fixup_resources pdev %p\n", pdev
);
348 * Loop through each node function to find usable EADs bridges.
350 static void scan_PHB_slots(struct pci_controller
*Phb
)
352 struct HvCallPci_DeviceInfo
*DevInfo
;
353 HvBusNumber bus
= Phb
->local_number
; /* System Bus */
354 const HvSubBusNumber SubBus
= 0; /* EADs is always 0. */
357 const int MaxAgents
= 8;
359 DevInfo
= (struct HvCallPci_DeviceInfo
*)
360 kmalloc(sizeof(struct HvCallPci_DeviceInfo
), GFP_KERNEL
);
365 * Probe for EADs Bridges
367 for (IdSel
= 1; IdSel
< MaxAgents
; ++IdSel
) {
368 HvRc
= HvCallPci_getDeviceInfo(bus
, SubBus
, IdSel
,
369 ISERIES_HV_ADDR(DevInfo
),
370 sizeof(struct HvCallPci_DeviceInfo
));
372 if (DevInfo
->deviceType
== HvCallPci_NodeDevice
)
373 scan_EADS_bridge(bus
, SubBus
, IdSel
);
375 printk("PCI: Invalid System Configuration(0x%02X)"
376 " for bus 0x%02x id 0x%02x.\n",
377 DevInfo
->deviceType
, bus
, IdSel
);
380 pci_Log_Error("getDeviceInfo", bus
, SubBus
, IdSel
, HvRc
);
385 static void scan_EADS_bridge(HvBusNumber bus
, HvSubBusNumber SubBus
,
388 struct HvCallPci_BridgeInfo
*BridgeInfo
;
393 BridgeInfo
= (struct HvCallPci_BridgeInfo
*)
394 kmalloc(sizeof(struct HvCallPci_BridgeInfo
), GFP_KERNEL
);
395 if (BridgeInfo
== NULL
)
398 /* Note: hvSubBus and irq is always be 0 at this level! */
399 for (Function
= 0; Function
< 8; ++Function
) {
400 AgentId
= ISERIES_PCI_AGENTID(IdSel
, Function
);
401 HvRc
= HvCallXm_connectBusUnit(bus
, SubBus
, AgentId
, 0);
403 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
404 bus
, IdSel
, Function
, AgentId
);
405 /* Connect EADs: 0x18.00.12 = 0x00 */
406 PPCDBG(PPCDBG_BUSWALK
,
407 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
408 bus
, SubBus
, AgentId
);
409 HvRc
= HvCallPci_getBusUnitInfo(bus
, SubBus
, AgentId
,
410 ISERIES_HV_ADDR(BridgeInfo
),
411 sizeof(struct HvCallPci_BridgeInfo
));
413 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
414 BridgeInfo
->busUnitInfo
.deviceType
,
415 BridgeInfo
->subBusNumber
,
416 BridgeInfo
->maxAgents
,
417 BridgeInfo
->maxSubBusNumber
,
418 BridgeInfo
->logicalSlotNumber
);
419 PPCDBG(PPCDBG_BUSWALK
,
420 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
421 BridgeInfo
->busUnitInfo
.deviceType
,
422 BridgeInfo
->subBusNumber
,
423 BridgeInfo
->maxAgents
,
424 BridgeInfo
->maxSubBusNumber
,
425 BridgeInfo
->logicalSlotNumber
);
427 if (BridgeInfo
->busUnitInfo
.deviceType
==
428 HvCallPci_BridgeDevice
) {
429 /* Scan_Bridge_Slot...: 0x18.00.12 */
430 scan_bridge_slot(bus
, BridgeInfo
);
432 printk("PCI: Invalid Bridge Configuration(0x%02X)",
433 BridgeInfo
->busUnitInfo
.deviceType
);
435 } else if (HvRc
!= 0x000B)
436 pci_Log_Error("EADs Connect",
437 bus
, SubBus
, AgentId
, HvRc
);
443 * This assumes that the node slot is always on the primary bus!
445 static int scan_bridge_slot(HvBusNumber Bus
,
446 struct HvCallPci_BridgeInfo
*BridgeInfo
)
448 struct device_node
*node
;
449 HvSubBusNumber SubBus
= BridgeInfo
->subBusNumber
;
453 int IdSel
= ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus
);
454 int Function
= ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus
);
455 HvAgentId EADsIdSel
= ISERIES_PCI_AGENTID(IdSel
, Function
);
457 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
458 Irq
= iSeries_allocate_IRQ(Bus
, 0, EADsIdSel
);
459 PPCDBG(PPCDBG_BUSWALK
,
460 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
461 Bus
, 0, EADsIdSel
, Irq
);
464 * Connect all functions of any device found.
466 for (IdSel
= 1; IdSel
<= BridgeInfo
->maxAgents
; ++IdSel
) {
467 for (Function
= 0; Function
< 8; ++Function
) {
468 HvAgentId AgentId
= ISERIES_PCI_AGENTID(IdSel
, Function
);
469 HvRc
= HvCallXm_connectBusUnit(Bus
, SubBus
,
472 pci_Log_Error("Connect Bus Unit",
473 Bus
, SubBus
, AgentId
, HvRc
);
477 HvRc
= HvCallPci_configLoad16(Bus
, SubBus
, AgentId
,
478 PCI_VENDOR_ID
, &VendorId
);
480 pci_Log_Error("Read Vendor",
481 Bus
, SubBus
, AgentId
, HvRc
);
484 printk("read vendor ID: %x\n", VendorId
);
486 /* FoundDevice: 0x18.28.10 = 0x12AE */
487 PPCDBG(PPCDBG_BUSWALK
,
488 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
489 Bus
, SubBus
, AgentId
, VendorId
, Irq
);
490 HvRc
= HvCallPci_configStore8(Bus
, SubBus
, AgentId
,
491 PCI_INTERRUPT_LINE
, Irq
);
493 pci_Log_Error("PciCfgStore Irq Failed!",
494 Bus
, SubBus
, AgentId
, HvRc
);
497 node
= build_device_node(Bus
, SubBus
, EADsIdSel
, Function
);
498 PCI_DN(node
)->Irq
= Irq
;
499 PCI_DN(node
)->LogicalSlot
= BridgeInfo
->logicalSlotNumber
;
501 } /* for (Function = 0; Function < 8; ++Function) */
502 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
507 * I/0 Memory copy MUST use mmio commands on iSeries
508 * To do; For performance, include the hv call directly
510 void iSeries_memset_io(volatile void __iomem
*dest
, char c
, size_t Count
)
513 long NumberOfBytes
= Count
;
515 while (NumberOfBytes
> 0) {
516 iSeries_Write_Byte(ByteValue
, dest
++);
520 EXPORT_SYMBOL(iSeries_memset_io
);
522 void iSeries_memcpy_toio(volatile void __iomem
*dest
, void *source
, size_t count
)
525 long NumberOfBytes
= count
;
527 while (NumberOfBytes
> 0) {
528 iSeries_Write_Byte(*src
++, dest
++);
532 EXPORT_SYMBOL(iSeries_memcpy_toio
);
534 void iSeries_memcpy_fromio(void *dest
, const volatile void __iomem
*src
, size_t count
)
537 long NumberOfBytes
= count
;
539 while (NumberOfBytes
> 0) {
540 *dst
++ = iSeries_Read_Byte(src
++);
544 EXPORT_SYMBOL(iSeries_memcpy_fromio
);
547 * Look down the chain to find the matching Device Device
549 static struct device_node
*find_Device_Node(int bus
, int devfn
)
551 struct list_head
*pos
;
553 list_for_each(pos
, &iSeries_Global_Device_List
) {
554 struct device_node
*node
=
555 list_entry(pos
, struct device_node
, Device_List
);
557 if ((bus
== ISERIES_BUS(node
)) &&
558 (devfn
== PCI_DN(node
)->devfn
))
566 * Returns the device node for the passed pci_dev
567 * Sanity Check Node PciDev to passed pci_dev
568 * If none is found, returns a NULL which the client must handle.
570 static struct device_node
*get_Device_Node(struct pci_dev
*pdev
)
572 struct device_node
*node
;
574 node
= pdev
->sysdata
;
575 if (node
== NULL
|| PCI_DN(node
)->pcidev
!= pdev
)
576 node
= find_Device_Node(pdev
->bus
->number
, pdev
->devfn
);
582 * Config space read and write functions.
583 * For now at least, we look for the device node for the bus and devfn
584 * that we are asked to access. It may be possible to translate the devfn
585 * to a subbus and deviceid more directly.
587 static u64 hv_cfg_read_func
[4] = {
588 HvCallPciConfigLoad8
, HvCallPciConfigLoad16
,
589 HvCallPciConfigLoad32
, HvCallPciConfigLoad32
592 static u64 hv_cfg_write_func
[4] = {
593 HvCallPciConfigStore8
, HvCallPciConfigStore16
,
594 HvCallPciConfigStore32
, HvCallPciConfigStore32
598 * Read PCI config space
600 static int iSeries_pci_read_config(struct pci_bus
*bus
, unsigned int devfn
,
601 int offset
, int size
, u32
*val
)
603 struct device_node
*node
= find_Device_Node(bus
->number
, devfn
);
605 struct HvCallPci_LoadReturn ret
;
608 return PCIBIOS_DEVICE_NOT_FOUND
;
611 return PCIBIOS_BAD_REGISTER_NUMBER
;
614 fn
= hv_cfg_read_func
[(size
- 1) & 3];
615 HvCall3Ret16(fn
, &ret
, PCI_DN(node
)->DsaAddr
.DsaAddr
, offset
, 0);
619 return PCIBIOS_DEVICE_NOT_FOUND
; /* or something */
627 * Write PCI config space
630 static int iSeries_pci_write_config(struct pci_bus
*bus
, unsigned int devfn
,
631 int offset
, int size
, u32 val
)
633 struct device_node
*node
= find_Device_Node(bus
->number
, devfn
);
638 return PCIBIOS_DEVICE_NOT_FOUND
;
640 return PCIBIOS_BAD_REGISTER_NUMBER
;
642 fn
= hv_cfg_write_func
[(size
- 1) & 3];
643 ret
= HvCall4(fn
, PCI_DN(node
)->DsaAddr
.DsaAddr
, offset
, val
, 0);
646 return PCIBIOS_DEVICE_NOT_FOUND
;
651 static struct pci_ops iSeries_pci_ops
= {
652 .read
= iSeries_pci_read_config
,
653 .write
= iSeries_pci_write_config
658 * -> On Failure, print and log information.
659 * Increment Retry Count, if exceeds max, panic partition.
661 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
662 * PCI: Device 23.90 ReadL Retry( 1)
663 * PCI: Device 23.90 ReadL Retry Successful(1)
665 static int CheckReturnCode(char *TextHdr
, struct device_node
*DevNode
,
669 struct pci_dn
*pdn
= PCI_DN(DevNode
);
673 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
674 TextHdr
, pdn
->DsaAddr
.Dsa
.busNumber
, pdn
->devfn
,
677 * Bump the retry and check for retry count exceeded.
678 * If, Exceeded, panic the system.
680 if (((*retry
) > Pci_Retry_Max
) &&
681 (Pci_Error_Flag
> 0)) {
682 mf_display_src(0xB6000103);
684 panic("PCI: Hardware I/O Error, SRC B6000103, "
685 "Automatic Reboot Disabled.\n");
687 return -1; /* Retry Try */
693 * Translate the I/O Address into a device node, bar, and bar offset.
694 * Note: Make sure the passed variable end up on the stack to avoid
695 * the exposure of being device global.
697 static inline struct device_node
*xlate_iomm_address(
698 const volatile void __iomem
*IoAddress
,
699 u64
*dsaptr
, u64
*BarOffsetPtr
)
701 unsigned long OrigIoAddr
;
702 unsigned long BaseIoAddr
;
703 unsigned long TableIndex
;
704 struct device_node
*DevNode
;
706 OrigIoAddr
= (unsigned long __force
)IoAddress
;
707 if ((OrigIoAddr
< BASE_IO_MEMORY
) || (OrigIoAddr
>= max_io_memory
))
709 BaseIoAddr
= OrigIoAddr
- BASE_IO_MEMORY
;
710 TableIndex
= BaseIoAddr
/ IOMM_TABLE_ENTRY_SIZE
;
711 DevNode
= iomm_table
[TableIndex
];
713 if (DevNode
!= NULL
) {
714 int barnum
= iobar_table
[TableIndex
];
715 *dsaptr
= PCI_DN(DevNode
)->DsaAddr
.DsaAddr
| (barnum
<< 24);
716 *BarOffsetPtr
= BaseIoAddr
% IOMM_TABLE_ENTRY_SIZE
;
718 panic("PCI: Invalid PCI IoAddress detected!\n");
723 * Read MM I/O Instructions for the iSeries
724 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
725 * else, data is returned in big Endian format.
727 * iSeries_Read_Byte = Read Byte ( 8 bit)
728 * iSeries_Read_Word = Read Word (16 bit)
729 * iSeries_Read_Long = Read Long (32 bit)
731 u8
iSeries_Read_Byte(const volatile void __iomem
*IoAddress
)
736 struct HvCallPci_LoadReturn ret
;
737 struct device_node
*DevNode
=
738 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
740 if (DevNode
== NULL
) {
741 static unsigned long last_jiffies
;
742 static int num_printed
;
744 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
745 last_jiffies
= jiffies
;
748 if (num_printed
++ < 10)
749 printk(KERN_ERR
"iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress
);
754 HvCall3Ret16(HvCallPciBarLoad8
, &ret
, dsa
, BarOffset
, 0);
755 } while (CheckReturnCode("RDB", DevNode
, &retry
, ret
.rc
) != 0);
757 return (u8
)ret
.value
;
759 EXPORT_SYMBOL(iSeries_Read_Byte
);
761 u16
iSeries_Read_Word(const volatile void __iomem
*IoAddress
)
766 struct HvCallPci_LoadReturn ret
;
767 struct device_node
*DevNode
=
768 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
770 if (DevNode
== NULL
) {
771 static unsigned long last_jiffies
;
772 static int num_printed
;
774 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
775 last_jiffies
= jiffies
;
778 if (num_printed
++ < 10)
779 printk(KERN_ERR
"iSeries_Read_Word: invalid access at IO address %p\n", IoAddress
);
784 HvCall3Ret16(HvCallPciBarLoad16
, &ret
, dsa
,
786 } while (CheckReturnCode("RDW", DevNode
, &retry
, ret
.rc
) != 0);
788 return swab16((u16
)ret
.value
);
790 EXPORT_SYMBOL(iSeries_Read_Word
);
792 u32
iSeries_Read_Long(const volatile void __iomem
*IoAddress
)
797 struct HvCallPci_LoadReturn ret
;
798 struct device_node
*DevNode
=
799 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
801 if (DevNode
== NULL
) {
802 static unsigned long last_jiffies
;
803 static int num_printed
;
805 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
806 last_jiffies
= jiffies
;
809 if (num_printed
++ < 10)
810 printk(KERN_ERR
"iSeries_Read_Long: invalid access at IO address %p\n", IoAddress
);
815 HvCall3Ret16(HvCallPciBarLoad32
, &ret
, dsa
,
817 } while (CheckReturnCode("RDL", DevNode
, &retry
, ret
.rc
) != 0);
819 return swab32((u32
)ret
.value
);
821 EXPORT_SYMBOL(iSeries_Read_Long
);
824 * Write MM I/O Instructions for the iSeries
826 * iSeries_Write_Byte = Write Byte (8 bit)
827 * iSeries_Write_Word = Write Word(16 bit)
828 * iSeries_Write_Long = Write Long(32 bit)
830 void iSeries_Write_Byte(u8 data
, volatile void __iomem
*IoAddress
)
836 struct device_node
*DevNode
=
837 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
839 if (DevNode
== NULL
) {
840 static unsigned long last_jiffies
;
841 static int num_printed
;
843 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
844 last_jiffies
= jiffies
;
847 if (num_printed
++ < 10)
848 printk(KERN_ERR
"iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress
);
852 ++Pci_Io_Write_Count
;
853 rc
= HvCall4(HvCallPciBarStore8
, dsa
, BarOffset
, data
, 0);
854 } while (CheckReturnCode("WWB", DevNode
, &retry
, rc
) != 0);
856 EXPORT_SYMBOL(iSeries_Write_Byte
);
858 void iSeries_Write_Word(u16 data
, volatile void __iomem
*IoAddress
)
864 struct device_node
*DevNode
=
865 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
867 if (DevNode
== NULL
) {
868 static unsigned long last_jiffies
;
869 static int num_printed
;
871 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
872 last_jiffies
= jiffies
;
875 if (num_printed
++ < 10)
876 printk(KERN_ERR
"iSeries_Write_Word: invalid access at IO address %p\n", IoAddress
);
880 ++Pci_Io_Write_Count
;
881 rc
= HvCall4(HvCallPciBarStore16
, dsa
, BarOffset
, swab16(data
), 0);
882 } while (CheckReturnCode("WWW", DevNode
, &retry
, rc
) != 0);
884 EXPORT_SYMBOL(iSeries_Write_Word
);
886 void iSeries_Write_Long(u32 data
, volatile void __iomem
*IoAddress
)
892 struct device_node
*DevNode
=
893 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
895 if (DevNode
== NULL
) {
896 static unsigned long last_jiffies
;
897 static int num_printed
;
899 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
900 last_jiffies
= jiffies
;
903 if (num_printed
++ < 10)
904 printk(KERN_ERR
"iSeries_Write_Long: invalid access at IO address %p\n", IoAddress
);
908 ++Pci_Io_Write_Count
;
909 rc
= HvCall4(HvCallPciBarStore32
, dsa
, BarOffset
, swab32(data
), 0);
910 } while (CheckReturnCode("WWL", DevNode
, &retry
, rc
) != 0);
912 EXPORT_SYMBOL(iSeries_Write_Long
);