2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
4 * Author: Li Yang <LeoLi@freescale.com>
5 * Yin Olivia <Hong-hua.Yin@freescale.com>
8 * MPC8360E MDS board specific routines.
11 * Jun 21, 2006 Initial version
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/compiler.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/reboot.h>
25 #include <linux/pci.h>
26 #include <linux/kdev_t.h>
27 #include <linux/major.h>
28 #include <linux/console.h>
29 #include <linux/delay.h>
30 #include <linux/seq_file.h>
31 #include <linux/root_dev.h>
32 #include <linux/initrd.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_device.h>
36 #include <asm/system.h>
37 #include <linux/atomic.h>
40 #include <asm/machdep.h>
45 #include <sysdev/fsl_soc.h>
46 #include <sysdev/fsl_pci.h>
47 #include <sysdev/simple_gpio.h>
49 #include <asm/qe_ic.h>
55 #define DBG(fmt...) udbg_printf(fmt)
60 /* ************************************************************************
62 * Setup the architecture
65 static void __init
mpc836x_mds_setup_arch(void)
67 struct device_node
*np
;
68 u8 __iomem
*bcsr_regs
= NULL
;
71 ppc_md
.progress("mpc836x_mds_setup_arch()", 0);
74 np
= of_find_node_by_name(NULL
, "bcsr");
78 of_address_to_resource(np
, 0, &res
);
79 bcsr_regs
= ioremap(res
.start
, resource_size(&res
));
84 for_each_compatible_node(np
, "pci", "fsl,mpc8349-pci")
85 mpc83xx_add_bridge(np
);
88 #ifdef CONFIG_QUICC_ENGINE
91 if ((np
= of_find_node_by_name(NULL
, "par_io")) != NULL
) {
95 for (np
= NULL
; (np
= of_find_node_by_name(np
, "ucc")) != NULL
;)
98 /* Must fixup Par IO before QE GPIO chips are registered. */
99 par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
100 par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
101 par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
102 par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
103 par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
104 par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
105 par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
106 #endif /* CONFIG_QE_USB */
109 if ((np
= of_find_compatible_node(NULL
, "network", "ucc_geth"))
113 /* Reset the Ethernet PHY */
114 #define BCSR9_GETHRST 0x20
115 clrbits8(&bcsr_regs
[9], BCSR9_GETHRST
);
117 setbits8(&bcsr_regs
[9], BCSR9_GETHRST
);
119 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
120 svid
= mfspr(SPRN_SVR
);
121 if (svid
== 0x80480021) {
124 immap
= ioremap(get_immrbase() + 0x14a8, 8);
127 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
128 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
130 setbits32(immap
, 0x0c003000);
133 * IMMR + 0x14AC[20:27] = 10101010
134 * (data delay for both UCC's)
136 clrsetbits_be32(immap
+ 4, 0xff0, 0xaa0);
144 #endif /* CONFIG_QUICC_ENGINE */
147 machine_device_initcall(mpc836x_mds
, mpc83xx_declare_of_platform_devices
);
150 static int __init
mpc836x_usb_cfg(void)
153 struct device_node
*np
;
157 np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc8360mds-bcsr");
161 bcsr
= of_iomap(np
, 0);
166 np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc8323-qe-usb");
172 #define BCSR8_TSEC1M_MASK (0x3 << 6)
173 #define BCSR8_TSEC1M_RGMII (0x0 << 6)
174 #define BCSR8_TSEC2M_MASK (0x3 << 4)
175 #define BCSR8_TSEC2M_RGMII (0x0 << 4)
177 * Default is GMII (2), but we should set it to RGMII (0) if we use
178 * USB (Eth PHY is in RGMII mode anyway).
180 clrsetbits_8(&bcsr
[8], BCSR8_TSEC1M_MASK
| BCSR8_TSEC2M_MASK
,
181 BCSR8_TSEC1M_RGMII
| BCSR8_TSEC2M_RGMII
);
183 #define BCSR13_USBMASK 0x0f
184 #define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */
185 #define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */
186 #define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */
187 #define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */
189 clrsetbits_8(&bcsr
[13], BCSR13_USBMASK
, BCSR13_USBSPEED
);
191 mode
= of_get_property(np
, "mode", NULL
);
192 if (mode
&& !strcmp(mode
, "peripheral")) {
193 setbits8(&bcsr
[13], BCSR13_nUSBVCC
);
194 qe_usb_clock_set(QE_CLK21
, 48000000);
196 setbits8(&bcsr
[13], BCSR13_USBMODE
);
198 * The BCSR GPIOs are used to control power and
199 * speed of the USB transceiver. This is needed for
202 simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
210 machine_arch_initcall(mpc836x_mds
, mpc836x_usb_cfg
);
211 #endif /* CONFIG_QE_USB */
214 * Called very early, MMU is off, device-tree isn't unflattened
216 static int __init
mpc836x_mds_probe(void)
218 unsigned long root
= of_get_flat_dt_root();
220 return of_flat_dt_is_compatible(root
, "MPC836xMDS");
223 define_machine(mpc836x_mds
) {
224 .name
= "MPC836x MDS",
225 .probe
= mpc836x_mds_probe
,
226 .setup_arch
= mpc836x_mds_setup_arch
,
227 .init_IRQ
= mpc83xx_ipic_and_qe_init_IRQ
,
228 .get_irq
= ipic_get_irq
,
229 .restart
= mpc83xx_restart
,
230 .time_init
= mpc83xx_time_init
,
231 .calibrate_decr
= generic_calibrate_decr
,
232 .progress
= udbg_progress
,