Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / setup_32.c
1 /*
2 * Common prep/pmac/chrp boot and setup code.
3 */
4
5 #include <linux/module.h>
6 #include <linux/string.h>
7 #include <linux/sched.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/reboot.h>
11 #include <linux/delay.h>
12 #include <linux/initrd.h>
13 #include <linux/ide.h>
14 #include <linux/tty.h>
15 #include <linux/bootmem.h>
16 #include <linux/seq_file.h>
17 #include <linux/root_dev.h>
18 #include <linux/cpu.h>
19 #include <linux/console.h>
20
21 #include <asm/residual.h>
22 #include <asm/io.h>
23 #include <asm/prom.h>
24 #include <asm/processor.h>
25 #include <asm/pgtable.h>
26 #include <asm/setup.h>
27 #include <asm/amigappc.h>
28 #include <asm/smp.h>
29 #include <asm/elf.h>
30 #include <asm/cputable.h>
31 #include <asm/bootx.h>
32 #include <asm/btext.h>
33 #include <asm/machdep.h>
34 #include <asm/uaccess.h>
35 #include <asm/system.h>
36 #include <asm/pmac_feature.h>
37 #include <asm/sections.h>
38 #include <asm/nvram.h>
39 #include <asm/xmon.h>
40 #include <asm/time.h>
41 #include <asm/serial.h>
42 #include <asm/udbg.h>
43
44 #include "setup.h"
45
46 #define DBG(fmt...)
47
48 #if defined CONFIG_KGDB
49 #include <asm/kgdb.h>
50 #endif
51
52 extern void bootx_init(unsigned long r4, unsigned long phys);
53
54 boot_infos_t *boot_infos;
55 struct ide_machdep_calls ppc_ide_md;
56
57 int boot_cpuid;
58 EXPORT_SYMBOL_GPL(boot_cpuid);
59 int boot_cpuid_phys;
60
61 unsigned long ISA_DMA_THRESHOLD;
62 unsigned int DMA_MODE_READ;
63 unsigned int DMA_MODE_WRITE;
64
65 int have_of = 1;
66
67 #ifdef CONFIG_PPC_MULTIPLATFORM
68 dev_t boot_dev;
69 #endif /* CONFIG_PPC_MULTIPLATFORM */
70
71 #ifdef CONFIG_MAGIC_SYSRQ
72 unsigned long SYSRQ_KEY = 0x54;
73 #endif /* CONFIG_MAGIC_SYSRQ */
74
75 #ifdef CONFIG_VGA_CONSOLE
76 unsigned long vgacon_remap_base;
77 #endif
78
79 /*
80 * These are used in binfmt_elf.c to put aux entries on the stack
81 * for each elf executable being started.
82 */
83 int dcache_bsize;
84 int icache_bsize;
85 int ucache_bsize;
86
87 /*
88 * We're called here very early in the boot. We determine the machine
89 * type and call the appropriate low-level setup functions.
90 * -- Cort <cort@fsmlabs.com>
91 *
92 * Note that the kernel may be running at an address which is different
93 * from the address that it was linked at, so we must use RELOC/PTRRELOC
94 * to access static data (including strings). -- paulus
95 */
96 unsigned long __init early_init(unsigned long dt_ptr)
97 {
98 unsigned long offset = reloc_offset();
99
100 /* First zero the BSS -- use memset_io, some platforms don't have
101 * caches on yet */
102 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, _end - __bss_start);
103
104 /*
105 * Identify the CPU type and fix up code sections
106 * that depend on which cpu we have.
107 */
108 identify_cpu(offset, 0);
109 do_cpu_ftr_fixups(offset);
110
111 return KERNELBASE + offset;
112 }
113
114
115 /*
116 * Find out what kind of machine we're on and save any data we need
117 * from the early boot process (devtree is copied on pmac by prom_init()).
118 * This is called very early on the boot process, after a minimal
119 * MMU environment has been set up but before MMU_init is called.
120 */
121 void __init machine_init(unsigned long dt_ptr, unsigned long phys)
122 {
123 /* If btext is enabled, we might have a BAT setup for early display,
124 * thus we do enable some very basic udbg output
125 */
126 #ifdef CONFIG_BOOTX_TEXT
127 udbg_putc = btext_drawchar;
128 #endif
129
130 /* Do some early initialization based on the flat device tree */
131 early_init_devtree(__va(dt_ptr));
132
133 probe_machine();
134
135 #ifdef CONFIG_6xx
136 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
137 cpu_has_feature(CPU_FTR_CAN_NAP))
138 ppc_md.power_save = ppc6xx_idle;
139 #endif
140
141 if (ppc_md.progress)
142 ppc_md.progress("id mach(): done", 0x200);
143 }
144
145 #ifdef CONFIG_BOOKE_WDT
146 /* Checks wdt=x and wdt_period=xx command-line option */
147 int __init early_parse_wdt(char *p)
148 {
149 if (p && strncmp(p, "0", 1) != 0)
150 booke_wdt_enabled = 1;
151
152 return 0;
153 }
154 early_param("wdt", early_parse_wdt);
155
156 int __init early_parse_wdt_period (char *p)
157 {
158 if (p)
159 booke_wdt_period = simple_strtoul(p, NULL, 0);
160
161 return 0;
162 }
163 early_param("wdt_period", early_parse_wdt_period);
164 #endif /* CONFIG_BOOKE_WDT */
165
166 /* Checks "l2cr=xxxx" command-line option */
167 int __init ppc_setup_l2cr(char *str)
168 {
169 if (cpu_has_feature(CPU_FTR_L2CR)) {
170 unsigned long val = simple_strtoul(str, NULL, 0);
171 printk(KERN_INFO "l2cr set to %lx\n", val);
172 _set_L2CR(0); /* force invalidate by disable cache */
173 _set_L2CR(val); /* and enable it */
174 }
175 return 1;
176 }
177 __setup("l2cr=", ppc_setup_l2cr);
178
179 #ifdef CONFIG_GENERIC_NVRAM
180
181 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
182 unsigned char nvram_read_byte(int addr)
183 {
184 if (ppc_md.nvram_read_val)
185 return ppc_md.nvram_read_val(addr);
186 return 0xff;
187 }
188 EXPORT_SYMBOL(nvram_read_byte);
189
190 void nvram_write_byte(unsigned char val, int addr)
191 {
192 if (ppc_md.nvram_write_val)
193 ppc_md.nvram_write_val(addr, val);
194 }
195 EXPORT_SYMBOL(nvram_write_byte);
196
197 void nvram_sync(void)
198 {
199 if (ppc_md.nvram_sync)
200 ppc_md.nvram_sync();
201 }
202 EXPORT_SYMBOL(nvram_sync);
203
204 #endif /* CONFIG_NVRAM */
205
206 static struct cpu cpu_devices[NR_CPUS];
207
208 int __init ppc_init(void)
209 {
210 int i;
211
212 /* clear the progress line */
213 if ( ppc_md.progress ) ppc_md.progress(" ", 0xffff);
214
215 /* register CPU devices */
216 for_each_possible_cpu(i)
217 register_cpu(&cpu_devices[i], i);
218
219 /* call platform init */
220 if (ppc_md.init != NULL) {
221 ppc_md.init();
222 }
223 return 0;
224 }
225
226 arch_initcall(ppc_init);
227
228 /* Warning, IO base is not yet inited */
229 void __init setup_arch(char **cmdline_p)
230 {
231 *cmdline_p = cmd_line;
232
233 /* so udelay does something sensible, assume <= 1000 bogomips */
234 loops_per_jiffy = 500000000 / HZ;
235
236 unflatten_device_tree();
237 check_for_initrd();
238
239 if (ppc_md.init_early)
240 ppc_md.init_early();
241
242 find_legacy_serial_ports();
243 finish_device_tree();
244
245 smp_setup_cpu_maps();
246
247 #ifdef CONFIG_XMON_DEFAULT
248 xmon_init(1);
249 #endif
250 /* Register early console */
251 register_early_udbg_console();
252
253 #if defined(CONFIG_KGDB)
254 if (ppc_md.kgdb_map_scc)
255 ppc_md.kgdb_map_scc();
256 set_debug_traps();
257 if (strstr(cmd_line, "gdb")) {
258 if (ppc_md.progress)
259 ppc_md.progress("setup_arch: kgdb breakpoint", 0x4000);
260 printk("kgdb breakpoint activated\n");
261 breakpoint();
262 }
263 #endif
264
265 /*
266 * Set cache line size based on type of cpu as a default.
267 * Systems with OF can look in the properties on the cpu node(s)
268 * for a possibly more accurate value.
269 */
270 if (cpu_has_feature(CPU_FTR_SPLIT_ID_CACHE)) {
271 dcache_bsize = cur_cpu_spec->dcache_bsize;
272 icache_bsize = cur_cpu_spec->icache_bsize;
273 ucache_bsize = 0;
274 } else
275 ucache_bsize = dcache_bsize = icache_bsize
276 = cur_cpu_spec->dcache_bsize;
277
278 /* reboot on panic */
279 panic_timeout = 180;
280
281 if (ppc_md.panic)
282 setup_panic();
283
284 init_mm.start_code = PAGE_OFFSET;
285 init_mm.end_code = (unsigned long) _etext;
286 init_mm.end_data = (unsigned long) _edata;
287 init_mm.brk = klimit;
288
289 if (do_early_xmon)
290 debugger(NULL);
291
292 /* set up the bootmem stuff with available memory */
293 do_init_bootmem();
294 if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
295
296 #ifdef CONFIG_DUMMY_CONSOLE
297 conswitchp = &dummy_con;
298 #endif
299
300 ppc_md.setup_arch();
301 if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
302
303 paging_init();
304 }