2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14 #include <linux/irq.h>
15 #include <linux/list.h>
17 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/pci-bridge.h>
22 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
24 #include <asm/machdep.h>
29 #define DBG(x...) printk(x)
34 unsigned long isa_io_base
= 0;
35 unsigned long isa_mem_base
= 0;
36 unsigned long pci_dram_offset
= 0;
37 int pcibios_assign_bus_offset
= 1;
39 void pcibios_make_OF_bus_map(void);
41 static int pci_relocate_bridge_resource(struct pci_bus
*bus
, int i
);
42 static int probe_resource(struct pci_bus
*parent
, struct resource
*pr
,
43 struct resource
*res
, struct resource
**conflict
);
44 static void update_bridge_base(struct pci_bus
*bus
, int i
);
45 static void pcibios_fixup_resources(struct pci_dev
* dev
);
46 static void fixup_broken_pcnet32(struct pci_dev
* dev
);
47 static int reparent_resources(struct resource
*parent
, struct resource
*res
);
48 static void fixup_cpc710_pci64(struct pci_dev
* dev
);
50 static u8
* pci_to_OF_bus_map
;
53 /* By default, we don't re-assign bus numbers. We do this only on
56 int pci_assign_all_buses
;
58 struct pci_controller
* hose_head
;
59 struct pci_controller
** hose_tail
= &hose_head
;
61 static int pci_bus_count
;
64 fixup_broken_pcnet32(struct pci_dev
* dev
)
66 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
67 dev
->vendor
= PCI_VENDOR_ID_AMD
;
68 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
71 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
74 fixup_cpc710_pci64(struct pci_dev
* dev
)
76 /* Hide the PCI64 BARs from the kernel as their content doesn't
77 * fit well in the resource management
79 dev
->resource
[0].start
= dev
->resource
[0].end
= 0;
80 dev
->resource
[0].flags
= 0;
81 dev
->resource
[1].start
= dev
->resource
[1].end
= 0;
82 dev
->resource
[1].flags
= 0;
84 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CPC710_PCI64
, fixup_cpc710_pci64
);
87 pcibios_fixup_resources(struct pci_dev
*dev
)
89 struct pci_controller
* hose
= (struct pci_controller
*)dev
->sysdata
;
94 printk(KERN_ERR
"No hose for PCI dev %s!\n", pci_name(dev
));
97 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
98 struct resource
*res
= dev
->resource
+ i
;
101 if (res
->end
== 0xffffffff) {
102 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
103 pci_name(dev
), i
, res
->start
, res
->end
);
104 res
->end
-= res
->start
;
106 res
->flags
|= IORESOURCE_UNSET
;
110 if (res
->flags
& IORESOURCE_MEM
) {
111 offset
= hose
->pci_mem_offset
;
112 } else if (res
->flags
& IORESOURCE_IO
) {
113 offset
= (unsigned long) hose
->io_base_virt
117 res
->start
+= offset
;
120 printk("Fixup res %d (%lx) of dev %s: %llx -> %llx\n",
121 i
, res
->flags
, pci_name(dev
),
122 res
->start
- offset
, res
->start
);
127 /* Call machine specific resource fixup */
128 if (ppc_md
.pcibios_fixup_resources
)
129 ppc_md
.pcibios_fixup_resources(dev
);
131 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
133 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
134 struct resource
*res
)
136 unsigned long offset
= 0;
137 struct pci_controller
*hose
= dev
->sysdata
;
139 if (hose
&& res
->flags
& IORESOURCE_IO
)
140 offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
141 else if (hose
&& res
->flags
& IORESOURCE_MEM
)
142 offset
= hose
->pci_mem_offset
;
143 region
->start
= res
->start
- offset
;
144 region
->end
= res
->end
- offset
;
146 EXPORT_SYMBOL(pcibios_resource_to_bus
);
148 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
149 struct pci_bus_region
*region
)
151 unsigned long offset
= 0;
152 struct pci_controller
*hose
= dev
->sysdata
;
154 if (hose
&& res
->flags
& IORESOURCE_IO
)
155 offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
156 else if (hose
&& res
->flags
& IORESOURCE_MEM
)
157 offset
= hose
->pci_mem_offset
;
158 res
->start
= region
->start
+ offset
;
159 res
->end
= region
->end
+ offset
;
161 EXPORT_SYMBOL(pcibios_bus_to_resource
);
164 * We need to avoid collisions with `mirrored' VGA ports
165 * and other strange ISA hardware, so we always want the
166 * addresses to be allocated in the 0x000-0x0ff region
169 * Why? Because some silly external IO cards only decode
170 * the low 10 bits of the IO address. The 0x00-0xff region
171 * is reserved for motherboard devices that decode all 16
172 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
173 * but we want to try to avoid allocating at 0x2900-0x2bff
174 * which might have be mirrored at 0x0100-0x03ff..
176 void pcibios_align_resource(void *data
, struct resource
*res
,
177 resource_size_t size
, resource_size_t align
)
179 struct pci_dev
*dev
= data
;
181 if (res
->flags
& IORESOURCE_IO
) {
182 resource_size_t start
= res
->start
;
185 printk(KERN_ERR
"PCI: I/O Region %s/%d too large"
186 " (%lld bytes)\n", pci_name(dev
),
187 dev
->resource
- res
, (unsigned long long)size
);
191 start
= (start
+ 0x3ff) & ~0x3ff;
196 EXPORT_SYMBOL(pcibios_align_resource
);
199 * Handle resources of PCI devices. If the world were perfect, we could
200 * just allocate all the resource regions and do nothing more. It isn't.
201 * On the other hand, we cannot just re-allocate all devices, as it would
202 * require us to know lots of host bridge internals. So we attempt to
203 * keep as much of the original configuration as possible, but tweak it
204 * when it's found to be wrong.
206 * Known BIOS problems we have to work around:
207 * - I/O or memory regions not configured
208 * - regions configured, but not enabled in the command register
209 * - bogus I/O addresses above 64K used
210 * - expansion ROMs left enabled (this may sound harmless, but given
211 * the fact the PCI specs explicitly allow address decoders to be
212 * shared between expansion ROMs and other resource regions, it's
213 * at least dangerous)
216 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
217 * This gives us fixed barriers on where we can allocate.
218 * (2) Allocate resources for all enabled devices. If there is
219 * a collision, just mark the resource as unallocated. Also
220 * disable expansion ROMs during this step.
221 * (3) Try to allocate resources for disabled devices. If the
222 * resources were assigned correctly, everything goes well,
223 * if they weren't, they won't disturb allocation of other
225 * (4) Assign new addresses to resources which were either
226 * not configured at all or misconfigured. If explicitly
227 * requested by the user, configure expansion ROM address
232 pcibios_allocate_bus_resources(struct list_head
*bus_list
)
236 struct resource
*res
, *pr
;
238 /* Depth-First Search on bus tree */
239 list_for_each_entry(bus
, bus_list
, node
) {
240 for (i
= 0; i
< 4; ++i
) {
241 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
242 || res
->start
> res
->end
)
244 if (bus
->parent
== NULL
)
245 pr
= (res
->flags
& IORESOURCE_IO
)?
246 &ioport_resource
: &iomem_resource
;
248 pr
= pci_find_parent_resource(bus
->self
, res
);
250 /* this happens when the generic PCI
251 * code (wrongly) decides that this
252 * bridge is transparent -- paulus
258 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
259 res
->start
, res
->end
, res
->flags
, pr
);
261 if (request_resource(pr
, res
) == 0)
264 * Must be a conflict with an existing entry.
265 * Move that entry (or entries) under the
266 * bridge resource and try again.
268 if (reparent_resources(pr
, res
) == 0)
271 printk(KERN_ERR
"PCI: Cannot allocate resource region "
272 "%d of PCI bridge %d\n", i
, bus
->number
);
273 if (pci_relocate_bridge_resource(bus
, i
))
274 bus
->resource
[i
] = NULL
;
276 pcibios_allocate_bus_resources(&bus
->children
);
281 * Reparent resource children of pr that conflict with res
282 * under res, and make res replace those children.
285 reparent_resources(struct resource
*parent
, struct resource
*res
)
287 struct resource
*p
, **pp
;
288 struct resource
**firstpp
= NULL
;
290 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
291 if (p
->end
< res
->start
)
293 if (res
->end
< p
->start
)
295 if (p
->start
< res
->start
|| p
->end
> res
->end
)
296 return -1; /* not completely contained */
301 return -1; /* didn't find any conflicting entries? */
302 res
->parent
= parent
;
303 res
->child
= *firstpp
;
307 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
309 DBG(KERN_INFO
"PCI: reparented %s [%llx..%llx] under %s\n",
310 p
->name
, p
->start
, p
->end
, res
->name
);
316 * A bridge has been allocated a range which is outside the range
317 * of its parent bridge, so it needs to be moved.
320 pci_relocate_bridge_resource(struct pci_bus
*bus
, int i
)
322 struct resource
*res
, *pr
, *conflict
;
323 unsigned long try, size
;
325 struct pci_bus
*parent
= bus
->parent
;
327 if (parent
== NULL
) {
328 /* shouldn't ever happen */
329 printk(KERN_ERR
"PCI: can't move host bridge resource\n");
332 res
= bus
->resource
[i
];
336 for (j
= 0; j
< 4; j
++) {
337 struct resource
*r
= parent
->resource
[j
];
340 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
342 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
)) {
346 if (res
->flags
& IORESOURCE_PREFETCH
)
351 size
= res
->end
- res
->start
;
352 if (pr
->start
> pr
->end
|| size
> pr
->end
- pr
->start
)
356 res
->start
= try - size
;
358 if (probe_resource(bus
->parent
, pr
, res
, &conflict
) == 0)
360 if (conflict
->start
<= pr
->start
+ size
)
362 try = conflict
->start
- 1;
364 if (request_resource(pr
, res
)) {
365 DBG(KERN_ERR
"PCI: huh? couldn't move to %llx..%llx\n",
366 res
->start
, res
->end
);
367 return -1; /* "can't happen" */
369 update_bridge_base(bus
, i
);
370 printk(KERN_INFO
"PCI: bridge %d resource %d moved to %llx..%llx\n",
371 bus
->number
, i
, (unsigned long long)res
->start
,
372 (unsigned long long)res
->end
);
377 probe_resource(struct pci_bus
*parent
, struct resource
*pr
,
378 struct resource
*res
, struct resource
**conflict
)
385 for (r
= pr
->child
; r
!= NULL
; r
= r
->sibling
) {
386 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
391 list_for_each_entry(bus
, &parent
->children
, node
) {
392 for (i
= 0; i
< 4; ++i
) {
393 if ((r
= bus
->resource
[i
]) == NULL
)
395 if (!r
->flags
|| r
->start
> r
->end
|| r
== res
)
397 if (pci_find_parent_resource(bus
->self
, r
) != pr
)
399 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
405 list_for_each_entry(dev
, &parent
->devices
, bus_list
) {
406 for (i
= 0; i
< 6; ++i
) {
407 r
= &dev
->resource
[i
];
408 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
410 if (pci_find_parent_resource(dev
, r
) != pr
)
412 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
422 update_bridge_base(struct pci_bus
*bus
, int i
)
424 struct resource
*res
= bus
->resource
[i
];
425 u8 io_base_lo
, io_limit_lo
;
426 u16 mem_base
, mem_limit
;
428 unsigned long start
, end
, off
;
429 struct pci_dev
*dev
= bus
->self
;
430 struct pci_controller
*hose
= dev
->sysdata
;
433 printk("update_bridge_base: no hose?\n");
436 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
437 pci_write_config_word(dev
, PCI_COMMAND
,
438 cmd
& ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
));
439 if (res
->flags
& IORESOURCE_IO
) {
440 off
= (unsigned long) hose
->io_base_virt
- isa_io_base
;
441 start
= res
->start
- off
;
442 end
= res
->end
- off
;
443 io_base_lo
= (start
>> 8) & PCI_IO_RANGE_MASK
;
444 io_limit_lo
= (end
>> 8) & PCI_IO_RANGE_MASK
;
446 io_base_lo
|= PCI_IO_RANGE_TYPE_32
;
448 io_base_lo
|= PCI_IO_RANGE_TYPE_16
;
449 pci_write_config_word(dev
, PCI_IO_BASE_UPPER16
,
451 pci_write_config_word(dev
, PCI_IO_LIMIT_UPPER16
,
453 pci_write_config_byte(dev
, PCI_IO_BASE
, io_base_lo
);
454 pci_write_config_byte(dev
, PCI_IO_LIMIT
, io_limit_lo
);
456 } else if ((res
->flags
& (IORESOURCE_MEM
| IORESOURCE_PREFETCH
))
458 off
= hose
->pci_mem_offset
;
459 mem_base
= ((res
->start
- off
) >> 16) & PCI_MEMORY_RANGE_MASK
;
460 mem_limit
= ((res
->end
- off
) >> 16) & PCI_MEMORY_RANGE_MASK
;
461 pci_write_config_word(dev
, PCI_MEMORY_BASE
, mem_base
);
462 pci_write_config_word(dev
, PCI_MEMORY_LIMIT
, mem_limit
);
464 } else if ((res
->flags
& (IORESOURCE_MEM
| IORESOURCE_PREFETCH
))
465 == (IORESOURCE_MEM
| IORESOURCE_PREFETCH
)) {
466 off
= hose
->pci_mem_offset
;
467 mem_base
= ((res
->start
- off
) >> 16) & PCI_PREF_RANGE_MASK
;
468 mem_limit
= ((res
->end
- off
) >> 16) & PCI_PREF_RANGE_MASK
;
469 pci_write_config_word(dev
, PCI_PREF_MEMORY_BASE
, mem_base
);
470 pci_write_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, mem_limit
);
473 DBG(KERN_ERR
"PCI: ugh, bridge %s res %d has flags=%lx\n",
474 pci_name(dev
), i
, res
->flags
);
476 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
479 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
481 struct resource
*pr
, *r
= &dev
->resource
[idx
];
483 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
484 pci_name(dev
), idx
, r
->start
, r
->end
, r
->flags
);
485 pr
= pci_find_parent_resource(dev
, r
);
486 if (!pr
|| request_resource(pr
, r
) < 0) {
487 printk(KERN_ERR
"PCI: Cannot allocate resource region %d"
488 " of device %s\n", idx
, pci_name(dev
));
490 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
491 pr
, pr
->start
, pr
->end
, pr
->flags
);
492 /* We'll assign a new address later */
493 r
->flags
|= IORESOURCE_UNSET
;
500 pcibios_allocate_resources(int pass
)
502 struct pci_dev
*dev
= NULL
;
507 for_each_pci_dev(dev
) {
508 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
509 for (idx
= 0; idx
< 6; idx
++) {
510 r
= &dev
->resource
[idx
];
511 if (r
->parent
) /* Already allocated */
513 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
514 continue; /* Not assigned at all */
515 if (r
->flags
& IORESOURCE_IO
)
516 disabled
= !(command
& PCI_COMMAND_IO
);
518 disabled
= !(command
& PCI_COMMAND_MEMORY
);
519 if (pass
== disabled
)
520 alloc_resource(dev
, idx
);
524 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
525 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
526 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
528 DBG("PCI: Switching off ROM of %s\n", pci_name(dev
));
529 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
530 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
531 pci_write_config_dword(dev
, dev
->rom_base_reg
,
532 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
538 pcibios_assign_resources(void)
540 struct pci_dev
*dev
= NULL
;
544 for_each_pci_dev(dev
) {
545 int class = dev
->class >> 8;
547 /* Don't touch classless devices and host bridges */
548 if (!class || class == PCI_CLASS_BRIDGE_HOST
)
551 for (idx
= 0; idx
< 6; idx
++) {
552 r
= &dev
->resource
[idx
];
555 * We shall assign a new address to this resource,
556 * either because the BIOS (sic) forgot to do so
557 * or because we have decided the old address was
558 * unusable for some reason.
560 if ((r
->flags
& IORESOURCE_UNSET
) && r
->end
&&
561 (!ppc_md
.pcibios_enable_device_hook
||
562 !ppc_md
.pcibios_enable_device_hook(dev
, 1))) {
563 r
->flags
&= ~IORESOURCE_UNSET
;
564 pci_assign_resource(dev
, idx
);
568 #if 0 /* don't assign ROMs */
569 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
573 pci_assign_resource(dev
, PCI_ROM_RESOURCE
);
580 pcibios_enable_resources(struct pci_dev
*dev
, int mask
)
586 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
588 for (idx
=0; idx
<6; idx
++) {
589 /* Only set up the requested stuff */
590 if (!(mask
& (1<<idx
)))
593 r
= &dev
->resource
[idx
];
594 if (r
->flags
& IORESOURCE_UNSET
) {
595 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", pci_name(dev
));
598 if (r
->flags
& IORESOURCE_IO
)
599 cmd
|= PCI_COMMAND_IO
;
600 if (r
->flags
& IORESOURCE_MEM
)
601 cmd
|= PCI_COMMAND_MEMORY
;
603 if (dev
->resource
[PCI_ROM_RESOURCE
].start
)
604 cmd
|= PCI_COMMAND_MEMORY
;
605 if (cmd
!= old_cmd
) {
606 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev
), old_cmd
, cmd
);
607 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
612 static int next_controller_index
;
614 struct pci_controller
* __init
615 pcibios_alloc_controller(void)
617 struct pci_controller
*hose
;
619 hose
= (struct pci_controller
*)alloc_bootmem(sizeof(*hose
));
620 memset(hose
, 0, sizeof(struct pci_controller
));
623 hose_tail
= &hose
->next
;
625 hose
->index
= next_controller_index
++;
632 * Functions below are used on OpenFirmware machines.
635 make_one_node_map(struct device_node
* node
, u8 pci_bus
)
637 const int *bus_range
;
640 if (pci_bus
>= pci_bus_count
)
642 bus_range
= get_property(node
, "bus-range", &len
);
643 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
644 printk(KERN_WARNING
"Can't get bus-range for %s, "
645 "assuming it starts at 0\n", node
->full_name
);
646 pci_to_OF_bus_map
[pci_bus
] = 0;
648 pci_to_OF_bus_map
[pci_bus
] = bus_range
[0];
650 for (node
=node
->child
; node
!= 0;node
= node
->sibling
) {
652 const unsigned int *class_code
, *reg
;
654 class_code
= get_property(node
, "class-code", NULL
);
655 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
656 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
658 reg
= get_property(node
, "reg", NULL
);
661 dev
= pci_find_slot(pci_bus
, ((reg
[0] >> 8) & 0xff));
662 if (!dev
|| !dev
->subordinate
)
664 make_one_node_map(node
, dev
->subordinate
->number
);
669 pcibios_make_OF_bus_map(void)
672 struct pci_controller
* hose
;
673 struct property
*map_prop
;
675 pci_to_OF_bus_map
= (u8
*)kmalloc(pci_bus_count
, GFP_KERNEL
);
676 if (!pci_to_OF_bus_map
) {
677 printk(KERN_ERR
"Can't allocate OF bus map !\n");
681 /* We fill the bus map with invalid values, that helps
684 for (i
=0; i
<pci_bus_count
; i
++)
685 pci_to_OF_bus_map
[i
] = 0xff;
687 /* For each hose, we begin searching bridges */
688 for(hose
=hose_head
; hose
; hose
=hose
->next
) {
689 struct device_node
* node
;
690 node
= (struct device_node
*)hose
->arch_data
;
693 make_one_node_map(node
, hose
->first_busno
);
695 map_prop
= of_find_property(find_path_device("/"),
696 "pci-OF-bus-map", NULL
);
698 BUG_ON(pci_bus_count
> map_prop
->length
);
699 memcpy(map_prop
->value
, pci_to_OF_bus_map
, pci_bus_count
);
702 printk("PCI->OF bus map:\n");
703 for (i
=0; i
<pci_bus_count
; i
++) {
704 if (pci_to_OF_bus_map
[i
] == 0xff)
706 printk("%d -> %d\n", i
, pci_to_OF_bus_map
[i
]);
711 typedef int (*pci_OF_scan_iterator
)(struct device_node
* node
, void* data
);
713 static struct device_node
*
714 scan_OF_pci_childs(struct device_node
* node
, pci_OF_scan_iterator filter
, void* data
)
716 struct device_node
* sub_node
;
718 for (; node
!= 0;node
= node
->sibling
) {
719 const unsigned int *class_code
;
721 if (filter(node
, data
))
724 /* For PCI<->PCI bridges or CardBus bridges, we go down
725 * Note: some OFs create a parent node "multifunc-device" as
726 * a fake root for all functions of a multi-function device,
727 * we go down them as well.
729 class_code
= get_property(node
, "class-code", NULL
);
730 if ((!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
731 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
)) &&
732 strcmp(node
->name
, "multifunc-device"))
734 sub_node
= scan_OF_pci_childs(node
->child
, filter
, data
);
742 scan_OF_pci_childs_iterator(struct device_node
* node
, void* data
)
744 const unsigned int *reg
;
745 u8
* fdata
= (u8
*)data
;
747 reg
= get_property(node
, "reg", NULL
);
748 if (reg
&& ((reg
[0] >> 8) & 0xff) == fdata
[1]
749 && ((reg
[0] >> 16) & 0xff) == fdata
[0])
754 static struct device_node
*
755 scan_OF_childs_for_device(struct device_node
* node
, u8 bus
, u8 dev_fn
)
757 u8 filter_data
[2] = {bus
, dev_fn
};
759 return scan_OF_pci_childs(node
, scan_OF_pci_childs_iterator
, filter_data
);
763 * Scans the OF tree for a device node matching a PCI device
766 pci_busdev_to_OF_node(struct pci_bus
*bus
, int devfn
)
768 struct pci_controller
*hose
;
769 struct device_node
*node
;
775 /* Lookup the hose */
777 hose
= pci_bus_to_hose(busnr
);
781 /* Check it has an OF node associated */
782 node
= (struct device_node
*) hose
->arch_data
;
786 /* Fixup bus number according to what OF think it is. */
787 #ifdef CONFIG_PPC_PMAC
788 /* The G5 need a special case here. Basically, we don't remap all
789 * busses on it so we don't create the pci-OF-map. However, we do
790 * remap the AGP bus and so have to deal with it. A future better
791 * fix has to be done by making the remapping per-host and always
792 * filling the pci_to_OF map. --BenH
794 if (machine_is(powermac
) && busnr
>= 0xf0)
798 if (pci_to_OF_bus_map
)
799 busnr
= pci_to_OF_bus_map
[busnr
];
803 /* Now, lookup childs of the hose */
804 return scan_OF_childs_for_device(node
->child
, busnr
, devfn
);
806 EXPORT_SYMBOL(pci_busdev_to_OF_node
);
809 pci_device_to_OF_node(struct pci_dev
*dev
)
811 return pci_busdev_to_OF_node(dev
->bus
, dev
->devfn
);
813 EXPORT_SYMBOL(pci_device_to_OF_node
);
815 /* This routine is meant to be used early during boot, when the
816 * PCI bus numbers have not yet been assigned, and you need to
817 * issue PCI config cycles to an OF device.
818 * It could also be used to "fix" RTAS config cycles if you want
819 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
822 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
827 struct pci_controller
* hose
;
828 for (hose
=hose_head
;hose
;hose
=hose
->next
)
829 if (hose
->arch_data
== node
)
837 find_OF_pci_device_filter(struct device_node
* node
, void* data
)
839 return ((void *)node
== data
);
843 * Returns the PCI device matching a given OF node
846 pci_device_from_OF_node(struct device_node
* node
, u8
* bus
, u8
* devfn
)
848 const unsigned int *reg
;
849 struct pci_controller
* hose
;
850 struct pci_dev
* dev
= NULL
;
854 /* Make sure it's really a PCI device */
855 hose
= pci_find_hose_for_OF_device(node
);
856 if (!hose
|| !hose
->arch_data
)
858 if (!scan_OF_pci_childs(((struct device_node
*)hose
->arch_data
)->child
,
859 find_OF_pci_device_filter
, (void *)node
))
861 reg
= get_property(node
, "reg", NULL
);
864 *bus
= (reg
[0] >> 16) & 0xff;
865 *devfn
= ((reg
[0] >> 8) & 0xff);
867 /* Ok, here we need some tweak. If we have already renumbered
868 * all busses, we can't rely on the OF bus number any more.
869 * the pci_to_OF_bus_map is not enough as several PCI busses
870 * may match the same OF bus number.
872 if (!pci_to_OF_bus_map
)
875 for_each_pci_dev(dev
)
876 if (pci_to_OF_bus_map
[dev
->bus
->number
] == *bus
&&
877 dev
->devfn
== *devfn
) {
878 *bus
= dev
->bus
->number
;
885 EXPORT_SYMBOL(pci_device_from_OF_node
);
888 pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
889 struct device_node
*dev
, int primary
)
891 static unsigned int static_lc_ranges
[256] __initdata
;
892 const unsigned int *dt_ranges
;
893 unsigned int *lc_ranges
, *ranges
, *prev
, size
;
894 int rlen
= 0, orig_rlen
;
896 struct resource
*res
;
897 int np
, na
= prom_n_addr_cells(dev
);
900 /* First we try to merge ranges to fix a problem with some pmacs
901 * that can have more than 3 ranges, fortunately using contiguous
904 dt_ranges
= get_property(dev
, "ranges", &rlen
);
907 /* Sanity check, though hopefully that never happens */
908 if (rlen
> sizeof(static_lc_ranges
)) {
909 printk(KERN_WARNING
"OF ranges property too large !\n");
910 rlen
= sizeof(static_lc_ranges
);
912 lc_ranges
= static_lc_ranges
;
913 memcpy(lc_ranges
, dt_ranges
, rlen
);
916 /* Let's work on a copy of the "ranges" property instead of damaging
917 * the device-tree image in memory
921 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
923 if (prev
[0] == ranges
[0] && prev
[1] == ranges
[1] &&
924 (prev
[2] + prev
[na
+4]) == ranges
[2] &&
925 (prev
[na
+2] + prev
[na
+4]) == ranges
[na
+2]) {
926 prev
[na
+4] += ranges
[na
+4];
937 * The ranges property is laid out as an array of elements,
938 * each of which comprises:
939 * cells 0 - 2: a PCI address
940 * cells 3 or 3+4: a CPU physical address
941 * (size depending on dev->n_addr_cells)
942 * cells 4+5 or 5+6: the size of the range
946 while (ranges
&& (rlen
-= np
* sizeof(unsigned int)) >= 0) {
949 switch ((ranges
[0] >> 24) & 0x3) {
950 case 1: /* I/O space */
953 hose
->io_base_phys
= ranges
[na
+2];
954 /* limit I/O space to 16MB */
955 if (size
> 0x01000000)
957 hose
->io_base_virt
= ioremap(ranges
[na
+2], size
);
959 isa_io_base
= (unsigned long) hose
->io_base_virt
;
960 res
= &hose
->io_resource
;
961 res
->flags
= IORESOURCE_IO
;
962 res
->start
= ranges
[2];
963 DBG("PCI: IO 0x%llx -> 0x%llx\n",
964 res
->start
, res
->start
+ size
- 1);
966 case 2: /* memory space */
968 if (ranges
[1] == 0 && ranges
[2] == 0
969 && ranges
[na
+4] <= (16 << 20)) {
970 /* 1st 16MB, i.e. ISA memory area */
972 isa_mem_base
= ranges
[na
+2];
975 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
978 hose
->pci_mem_offset
= ranges
[na
+2] - ranges
[2];
980 res
= &hose
->mem_resources
[memno
];
981 res
->flags
= IORESOURCE_MEM
;
982 if(ranges
[0] & 0x40000000)
983 res
->flags
|= IORESOURCE_PREFETCH
;
984 res
->start
= ranges
[na
+2];
985 DBG("PCI: MEM[%d] 0x%llx -> 0x%llx\n", memno
,
986 res
->start
, res
->start
+ size
- 1);
991 res
->name
= dev
->full_name
;
992 res
->end
= res
->start
+ size
- 1;
1001 /* We create the "pci-OF-bus-map" property now so it appears in the
1005 pci_create_OF_bus_map(void)
1007 struct property
* of_prop
;
1009 of_prop
= (struct property
*) alloc_bootmem(sizeof(struct property
) + 256);
1010 if (of_prop
&& find_path_device("/")) {
1011 memset(of_prop
, -1, sizeof(struct property
) + 256);
1012 of_prop
->name
= "pci-OF-bus-map";
1013 of_prop
->length
= 256;
1014 of_prop
->value
= (unsigned char *)&of_prop
[1];
1015 prom_add_property(find_path_device("/"), of_prop
);
1019 static ssize_t
pci_show_devspec(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1021 struct pci_dev
*pdev
;
1022 struct device_node
*np
;
1024 pdev
= to_pci_dev (dev
);
1025 np
= pci_device_to_OF_node(pdev
);
1026 if (np
== NULL
|| np
->full_name
== NULL
)
1028 return sprintf(buf
, "%s", np
->full_name
);
1030 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
1032 #else /* CONFIG_PPC_OF */
1033 void pcibios_make_OF_bus_map(void)
1036 #endif /* CONFIG_PPC_OF */
1038 /* Add sysfs properties */
1039 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
1041 #ifdef CONFIG_PPC_OF
1042 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
1043 #endif /* CONFIG_PPC_OF */
1047 #ifdef CONFIG_PPC_PMAC
1049 * This set of routines checks for PCI<->PCI bridges that have closed
1050 * IO resources and have child devices. It tries to re-open an IO
1053 * This is a _temporary_ fix to workaround a problem with Apple's OF
1054 * closing IO windows on P2P bridges when the OF drivers of cards
1055 * below this bridge don't claim any IO range (typically ATI or
1058 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1059 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1060 * ordering when creating the host bus resources, and maybe a few more
1064 /* Initialize bridges with base/limit values we have collected */
1066 do_update_p2p_io_resource(struct pci_bus
*bus
, int enable_vga
)
1068 struct pci_dev
*bridge
= bus
->self
;
1069 struct pci_controller
* hose
= (struct pci_controller
*)bridge
->sysdata
;
1072 struct resource res
;
1074 if (bus
->resource
[0] == NULL
)
1076 res
= *(bus
->resource
[0]);
1078 DBG("Remapping Bus %d, bridge: %s\n", bus
->number
, pci_name(bridge
));
1079 res
.start
-= ((unsigned long) hose
->io_base_virt
- isa_io_base
);
1080 res
.end
-= ((unsigned long) hose
->io_base_virt
- isa_io_base
);
1081 DBG(" IO window: %016llx-%016llx\n", res
.start
, res
.end
);
1083 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1084 pci_read_config_dword(bridge
, PCI_IO_BASE
, &l
);
1086 l
|= (res
.start
>> 8) & 0x00f0;
1087 l
|= res
.end
& 0xf000;
1088 pci_write_config_dword(bridge
, PCI_IO_BASE
, l
);
1090 if ((l
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
1091 l
= (res
.start
>> 16) | (res
.end
& 0xffff0000);
1092 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, l
);
1095 pci_read_config_word(bridge
, PCI_COMMAND
, &w
);
1096 w
|= PCI_COMMAND_IO
;
1097 pci_write_config_word(bridge
, PCI_COMMAND
, w
);
1099 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1101 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
, &w
);
1102 w
|= PCI_BRIDGE_CTL_VGA
;
1103 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
, w
);
1108 /* This function is pretty basic and actually quite broken for the
1109 * general case, it's enough for us right now though. It's supposed
1110 * to tell us if we need to open an IO range at all or not and what
1114 check_for_io_childs(struct pci_bus
*bus
, struct resource
* res
, int *found_vga
)
1116 struct pci_dev
*dev
;
1120 #define push_end(res, mask) do { \
1121 BUG_ON((mask+1) & mask); \
1122 res->end = (res->end + mask) | mask; \
1125 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1126 u16
class = dev
->class >> 8;
1128 if (class == PCI_CLASS_DISPLAY_VGA
||
1129 class == PCI_CLASS_NOT_DEFINED_VGA
)
1131 if (class >> 8 == PCI_BASE_CLASS_BRIDGE
&& dev
->subordinate
)
1132 rc
|= check_for_io_childs(dev
->subordinate
, res
, found_vga
);
1133 if (class == PCI_CLASS_BRIDGE_CARDBUS
)
1134 push_end(res
, 0xfff);
1136 for (i
=0; i
<PCI_NUM_RESOURCES
; i
++) {
1138 unsigned long r_size
;
1140 if (dev
->class >> 8 == PCI_CLASS_BRIDGE_PCI
1141 && i
>= PCI_BRIDGE_RESOURCES
)
1143 r
= &dev
->resource
[i
];
1144 r_size
= r
->end
- r
->start
;
1147 if (r
->flags
& IORESOURCE_IO
&& (r_size
) != 0) {
1149 push_end(res
, r_size
);
1157 /* Here we scan all P2P bridges of a given level that have a closed
1158 * IO window. Note that the test for the presence of a VGA card should
1159 * be improved to take into account already configured P2P bridges,
1160 * currently, we don't see them and might end up configuring 2 bridges
1161 * with VGA pass through enabled
1164 do_fixup_p2p_level(struct pci_bus
*bus
)
1170 for (parent_io
=0; parent_io
<4; parent_io
++)
1171 if (bus
->resource
[parent_io
]
1172 && bus
->resource
[parent_io
]->flags
& IORESOURCE_IO
)
1177 list_for_each_entry(b
, &bus
->children
, node
) {
1178 struct pci_dev
*d
= b
->self
;
1179 struct pci_controller
* hose
= (struct pci_controller
*)d
->sysdata
;
1180 struct resource
*res
= b
->resource
[0];
1181 struct resource tmp_res
;
1185 memset(&tmp_res
, 0, sizeof(tmp_res
));
1186 tmp_res
.start
= bus
->resource
[parent_io
]->start
;
1188 /* We don't let low addresses go through that closed P2P bridge, well,
1189 * that may not be necessary but I feel safer that way
1191 if (tmp_res
.start
== 0)
1192 tmp_res
.start
= 0x1000;
1194 if (!list_empty(&b
->devices
) && res
&& res
->flags
== 0 &&
1195 res
!= bus
->resource
[parent_io
] &&
1196 (d
->class >> 8) == PCI_CLASS_BRIDGE_PCI
&&
1197 check_for_io_childs(b
, &tmp_res
, &found_vga
)) {
1200 printk(KERN_INFO
"Fixing up IO bus %s\n", b
->name
);
1204 printk(KERN_WARNING
"Skipping VGA, already active"
1205 " on bus segment\n");
1210 pci_read_config_byte(d
, PCI_IO_BASE
, &io_base_lo
);
1212 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
)
1213 max
= ((unsigned long) hose
->io_base_virt
1214 - isa_io_base
) + 0xffffffff;
1216 max
= ((unsigned long) hose
->io_base_virt
1217 - isa_io_base
) + 0xffff;
1220 res
->flags
= IORESOURCE_IO
;
1221 res
->name
= b
->name
;
1223 /* Find a resource in the parent where we can allocate */
1224 for (i
= 0 ; i
< 4; i
++) {
1225 struct resource
*r
= bus
->resource
[i
];
1228 if ((r
->flags
& IORESOURCE_IO
) == 0)
1230 DBG("Trying to allocate from %016llx, size %016llx from parent"
1231 " res %d: %016llx -> %016llx\n",
1232 res
->start
, res
->end
, i
, r
->start
, r
->end
);
1234 if (allocate_resource(r
, res
, res
->end
+ 1, res
->start
, max
,
1235 res
->end
+ 1, NULL
, NULL
) < 0) {
1239 do_update_p2p_io_resource(b
, found_vga
);
1243 do_fixup_p2p_level(b
);
1248 pcibios_fixup_p2p_bridges(void)
1252 list_for_each_entry(b
, &pci_root_buses
, node
)
1253 do_fixup_p2p_level(b
);
1256 #endif /* CONFIG_PPC_PMAC */
1261 struct pci_controller
*hose
;
1262 struct pci_bus
*bus
;
1265 printk(KERN_INFO
"PCI: Probing PCI hardware\n");
1267 /* Scan all of the recorded PCI controllers. */
1268 for (next_busno
= 0, hose
= hose_head
; hose
; hose
= hose
->next
) {
1269 if (pci_assign_all_buses
)
1270 hose
->first_busno
= next_busno
;
1271 hose
->last_busno
= 0xff;
1272 bus
= pci_scan_bus_parented(hose
->parent
, hose
->first_busno
,
1275 pci_bus_add_devices(bus
);
1276 hose
->last_busno
= bus
->subordinate
;
1277 if (pci_assign_all_buses
|| next_busno
<= hose
->last_busno
)
1278 next_busno
= hose
->last_busno
+ pcibios_assign_bus_offset
;
1280 pci_bus_count
= next_busno
;
1282 /* OpenFirmware based machines need a map of OF bus
1283 * numbers vs. kernel bus numbers since we may have to
1286 if (pci_assign_all_buses
&& have_of
)
1287 pcibios_make_OF_bus_map();
1289 /* Call machine dependent fixup */
1290 if (ppc_md
.pcibios_fixup
)
1291 ppc_md
.pcibios_fixup();
1293 /* Allocate and assign resources */
1294 pcibios_allocate_bus_resources(&pci_root_buses
);
1295 pcibios_allocate_resources(0);
1296 pcibios_allocate_resources(1);
1297 #ifdef CONFIG_PPC_PMAC
1298 pcibios_fixup_p2p_bridges();
1299 #endif /* CONFIG_PPC_PMAC */
1300 pcibios_assign_resources();
1302 /* Call machine dependent post-init code */
1303 if (ppc_md
.pcibios_after_init
)
1304 ppc_md
.pcibios_after_init();
1309 subsys_initcall(pcibios_init
);
1311 unsigned long resource_fixup(struct pci_dev
* dev
, struct resource
* res
,
1312 unsigned long start
, unsigned long size
)
1317 void __init
pcibios_fixup_bus(struct pci_bus
*bus
)
1319 struct pci_controller
*hose
= (struct pci_controller
*) bus
->sysdata
;
1320 unsigned long io_offset
;
1321 struct resource
*res
;
1322 struct pci_dev
*dev
;
1325 io_offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1326 if (bus
->parent
== NULL
) {
1327 /* This is a host bridge - fill in its resources */
1330 bus
->resource
[0] = res
= &hose
->io_resource
;
1333 printk(KERN_ERR
"I/O resource not set for host"
1334 " bridge %d\n", hose
->index
);
1336 res
->end
= IO_SPACE_LIMIT
;
1337 res
->flags
= IORESOURCE_IO
;
1339 res
->start
+= io_offset
;
1340 res
->end
+= io_offset
;
1342 for (i
= 0; i
< 3; ++i
) {
1343 res
= &hose
->mem_resources
[i
];
1347 printk(KERN_ERR
"Memory resource not set for "
1348 "host bridge %d\n", hose
->index
);
1349 res
->start
= hose
->pci_mem_offset
;
1351 res
->flags
= IORESOURCE_MEM
;
1353 bus
->resource
[i
+1] = res
;
1356 /* This is a subordinate bridge */
1357 pci_read_bridge_bases(bus
);
1359 for (i
= 0; i
< 4; ++i
) {
1360 if ((res
= bus
->resource
[i
]) == NULL
)
1364 if (io_offset
&& (res
->flags
& IORESOURCE_IO
)) {
1365 res
->start
+= io_offset
;
1366 res
->end
+= io_offset
;
1367 } else if (hose
->pci_mem_offset
1368 && (res
->flags
& IORESOURCE_MEM
)) {
1369 res
->start
+= hose
->pci_mem_offset
;
1370 res
->end
+= hose
->pci_mem_offset
;
1375 /* Platform specific bus fixups */
1376 if (ppc_md
.pcibios_fixup_bus
)
1377 ppc_md
.pcibios_fixup_bus(bus
);
1379 /* Read default IRQs and fixup if necessary */
1380 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1381 pci_read_irq_line(dev
);
1382 if (ppc_md
.pci_irq_fixup
)
1383 ppc_md
.pci_irq_fixup(dev
);
1387 char __init
*pcibios_setup(char *str
)
1392 /* the next one is stolen from the alpha port... */
1394 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
1396 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
1397 /* XXX FIXME - update OF device tree node interrupt property */
1400 #ifdef CONFIG_PPC_MERGE
1401 /* XXX This is a copy of the ppc64 version. This is temporary until we start
1402 * merging the 2 PCI layers
1405 * Reads the interrupt pin to determine if interrupt is use by card.
1406 * If the interrupt is used, then gets the interrupt line from the
1407 * openfirmware and sets it in the pci_dev and pci_config line.
1409 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1414 DBG("Try to map irq for %s...\n", pci_name(pci_dev
));
1416 /* Try to get a mapping from the device-tree */
1417 if (of_irq_map_pci(pci_dev
, &oirq
)) {
1420 /* If that fails, lets fallback to what is in the config
1421 * space and map that through the default controller. We
1422 * also set the type to level low since that's what PCI
1423 * interrupts are. If your platform does differently, then
1424 * either provide a proper interrupt tree or don't use this
1427 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
1431 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
1435 DBG(" -> no map ! Using irq line %d from PCI config\n", line
);
1437 virq
= irq_create_mapping(NULL
, line
);
1439 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
1441 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n",
1442 oirq
.size
, oirq
.specifier
[0], oirq
.controller
->full_name
);
1444 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
1447 if(virq
== NO_IRQ
) {
1448 DBG(" -> failed to map !\n");
1451 pci_dev
->irq
= virq
;
1452 pci_write_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, virq
);
1456 EXPORT_SYMBOL(pci_read_irq_line
);
1457 #endif /* CONFIG_PPC_MERGE */
1459 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1465 if (ppc_md
.pcibios_enable_device_hook
)
1466 if (ppc_md
.pcibios_enable_device_hook(dev
, 0))
1469 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1471 for (idx
=0; idx
<6; idx
++) {
1472 r
= &dev
->resource
[idx
];
1473 if (r
->flags
& IORESOURCE_UNSET
) {
1474 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", pci_name(dev
));
1477 if (r
->flags
& IORESOURCE_IO
)
1478 cmd
|= PCI_COMMAND_IO
;
1479 if (r
->flags
& IORESOURCE_MEM
)
1480 cmd
|= PCI_COMMAND_MEMORY
;
1482 if (cmd
!= old_cmd
) {
1483 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1484 pci_name(dev
), old_cmd
, cmd
);
1485 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1490 struct pci_controller
*
1491 pci_bus_to_hose(int bus
)
1493 struct pci_controller
* hose
= hose_head
;
1495 for (; hose
; hose
= hose
->next
)
1496 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
1502 pci_bus_io_base(unsigned int bus
)
1504 struct pci_controller
*hose
;
1506 hose
= pci_bus_to_hose(bus
);
1509 return hose
->io_base_virt
;
1513 pci_bus_io_base_phys(unsigned int bus
)
1515 struct pci_controller
*hose
;
1517 hose
= pci_bus_to_hose(bus
);
1520 return hose
->io_base_phys
;
1524 pci_bus_mem_base_phys(unsigned int bus
)
1526 struct pci_controller
*hose
;
1528 hose
= pci_bus_to_hose(bus
);
1531 return hose
->pci_mem_offset
;
1535 pci_resource_to_bus(struct pci_dev
*pdev
, struct resource
*res
)
1537 /* Hack alert again ! See comments in chrp_pci.c
1539 struct pci_controller
* hose
=
1540 (struct pci_controller
*)pdev
->sysdata
;
1541 if (hose
&& res
->flags
& IORESOURCE_MEM
)
1542 return res
->start
- hose
->pci_mem_offset
;
1543 /* We may want to do something with IOs here... */
1548 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
1549 unsigned long *offset
,
1550 enum pci_mmap_state mmap_state
)
1552 struct pci_controller
*hose
= pci_bus_to_hose(dev
->bus
->number
);
1553 unsigned long io_offset
= 0;
1557 return NULL
; /* should never happen */
1559 /* If memory, add on the PCI bridge address offset */
1560 if (mmap_state
== pci_mmap_mem
) {
1561 *offset
+= hose
->pci_mem_offset
;
1562 res_bit
= IORESOURCE_MEM
;
1564 io_offset
= hose
->io_base_virt
- ___IO_BASE
;
1565 *offset
+= io_offset
;
1566 res_bit
= IORESOURCE_IO
;
1570 * Check that the offset requested corresponds to one of the
1571 * resources of the device.
1573 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
1574 struct resource
*rp
= &dev
->resource
[i
];
1575 int flags
= rp
->flags
;
1577 /* treat ROM as memory (should be already) */
1578 if (i
== PCI_ROM_RESOURCE
)
1579 flags
|= IORESOURCE_MEM
;
1581 /* Active and same type? */
1582 if ((flags
& res_bit
) == 0)
1585 /* In the range of this resource? */
1586 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
1589 /* found it! construct the final physical address */
1590 if (mmap_state
== pci_mmap_io
)
1591 *offset
+= hose
->io_base_phys
- io_offset
;
1599 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1602 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
1603 pgprot_t protection
,
1604 enum pci_mmap_state mmap_state
,
1607 unsigned long prot
= pgprot_val(protection
);
1609 /* Write combine is always 0 on non-memory space mappings. On
1610 * memory space, if the user didn't pass 1, we check for a
1611 * "prefetchable" resource. This is a bit hackish, but we use
1612 * this to workaround the inability of /sysfs to provide a write
1615 if (mmap_state
!= pci_mmap_mem
)
1617 else if (write_combine
== 0) {
1618 if (rp
->flags
& IORESOURCE_PREFETCH
)
1622 /* XXX would be nice to have a way to ask for write-through */
1623 prot
|= _PAGE_NO_CACHE
;
1625 prot
&= ~_PAGE_GUARDED
;
1627 prot
|= _PAGE_GUARDED
;
1629 printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev
),
1630 (unsigned long long)rp
->start
, prot
);
1632 return __pgprot(prot
);
1636 * This one is used by /dev/mem and fbdev who have no clue about the
1637 * PCI device, it tries to find the PCI device first and calls the
1640 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
1643 pgprot_t protection
)
1645 struct pci_dev
*pdev
= NULL
;
1646 struct resource
*found
= NULL
;
1647 unsigned long prot
= pgprot_val(protection
);
1648 unsigned long offset
= pfn
<< PAGE_SHIFT
;
1651 if (page_is_ram(pfn
))
1654 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
1656 for_each_pci_dev(pdev
) {
1657 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
1658 struct resource
*rp
= &pdev
->resource
[i
];
1659 int flags
= rp
->flags
;
1661 /* Active and same type? */
1662 if ((flags
& IORESOURCE_MEM
) == 0)
1664 /* In the range of this resource? */
1665 if (offset
< (rp
->start
& PAGE_MASK
) ||
1675 if (found
->flags
& IORESOURCE_PREFETCH
)
1676 prot
&= ~_PAGE_GUARDED
;
1680 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
1682 return __pgprot(prot
);
1687 * Perform the actual remap of the pages for a PCI device mapping, as
1688 * appropriate for this architecture. The region in the process to map
1689 * is described by vm_start and vm_end members of VMA, the base physical
1690 * address is found in vm_pgoff.
1691 * The pci device structure is provided so that architectures may make mapping
1692 * decisions on a per-device or per-bus basis.
1694 * Returns a negative error code on failure, zero on success.
1696 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1697 enum pci_mmap_state mmap_state
,
1700 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
1701 struct resource
*rp
;
1704 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
1708 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
1709 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
1711 mmap_state
, write_combine
);
1713 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
1714 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
1719 /* Obsolete functions. Should be removed once the symbios driver
1723 phys_to_bus(unsigned long pa
)
1725 struct pci_controller
*hose
;
1728 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
1729 for (i
= 0; i
< 3; ++i
) {
1730 if (pa
>= hose
->mem_resources
[i
].start
1731 && pa
<= hose
->mem_resources
[i
].end
) {
1733 * XXX the hose->pci_mem_offset really
1734 * only applies to mem_resources[0].
1735 * We need a way to store an offset for
1736 * the others. -- paulus
1739 pa
-= hose
->pci_mem_offset
;
1744 /* hmmm, didn't find it */
1749 pci_phys_to_bus(unsigned long pa
, int busnr
)
1751 struct pci_controller
* hose
= pci_bus_to_hose(busnr
);
1754 return pa
- hose
->pci_mem_offset
;
1758 pci_bus_to_phys(unsigned int ba
, int busnr
)
1760 struct pci_controller
* hose
= pci_bus_to_hose(busnr
);
1763 return ba
+ hose
->pci_mem_offset
;
1766 /* Provide information on locations of various I/O regions in physical
1767 * memory. Do this on a per-card basis so that we choose the right
1769 * Note that the returned IO or memory base is a physical address
1772 long sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
1774 struct pci_controller
* hose
;
1775 long result
= -EOPNOTSUPP
;
1777 /* Argh ! Please forgive me for that hack, but that's the
1778 * simplest way to get existing XFree to not lockup on some
1779 * G5 machines... So when something asks for bus 0 io base
1780 * (bus 0 is HT root), we return the AGP one instead.
1782 #ifdef CONFIG_PPC_PMAC
1783 if (machine_is(powermac
) && machine_is_compatible("MacRISC4"))
1786 #endif /* CONFIG_PPC_PMAC */
1788 hose
= pci_bus_to_hose(bus
);
1793 case IOBASE_BRIDGE_NUMBER
:
1794 return (long)hose
->first_busno
;
1796 return (long)hose
->pci_mem_offset
;
1798 return (long)hose
->io_base_phys
;
1800 return (long)isa_io_base
;
1801 case IOBASE_ISA_MEM
:
1802 return (long)isa_mem_base
;
1808 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1809 const struct resource
*rsrc
,
1810 resource_size_t
*start
, resource_size_t
*end
)
1812 struct pci_controller
*hose
= pci_bus_to_hose(dev
->bus
->number
);
1813 unsigned long offset
= 0;
1818 if (rsrc
->flags
& IORESOURCE_IO
)
1819 offset
= ___IO_BASE
- hose
->io_base_virt
+ hose
->io_base_phys
;
1821 *start
= rsrc
->start
+ offset
;
1822 *end
= rsrc
->end
+ offset
;
1826 pci_init_resource(struct resource
*res
, unsigned long start
, unsigned long end
,
1827 int flags
, char *name
)
1834 res
->sibling
= NULL
;
1838 void __iomem
*pci_iomap(struct pci_dev
*dev
, int bar
, unsigned long max
)
1840 unsigned long start
= pci_resource_start(dev
, bar
);
1841 unsigned long len
= pci_resource_len(dev
, bar
);
1842 unsigned long flags
= pci_resource_flags(dev
, bar
);
1846 if (max
&& len
> max
)
1848 if (flags
& IORESOURCE_IO
)
1849 return ioport_map(start
, len
);
1850 if (flags
& IORESOURCE_MEM
)
1851 /* Not checking IORESOURCE_CACHEABLE because PPC does
1852 * not currently distinguish between ioremap and
1855 return ioremap(start
, len
);
1860 void pci_iounmap(struct pci_dev
*dev
, void __iomem
*addr
)
1864 EXPORT_SYMBOL(pci_iomap
);
1865 EXPORT_SYMBOL(pci_iounmap
);
1867 unsigned long pci_address_to_pio(phys_addr_t address
)
1869 struct pci_controller
* hose
= hose_head
;
1871 for (; hose
; hose
= hose
->next
) {
1872 unsigned int size
= hose
->io_resource
.end
-
1873 hose
->io_resource
.start
+ 1;
1874 if (address
>= hose
->io_base_phys
&&
1875 address
< (hose
->io_base_phys
+ size
)) {
1876 unsigned long base
=
1877 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1878 return base
+ (address
- hose
->io_base_phys
);
1881 return (unsigned int)-1;
1883 EXPORT_SYMBOL(pci_address_to_pio
);
1886 * Null PCI config access functions, for the case when we can't
1889 #define NULL_PCI_OP(rw, size, type) \
1891 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1893 return PCIBIOS_DEVICE_NOT_FOUND; \
1897 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1900 return PCIBIOS_DEVICE_NOT_FOUND
;
1904 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1907 return PCIBIOS_DEVICE_NOT_FOUND
;
1910 static struct pci_ops null_pci_ops
=
1917 * These functions are used early on before PCI scanning is done
1918 * and all of the pci_dev and pci_bus structures have been created.
1920 static struct pci_bus
*
1921 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1923 static struct pci_bus bus
;
1926 hose
= pci_bus_to_hose(busnr
);
1928 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1932 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1936 #define EARLY_PCI_OP(rw, size, type) \
1937 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1938 int devfn, int offset, type value) \
1940 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1941 devfn, offset, value); \
1944 EARLY_PCI_OP(read
, byte
, u8
*)
1945 EARLY_PCI_OP(read
, word
, u16
*)
1946 EARLY_PCI_OP(read
, dword
, u32
*)
1947 EARLY_PCI_OP(write
, byte
, u8
)
1948 EARLY_PCI_OP(write
, word
, u16
)
1949 EARLY_PCI_OP(write
, dword
, u32
)