2 * Kernel execution entry point code.
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include "head_booke.h"
46 /* As with the other PowerPC ports, it is expected that when code
47 * execution begins here, the following registers contain valid, yet
48 * optional, information:
50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
51 * r4 - Starting address of the init RAM disk
52 * r5 - Ending address of the init RAM disk
53 * r6 - Start of kernel command line string (e.g. "mem=128")
54 * r7 - End of kernel command line string
61 * Reserve a word at a fixed location to store the address
66 * Save parameters we are passed
73 li r25,0 /* phys kernel start (low) */
74 li r24,0 /* CPU number */
75 li r23,0 /* phys kernel start (high) */
77 /* We try to not make any assumptions about how the boot loader
78 * setup or used the TLBs. We invalidate all mappings from the
79 * boot loader and load a single entry in TLB1[0] to map the
80 * first 64M of kernel memory. Any boot info passed from the
81 * bootloader needs to live in this first 64M.
83 * Requirement on bootloader:
84 * - The page we're executing in needs to reside in TLB1 and
85 * have IPROT=1. If not an invalidate broadcast could
86 * evict the entry we're currently executing in.
88 * r3 = Index of TLB1 were executing in
89 * r4 = Current MSR[IS]
90 * r5 = Index of TLB1 temp mapping
92 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
98 #define ENTRY_MAPPING_BOOT_SETUP
99 #include "fsl_booke_entry_mapping.S"
100 #undef ENTRY_MAPPING_BOOT_SETUP
102 /* Establish the interrupt vector offsets */
103 SET_IVOR(0, CriticalInput);
104 SET_IVOR(1, MachineCheck);
105 SET_IVOR(2, DataStorage);
106 SET_IVOR(3, InstructionStorage);
107 SET_IVOR(4, ExternalInput);
108 SET_IVOR(5, Alignment);
109 SET_IVOR(6, Program);
110 SET_IVOR(7, FloatingPointUnavailable);
111 SET_IVOR(8, SystemCall);
112 SET_IVOR(9, AuxillaryProcessorUnavailable);
113 SET_IVOR(10, Decrementer);
114 SET_IVOR(11, FixedIntervalTimer);
115 SET_IVOR(12, WatchdogTimer);
116 SET_IVOR(13, DataTLBError);
117 SET_IVOR(14, InstructionTLBError);
118 SET_IVOR(15, DebugCrit);
120 /* Establish the interrupt vector base */
121 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
124 /* Setup the defaults for TLB entries */
125 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
127 oris r2,r2,MAS4_TLBSELD(1)@h
134 oris r2,r2,HID0_DOZE@h
138 #if !defined(CONFIG_BDI_SWITCH)
140 * The Abatron BDI JTAG debugger does not tolerate others
141 * mucking with the debug registers.
146 /* clear any residual debug events */
152 /* Check to see if we're the second processor, and jump
153 * to the secondary_start code if so
157 bne __secondary_start
161 * This is where the main kernel code starts.
166 ori r2,r2,init_task@l
168 /* ptr to current thread */
169 addi r4,r2,THREAD /* init task's THREAD */
170 mtspr SPRN_SPRG_THREAD,r4
173 lis r1,init_thread_union@h
174 ori r1,r1,init_thread_union@l
176 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
180 #ifdef CONFIG_RELOCATABLE
181 lis r3,kernstart_addr@ha
182 la r3,kernstart_addr@l(r3)
183 #ifdef CONFIG_PHYS_64BIT
192 * Decide what sort of machine this is and initialize the MMU.
202 /* Setup PTE pointers for the Abatron bdiGDB */
203 lis r6, swapper_pg_dir@h
204 ori r6, r6, swapper_pg_dir@l
205 lis r5, abatron_pteptrs@h
206 ori r5, r5, abatron_pteptrs@l
208 ori r4, r4, KERNELBASE@l
209 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
213 lis r4,start_kernel@h
214 ori r4,r4,start_kernel@l
216 ori r3,r3,MSR_KERNEL@l
219 rfi /* change context and jump to start_kernel */
221 /* Macros to hide the PTE size differences
223 * FIND_PTE -- walks the page tables given EA & pgdir pointer
225 * r11 -- PGDIR pointer
227 * label 2: is the bailout case
229 * if we find the pte (fall through):
230 * r11 is low pte word
231 * r12 is pointer to the pte
233 #ifdef CONFIG_PTE_64BIT
235 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
236 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
237 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
238 beq 2f; /* Bail if no table */ \
239 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
240 lwz r11, 4(r12); /* Get pte entry */
243 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
244 lwz r11, 0(r11); /* Get L1 entry */ \
245 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
246 beq 2f; /* Bail if no table */ \
247 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
248 lwz r11, 0(r12); /* Get Linux PTE */
252 * Interrupt vector entry code
254 * The Book E MMUs are always on so we don't need to handle
255 * interrupts in real mode as with previous PPC processors. In
256 * this case we handle interrupts in the kernel virtual address
259 * Interrupt vectors are dynamically placed relative to the
260 * interrupt prefix as determined by the address of interrupt_base.
261 * The interrupt vectors offsets are programmed using the labels
262 * for each interrupt vector entry.
264 * Interrupt vectors must be aligned on a 16 byte boundary.
265 * We align on a 32 byte cache line boundary for good measure.
269 /* Critical Input Interrupt */
270 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
272 /* Machine Check Interrupt */
274 /* no RFMCI, MCSRRs on E200 */
275 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
277 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
280 /* Data Storage Interrupt */
281 START_EXCEPTION(DataStorage)
282 NORMAL_EXCEPTION_PROLOG
283 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
285 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
286 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
288 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
290 addi r3,r1,STACK_FRAME_OVERHEAD
291 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
293 /* Instruction Storage Interrupt */
294 INSTRUCTION_STORAGE_EXCEPTION
296 /* External Input Interrupt */
297 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
299 /* Alignment Interrupt */
302 /* Program Interrupt */
305 /* Floating Point Unavailable Interrupt */
306 #ifdef CONFIG_PPC_FPU
307 FP_UNAVAILABLE_EXCEPTION
310 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
311 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
313 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
317 /* System Call Interrupt */
318 START_EXCEPTION(SystemCall)
319 NORMAL_EXCEPTION_PROLOG
320 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
322 /* Auxillary Processor Unavailable Interrupt */
323 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
325 /* Decrementer Interrupt */
326 DECREMENTER_EXCEPTION
328 /* Fixed Internal Timer Interrupt */
329 /* TODO: Add FIT support */
330 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
332 /* Watchdog Timer Interrupt */
333 #ifdef CONFIG_BOOKE_WDT
334 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
336 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
339 /* Data TLB Error Interrupt */
340 START_EXCEPTION(DataTLBError)
341 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
342 mtspr SPRN_SPRG_WSCRATCH1, r11
343 mtspr SPRN_SPRG_WSCRATCH2, r12
344 mtspr SPRN_SPRG_WSCRATCH3, r13
346 mtspr SPRN_SPRG_WSCRATCH4, r11
347 mfspr r10, SPRN_DEAR /* Get faulting address */
349 /* If we are faulting a kernel address, we have to use the
350 * kernel page tables.
352 lis r11, PAGE_OFFSET@h
355 lis r11, swapper_pg_dir@h
356 ori r11, r11, swapper_pg_dir@l
358 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
359 rlwinm r12,r12,0,16,1
364 /* Get the PGD for the current thread */
366 mfspr r11,SPRN_SPRG_THREAD
370 /* Mask of required permission bits. Note that while we
371 * do copy ESR:ST to _PAGE_RW position as trying to write
372 * to an RO page is pretty common, we don't do it with
373 * _PAGE_DIRTY. We could do it, but it's a fairly rare
374 * event so I'd rather take the overhead when it happens
375 * rather than adding an instruction here. We should measure
376 * whether the whole thing is worth it in the first place
377 * as we could avoid loading SPRN_ESR completely in the first
380 * TODO: Is it worth doing that mfspr & rlwimi in the first
381 * place or can we save a couple of instructions here ?
384 #ifdef CONFIG_PTE_64BIT
386 oris r13,r13,_PAGE_ACCESSED@h
388 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
390 rlwimi r13,r12,11,29,29
393 andc. r13,r13,r11 /* Check permission */
395 #ifdef CONFIG_PTE_64BIT
397 subf r10,r11,r12 /* create false data dep */
398 lwzx r13,r11,r10 /* Get upper pte bits */
400 lwz r13,0(r12) /* Get upper pte bits */
404 bne 2f /* Bail if permission/valid mismach */
406 /* Jump to common tlb load */
409 /* The bailout. Restore registers to pre-exception conditions
410 * and call the heavyweights to help us out.
412 mfspr r11, SPRN_SPRG_RSCRATCH4
414 mfspr r13, SPRN_SPRG_RSCRATCH3
415 mfspr r12, SPRN_SPRG_RSCRATCH2
416 mfspr r11, SPRN_SPRG_RSCRATCH1
417 mfspr r10, SPRN_SPRG_RSCRATCH0
420 /* Instruction TLB Error Interrupt */
422 * Nearly the same as above, except we get our
423 * information from different registers and bailout
424 * to a different point.
426 START_EXCEPTION(InstructionTLBError)
427 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
428 mtspr SPRN_SPRG_WSCRATCH1, r11
429 mtspr SPRN_SPRG_WSCRATCH2, r12
430 mtspr SPRN_SPRG_WSCRATCH3, r13
432 mtspr SPRN_SPRG_WSCRATCH4, r11
433 mfspr r10, SPRN_SRR0 /* Get faulting address */
435 /* If we are faulting a kernel address, we have to use the
436 * kernel page tables.
438 lis r11, PAGE_OFFSET@h
441 lis r11, swapper_pg_dir@h
442 ori r11, r11, swapper_pg_dir@l
444 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
445 rlwinm r12,r12,0,16,1
448 /* Make up the required permissions for kernel code */
449 #ifdef CONFIG_PTE_64BIT
450 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
451 oris r13,r13,_PAGE_ACCESSED@h
453 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
457 /* Get the PGD for the current thread */
459 mfspr r11,SPRN_SPRG_THREAD
462 /* Make up the required permissions for user code */
463 #ifdef CONFIG_PTE_64BIT
464 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
465 oris r13,r13,_PAGE_ACCESSED@h
467 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
472 andc. r13,r13,r11 /* Check permission */
474 #ifdef CONFIG_PTE_64BIT
476 subf r10,r11,r12 /* create false data dep */
477 lwzx r13,r11,r10 /* Get upper pte bits */
479 lwz r13,0(r12) /* Get upper pte bits */
483 bne 2f /* Bail if permission mismach */
485 /* Jump to common TLB load point */
489 /* The bailout. Restore registers to pre-exception conditions
490 * and call the heavyweights to help us out.
492 mfspr r11, SPRN_SPRG_RSCRATCH4
494 mfspr r13, SPRN_SPRG_RSCRATCH3
495 mfspr r12, SPRN_SPRG_RSCRATCH2
496 mfspr r11, SPRN_SPRG_RSCRATCH1
497 mfspr r10, SPRN_SPRG_RSCRATCH0
501 /* SPE Unavailable */
502 START_EXCEPTION(SPEUnavailable)
503 NORMAL_EXCEPTION_PROLOG
505 addi r3,r1,STACK_FRAME_OVERHEAD
506 EXC_XFER_EE_LITE(0x2010, KernelSPE)
508 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
509 #endif /* CONFIG_SPE */
511 /* SPE Floating Point Data */
513 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
515 /* SPE Floating Point Round */
516 EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
518 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
519 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
520 #endif /* CONFIG_SPE */
522 /* Performance Monitor */
523 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
525 EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
527 CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
529 /* Debug Interrupt */
530 DEBUG_DEBUG_EXCEPTION
538 * Both the instruction and data TLB miss get to this
539 * point to load the TLB.
540 * r10 - available to use
541 * r11 - TLB (info from Linux PTE)
542 * r12 - available to use
543 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
544 * CR5 - results of addr >= PAGE_OFFSET
545 * MAS0, MAS1 - loaded with proper value when we get here
546 * MAS2, MAS3 - will need additional info from Linux PTE
547 * Upon exit, we reload everything and RFI.
551 * We set execute, because we don't have the granularity to
552 * properly set this at the page level (Linux problem).
553 * Many of these bits are software only. Bits we don't set
554 * here we (properly should) assume have the appropriate value.
558 #ifdef CONFIG_PTE_64BIT
559 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
561 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
565 #ifdef CONFIG_PTE_64BIT
566 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
567 andi. r10, r11, _PAGE_DIRTY
569 li r10, MAS3_SW | MAS3_UW
571 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
572 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
574 BEGIN_MMU_FTR_SECTION
575 srwi r10, r13, 12 /* grab RPN[12:31] */
577 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
579 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
580 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
582 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
586 rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
590 /* Round robin TLB1 entries assignment */
593 /* Extract TLB1CFG(NENTRY) */
594 mfspr r11, SPRN_TLB1CFG
595 andi. r11, r11, 0xfff
597 /* Extract MAS0(NV) */
598 andi. r13, r12, 0xfff
603 /* check if we need to wrap */
606 /* wrap back to first free tlbcam entry */
607 lis r13, tlbcam_index@ha
608 lwz r13, tlbcam_index@l(r13)
609 rlwimi r12, r13, 0, 20, 31
612 #endif /* CONFIG_E200 */
616 /* Done...restore registers and get out of here. */
617 mfspr r11, SPRN_SPRG_RSCRATCH4
619 mfspr r13, SPRN_SPRG_RSCRATCH3
620 mfspr r12, SPRN_SPRG_RSCRATCH2
621 mfspr r11, SPRN_SPRG_RSCRATCH1
622 mfspr r10, SPRN_SPRG_RSCRATCH0
623 rfi /* Force context change */
626 /* Note that the SPE support is closely modeled after the AltiVec
627 * support. Changes to one are likely to be applicable to the
631 * Disable SPE for the task which had SPE previously,
632 * and save its SPE registers in its thread_struct.
633 * Enables SPE for use in the kernel on return.
634 * On SMP we know the SPE units are free, since we give it up every
639 mtmsr r5 /* enable use of SPE now */
642 * For SMP, we don't do lazy SPE switching because it just gets too
643 * horrendously complex, especially when a task switches from one CPU
644 * to another. Instead we call giveup_spe in switch_to.
647 lis r3,last_task_used_spe@ha
648 lwz r4,last_task_used_spe@l(r3)
651 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
652 SAVE_32EVRS(0,r10,r4)
653 evxor evr10, evr10, evr10 /* clear out evr10 */
654 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
656 evstddx evr10, r4, r5 /* save off accumulator */
658 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
660 andc r4,r4,r10 /* disable SPE for previous task */
661 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
663 #endif /* !CONFIG_SMP */
664 /* enable use of SPE after return */
666 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
669 stw r4,THREAD_USED_SPE(r5)
672 REST_32EVRS(0,r10,r5)
675 stw r4,last_task_used_spe@l(r3)
676 #endif /* !CONFIG_SMP */
677 /* restore registers and return */
678 2: REST_4GPRS(3, r11)
693 * SPE unavailable trap from kernel - print a message, but let
694 * the task use SPE in the kernel until it returns to user mode.
699 stw r3,_MSR(r1) /* enable use of SPE after return */
703 mr r4,r2 /* current */
709 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
713 #endif /* CONFIG_SPE */
719 /* Adjust or setup IVORs for e200 */
720 _GLOBAL(__setup_e200_ivors)
723 li r3,SPEUnavailable@l
725 li r3,SPEFloatingPointData@l
727 li r3,SPEFloatingPointRound@l
732 /* Adjust or setup IVORs for e500v1/v2 */
733 _GLOBAL(__setup_e500_ivors)
736 li r3,SPEUnavailable@l
738 li r3,SPEFloatingPointData@l
740 li r3,SPEFloatingPointRound@l
742 li r3,PerformanceMonitor@l
747 /* Adjust or setup IVORs for e500mc */
748 _GLOBAL(__setup_e500mc_ivors)
751 li r3,PerformanceMonitor@l
755 li r3,CriticalDoorbell@l
761 * extern void giveup_altivec(struct task_struct *prev)
763 * The e500 core does not have an AltiVec unit.
765 _GLOBAL(giveup_altivec)
770 * extern void giveup_spe(struct task_struct *prev)
776 mtmsr r5 /* enable use of SPE now */
779 beqlr- /* if no previous owner, done */
780 addi r3,r3,THREAD /* want THREAD of task */
783 SAVE_32EVRS(0, r4, r3)
784 evxor evr6, evr6, evr6 /* clear out evr6 */
785 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
787 evstddx evr6, r4, r3 /* save off accumulator */
788 mfspr r6,SPRN_SPEFSCR
789 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
791 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
793 andc r4,r4,r3 /* disable SPE for previous task */
794 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
798 lis r4,last_task_used_spe@ha
799 stw r5,last_task_used_spe@l(r4)
800 #endif /* !CONFIG_SMP */
802 #endif /* CONFIG_SPE */
805 * extern void giveup_fpu(struct task_struct *prev)
807 * Not all FSL Book-E cores have an FPU
809 #ifndef CONFIG_PPC_FPU
815 * extern void abort(void)
817 * At present, this routine just applies a system reset.
821 mtspr SPRN_DBCR0,r13 /* disable all debug events */
824 ori r13,r13,MSR_DE@l /* Enable Debug Events */
828 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
834 #ifdef CONFIG_BDI_SWITCH
835 /* Context switch the PTE pointer for the Abatron BDI2000.
836 * The PGDIR is the second parameter.
838 lis r5, abatron_pteptrs@h
839 ori r5, r5, abatron_pteptrs@l
843 isync /* Force context change */
846 _GLOBAL(flush_dcache_L1)
849 rlwinm r5,r3,9,3 /* Extract cache block size */
850 twlgti r5,1 /* Only 32 and 64 byte cache blocks
851 * are currently defined.
854 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
855 * log2(number of ways)
857 slw r5,r4,r5 /* r5 = cache block size */
859 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
860 mulli r7,r7,13 /* An 8-way cache will require 13
865 /* save off HID0 and set DCFA */
867 ori r9,r8,HID0_DCFA@l
874 1: lwz r3,0(r4) /* Load... */
882 1: dcbf 0,r4 /* ...and flush. */
893 /* When we get here, r24 needs to hold the CPU # */
894 .globl __secondary_start
896 lis r3,__secondary_hold_acknowledge@h
897 ori r3,r3,__secondary_hold_acknowledge@l
904 lis r3,tlbcam_index@ha
905 lwz r3,tlbcam_index@l(r3)
907 li r26,0 /* r26 safe? */
909 /* Load each CAM entry */
915 /* get current_thread_info and current */
916 lis r1,secondary_ti@ha
917 lwz r1,secondary_ti@l(r1)
921 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
925 /* ptr to current thread */
926 addi r4,r2,THREAD /* address of our thread_struct */
927 mtspr SPRN_SPRG_THREAD,r4
929 /* Setup the defaults for TLB entries */
930 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
933 /* Jump to start_secondary */
935 ori r4,r4,MSR_KERNEL@l
936 lis r3,start_secondary@h
937 ori r3,r3,start_secondary@l
944 .globl __secondary_hold_acknowledge
945 __secondary_hold_acknowledge:
950 * We put a few things here that have to be page-aligned. This stuff
951 * goes at the beginning of the data segment, which is page-aligned.
957 .globl empty_zero_page
960 .globl swapper_pg_dir
962 .space PGD_TABLE_SIZE
965 * Room for two PTE pointers, usually the kernel and current user pointers
966 * to their respective root page table.