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Merge branch 'linux-4.12' of git://github.com/skeggsb/linux into drm-next
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / powerpc / kernel / exceptions-64s.S
1 /*
2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
6 *
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
9 *
10 * Most of this originates from head_64.S and thus has the same
11 * copyright history.
12 *
13 */
14
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
20
21 /*
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
27 * must be used.
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
29 * virtual 0xc00...
30 * - Conditional branch targets must be within +/-32K of caller.
31 *
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
37 *
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
44 *
45 * It's impossible to receive interrupts below 0x300 via AIL.
46 *
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
49 *
50 *
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
60 *
61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
63 * vectors there.
64 */
65 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
66 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
67 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
68 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
69 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
70 /*
71 * Data area reserved for FWNMI option.
72 * This address (0x7000) is fixed by the RPA.
73 * pseries and powernv need to keep the whole page from
74 * 0x7000 to 0x8000 free for use by the firmware
75 */
76 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
77 OPEN_TEXT_SECTION(0x8000)
78 #else
79 OPEN_TEXT_SECTION(0x7000)
80 #endif
81
82 USE_FIXED_SECTION(real_vectors)
83
84 /*
85 * This is the start of the interrupt handlers for pSeries
86 * This code runs with relocation off.
87 * Code from here to __end_interrupts gets copied down to real
88 * address 0x100 when we are running a relocatable kernel.
89 * Therefore any relative branches in this section must only
90 * branch to labels in this section.
91 */
92 .globl __start_interrupts
93 __start_interrupts:
94
95 /* No virt vectors corresponding with 0x0..0x100 */
96 EXC_VIRT_NONE(0x4000, 0x100)
97
98
99 #ifdef CONFIG_PPC_P7_NAP
100 /*
101 * If running native on arch 2.06 or later, check if we are waking up
102 * from nap/sleep/winkle, and branch to idle handler.
103 */
104 #define IDLETEST(n) \
105 BEGIN_FTR_SECTION ; \
106 mfspr r10,SPRN_SRR1 ; \
107 rlwinm. r10,r10,47-31,30,31 ; \
108 beq- 1f ; \
109 cmpwi cr3,r10,2 ; \
110 BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \
111 1: \
112 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
113 #else
114 #define IDLETEST NOTEST
115 #endif
116
117 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
118 SET_SCRATCH0(r13)
119 /*
120 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
121 * being used, so a nested NMI exception would corrupt it.
122 */
123 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
124 IDLETEST, 0x100)
125
126 EXC_REAL_END(system_reset, 0x100, 0x100)
127 EXC_VIRT_NONE(0x4100, 0x100)
128
129 #ifdef CONFIG_PPC_P7_NAP
130 EXC_COMMON_BEGIN(system_reset_idle_common)
131 b pnv_powersave_wakeup
132 #endif
133
134 EXC_COMMON_BEGIN(system_reset_common)
135 /*
136 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
137 * to recover, but nested NMI will notice in_nmi and not recover
138 * because of the use of the NMI stack. in_nmi reentrancy is tested in
139 * system_reset_exception.
140 */
141 lhz r10,PACA_IN_NMI(r13)
142 addi r10,r10,1
143 sth r10,PACA_IN_NMI(r13)
144 li r10,MSR_RI
145 mtmsrd r10,1
146
147 mr r10,r1
148 ld r1,PACA_NMI_EMERG_SP(r13)
149 subi r1,r1,INT_FRAME_SIZE
150 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
151 system_reset, system_reset_exception,
152 ADD_NVGPRS;ADD_RECONCILE)
153
154 /*
155 * The stack is no longer in use, decrement in_nmi.
156 */
157 lhz r10,PACA_IN_NMI(r13)
158 subi r10,r10,1
159 sth r10,PACA_IN_NMI(r13)
160
161 b ret_from_except
162
163 #ifdef CONFIG_PPC_PSERIES
164 /*
165 * Vectors for the FWNMI option. Share common code.
166 */
167 TRAMP_REAL_BEGIN(system_reset_fwnmi)
168 SET_SCRATCH0(r13) /* save r13 */
169 /* See comment at system_reset exception */
170 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
171 EXC_STD, NOTEST, 0x100)
172 #endif /* CONFIG_PPC_PSERIES */
173
174
175 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
176 /* This is moved out of line as it can be patched by FW, but
177 * some code path might still want to branch into the original
178 * vector
179 */
180 SET_SCRATCH0(r13) /* save r13 */
181 EXCEPTION_PROLOG_0(PACA_EXMC)
182 BEGIN_FTR_SECTION
183 b machine_check_powernv_early
184 FTR_SECTION_ELSE
185 b machine_check_pSeries_0
186 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
187 EXC_REAL_END(machine_check, 0x200, 0x100)
188 EXC_VIRT_NONE(0x4200, 0x100)
189 TRAMP_REAL_BEGIN(machine_check_powernv_early)
190 BEGIN_FTR_SECTION
191 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
192 /*
193 * Register contents:
194 * R13 = PACA
195 * R9 = CR
196 * Original R9 to R13 is saved on PACA_EXMC
197 *
198 * Switch to mc_emergency stack and handle re-entrancy (we limit
199 * the nested MCE upto level 4 to avoid stack overflow).
200 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
201 *
202 * We use paca->in_mce to check whether this is the first entry or
203 * nested machine check. We increment paca->in_mce to track nested
204 * machine checks.
205 *
206 * If this is the first entry then set stack pointer to
207 * paca->mc_emergency_sp, otherwise r1 is already pointing to
208 * stack frame on mc_emergency stack.
209 *
210 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
211 * checkstop if we get another machine check exception before we do
212 * rfid with MSR_ME=1.
213 *
214 * This interrupt can wake directly from idle. If that is the case,
215 * the machine check is handled then the idle wakeup code is called
216 * to restore state. In that case, the POWER9 DD1 idle PACA workaround
217 * is not applied in the early machine check code, which will cause
218 * bugs.
219 */
220 mr r11,r1 /* Save r1 */
221 lhz r10,PACA_IN_MCE(r13)
222 cmpwi r10,0 /* Are we in nested machine check */
223 bne 0f /* Yes, we are. */
224 /* First machine check entry */
225 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
226 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
227 addi r10,r10,1 /* increment paca->in_mce */
228 sth r10,PACA_IN_MCE(r13)
229 /* Limit nested MCE to level 4 to avoid stack overflow */
230 cmpwi r10,4
231 bgt 2f /* Check if we hit limit of 4 */
232 std r11,GPR1(r1) /* Save r1 on the stack. */
233 std r11,0(r1) /* make stack chain pointer */
234 mfspr r11,SPRN_SRR0 /* Save SRR0 */
235 std r11,_NIP(r1)
236 mfspr r11,SPRN_SRR1 /* Save SRR1 */
237 std r11,_MSR(r1)
238 mfspr r11,SPRN_DAR /* Save DAR */
239 std r11,_DAR(r1)
240 mfspr r11,SPRN_DSISR /* Save DSISR */
241 std r11,_DSISR(r1)
242 std r9,_CCR(r1) /* Save CR in stackframe */
243 /* Save r9 through r13 from EXMC save area to stack frame. */
244 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
245 mfmsr r11 /* get MSR value */
246 ori r11,r11,MSR_ME /* turn on ME bit */
247 ori r11,r11,MSR_RI /* turn on RI bit */
248 LOAD_HANDLER(r12, machine_check_handle_early)
249 1: mtspr SPRN_SRR0,r12
250 mtspr SPRN_SRR1,r11
251 rfid
252 b . /* prevent speculative execution */
253 2:
254 /* Stack overflow. Stay on emergency stack and panic.
255 * Keep the ME bit off while panic-ing, so that if we hit
256 * another machine check we checkstop.
257 */
258 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
259 ld r11,PACAKMSR(r13)
260 LOAD_HANDLER(r12, unrecover_mce)
261 li r10,MSR_ME
262 andc r11,r11,r10 /* Turn off MSR_ME */
263 b 1b
264 b . /* prevent speculative execution */
265 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
266
267 TRAMP_REAL_BEGIN(machine_check_pSeries)
268 .globl machine_check_fwnmi
269 machine_check_fwnmi:
270 SET_SCRATCH0(r13) /* save r13 */
271 EXCEPTION_PROLOG_0(PACA_EXMC)
272 machine_check_pSeries_0:
273 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
274 /*
275 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
276 * nested machine check corrupts it. machine_check_common enables
277 * MSR_RI.
278 */
279 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
280
281 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
282
283 EXC_COMMON_BEGIN(machine_check_common)
284 /*
285 * Machine check is different because we use a different
286 * save area: PACA_EXMC instead of PACA_EXGEN.
287 */
288 mfspr r10,SPRN_DAR
289 std r10,PACA_EXMC+EX_DAR(r13)
290 mfspr r10,SPRN_DSISR
291 stw r10,PACA_EXMC+EX_DSISR(r13)
292 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
293 FINISH_NAP
294 RECONCILE_IRQ_STATE(r10, r11)
295 ld r3,PACA_EXMC+EX_DAR(r13)
296 lwz r4,PACA_EXMC+EX_DSISR(r13)
297 /* Enable MSR_RI when finished with PACA_EXMC */
298 li r10,MSR_RI
299 mtmsrd r10,1
300 std r3,_DAR(r1)
301 std r4,_DSISR(r1)
302 bl save_nvgprs
303 addi r3,r1,STACK_FRAME_OVERHEAD
304 bl machine_check_exception
305 b ret_from_except
306
307 #define MACHINE_CHECK_HANDLER_WINDUP \
308 /* Clear MSR_RI before setting SRR0 and SRR1. */\
309 li r0,MSR_RI; \
310 mfmsr r9; /* get MSR value */ \
311 andc r9,r9,r0; \
312 mtmsrd r9,1; /* Clear MSR_RI */ \
313 /* Move original SRR0 and SRR1 into the respective regs */ \
314 ld r9,_MSR(r1); \
315 mtspr SPRN_SRR1,r9; \
316 ld r3,_NIP(r1); \
317 mtspr SPRN_SRR0,r3; \
318 ld r9,_CTR(r1); \
319 mtctr r9; \
320 ld r9,_XER(r1); \
321 mtxer r9; \
322 ld r9,_LINK(r1); \
323 mtlr r9; \
324 REST_GPR(0, r1); \
325 REST_8GPRS(2, r1); \
326 REST_GPR(10, r1); \
327 ld r11,_CCR(r1); \
328 mtcr r11; \
329 /* Decrement paca->in_mce. */ \
330 lhz r12,PACA_IN_MCE(r13); \
331 subi r12,r12,1; \
332 sth r12,PACA_IN_MCE(r13); \
333 REST_GPR(11, r1); \
334 REST_2GPRS(12, r1); \
335 /* restore original r1. */ \
336 ld r1,GPR1(r1)
337
338 #ifdef CONFIG_PPC_P7_NAP
339 /*
340 * This is an idle wakeup. Low level machine check has already been
341 * done. Queue the event then call the idle code to do the wake up.
342 */
343 EXC_COMMON_BEGIN(machine_check_idle_common)
344 bl machine_check_queue_event
345
346 /*
347 * We have not used any non-volatile GPRs here, and as a rule
348 * most exception code including machine check does not.
349 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
350 * wakeup will restore volatile registers.
351 *
352 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
353 *
354 * Then decrement MCE nesting after finishing with the stack.
355 */
356 ld r3,_MSR(r1)
357
358 lhz r11,PACA_IN_MCE(r13)
359 subi r11,r11,1
360 sth r11,PACA_IN_MCE(r13)
361
362 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
363 /* Recoverability could be improved by reducing the use of SRR1. */
364 li r11,0
365 mtmsrd r11,1
366
367 b pnv_powersave_wakeup_mce
368 #endif
369 /*
370 * Handle machine check early in real mode. We come here with
371 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
372 */
373 EXC_COMMON_BEGIN(machine_check_handle_early)
374 std r0,GPR0(r1) /* Save r0 */
375 EXCEPTION_PROLOG_COMMON_3(0x200)
376 bl save_nvgprs
377 addi r3,r1,STACK_FRAME_OVERHEAD
378 bl machine_check_early
379 std r3,RESULT(r1) /* Save result */
380 ld r12,_MSR(r1)
381
382 #ifdef CONFIG_PPC_P7_NAP
383 /*
384 * Check if thread was in power saving mode. We come here when any
385 * of the following is true:
386 * a. thread wasn't in power saving mode
387 * b. thread was in power saving mode with no state loss,
388 * supervisor state loss or hypervisor state loss.
389 *
390 * Go back to nap/sleep/winkle mode again if (b) is true.
391 */
392 BEGIN_FTR_SECTION
393 rlwinm. r11,r12,47-31,30,31
394 beq- 4f
395 BRANCH_TO_COMMON(r10, machine_check_idle_common)
396 4:
397 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
398 #endif
399
400 /*
401 * Check if we are coming from hypervisor userspace. If yes then we
402 * continue in host kernel in V mode to deliver the MC event.
403 */
404 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
405 beq 5f
406 andi. r11,r12,MSR_PR /* See if coming from user. */
407 bne 9f /* continue in V mode if we are. */
408
409 5:
410 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
411 /*
412 * We are coming from kernel context. Check if we are coming from
413 * guest. if yes, then we can continue. We will fall through
414 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
415 */
416 lbz r11,HSTATE_IN_GUEST(r13)
417 cmpwi r11,0 /* Check if coming from guest */
418 bne 9f /* continue if we are. */
419 #endif
420 /*
421 * At this point we are not sure about what context we come from.
422 * Queue up the MCE event and return from the interrupt.
423 * But before that, check if this is an un-recoverable exception.
424 * If yes, then stay on emergency stack and panic.
425 */
426 andi. r11,r12,MSR_RI
427 bne 2f
428 1: mfspr r11,SPRN_SRR0
429 LOAD_HANDLER(r10,unrecover_mce)
430 mtspr SPRN_SRR0,r10
431 ld r10,PACAKMSR(r13)
432 /*
433 * We are going down. But there are chances that we might get hit by
434 * another MCE during panic path and we may run into unstable state
435 * with no way out. Hence, turn ME bit off while going down, so that
436 * when another MCE is hit during panic path, system will checkstop
437 * and hypervisor will get restarted cleanly by SP.
438 */
439 li r3,MSR_ME
440 andc r10,r10,r3 /* Turn off MSR_ME */
441 mtspr SPRN_SRR1,r10
442 rfid
443 b .
444 2:
445 /*
446 * Check if we have successfully handled/recovered from error, if not
447 * then stay on emergency stack and panic.
448 */
449 ld r3,RESULT(r1) /* Load result */
450 cmpdi r3,0 /* see if we handled MCE successfully */
451
452 beq 1b /* if !handled then panic */
453 /*
454 * Return from MC interrupt.
455 * Queue up the MCE event so that we can log it later, while
456 * returning from kernel or opal call.
457 */
458 bl machine_check_queue_event
459 MACHINE_CHECK_HANDLER_WINDUP
460 rfid
461 9:
462 /* Deliver the machine check to host kernel in V mode. */
463 MACHINE_CHECK_HANDLER_WINDUP
464 b machine_check_pSeries
465
466 EXC_COMMON_BEGIN(unrecover_mce)
467 /* Invoke machine_check_exception to print MCE event and panic. */
468 addi r3,r1,STACK_FRAME_OVERHEAD
469 bl machine_check_exception
470 /*
471 * We will not reach here. Even if we did, there is no way out. Call
472 * unrecoverable_exception and die.
473 */
474 1: addi r3,r1,STACK_FRAME_OVERHEAD
475 bl unrecoverable_exception
476 b 1b
477
478
479 EXC_REAL(data_access, 0x300, 0x80)
480 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
481 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
482
483 EXC_COMMON_BEGIN(data_access_common)
484 /*
485 * Here r13 points to the paca, r9 contains the saved CR,
486 * SRR0 and SRR1 are saved in r11 and r12,
487 * r9 - r13 are saved in paca->exgen.
488 */
489 mfspr r10,SPRN_DAR
490 std r10,PACA_EXGEN+EX_DAR(r13)
491 mfspr r10,SPRN_DSISR
492 stw r10,PACA_EXGEN+EX_DSISR(r13)
493 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
494 RECONCILE_IRQ_STATE(r10, r11)
495 ld r12,_MSR(r1)
496 ld r3,PACA_EXGEN+EX_DAR(r13)
497 lwz r4,PACA_EXGEN+EX_DSISR(r13)
498 li r5,0x300
499 std r3,_DAR(r1)
500 std r4,_DSISR(r1)
501 BEGIN_MMU_FTR_SECTION
502 b do_hash_page /* Try to handle as hpte fault */
503 MMU_FTR_SECTION_ELSE
504 b handle_page_fault
505 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
506
507
508 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
509 SET_SCRATCH0(r13)
510 EXCEPTION_PROLOG_0(PACA_EXSLB)
511 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
512 std r3,PACA_EXSLB+EX_R3(r13)
513 mfspr r3,SPRN_DAR
514 mfspr r12,SPRN_SRR1
515 crset 4*cr6+eq
516 #ifndef CONFIG_RELOCATABLE
517 b slb_miss_realmode
518 #else
519 /*
520 * We can't just use a direct branch to slb_miss_realmode
521 * because the distance from here to there depends on where
522 * the kernel ends up being put.
523 */
524 mfctr r11
525 LOAD_HANDLER(r10, slb_miss_realmode)
526 mtctr r10
527 bctr
528 #endif
529 EXC_REAL_END(data_access_slb, 0x380, 0x80)
530
531 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
532 SET_SCRATCH0(r13)
533 EXCEPTION_PROLOG_0(PACA_EXSLB)
534 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
535 std r3,PACA_EXSLB+EX_R3(r13)
536 mfspr r3,SPRN_DAR
537 mfspr r12,SPRN_SRR1
538 crset 4*cr6+eq
539 #ifndef CONFIG_RELOCATABLE
540 b slb_miss_realmode
541 #else
542 /*
543 * We can't just use a direct branch to slb_miss_realmode
544 * because the distance from here to there depends on where
545 * the kernel ends up being put.
546 */
547 mfctr r11
548 LOAD_HANDLER(r10, slb_miss_realmode)
549 mtctr r10
550 bctr
551 #endif
552 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
553 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
554
555
556 EXC_REAL(instruction_access, 0x400, 0x80)
557 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
558 TRAMP_KVM(PACA_EXGEN, 0x400)
559
560 EXC_COMMON_BEGIN(instruction_access_common)
561 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
562 RECONCILE_IRQ_STATE(r10, r11)
563 ld r12,_MSR(r1)
564 ld r3,_NIP(r1)
565 andis. r4,r12,0x5820
566 li r5,0x400
567 std r3,_DAR(r1)
568 std r4,_DSISR(r1)
569 BEGIN_MMU_FTR_SECTION
570 b do_hash_page /* Try to handle as hpte fault */
571 MMU_FTR_SECTION_ELSE
572 b handle_page_fault
573 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
574
575
576 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
577 SET_SCRATCH0(r13)
578 EXCEPTION_PROLOG_0(PACA_EXSLB)
579 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
580 std r3,PACA_EXSLB+EX_R3(r13)
581 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
582 mfspr r12,SPRN_SRR1
583 crclr 4*cr6+eq
584 #ifndef CONFIG_RELOCATABLE
585 b slb_miss_realmode
586 #else
587 mfctr r11
588 LOAD_HANDLER(r10, slb_miss_realmode)
589 mtctr r10
590 bctr
591 #endif
592 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
593
594 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
595 SET_SCRATCH0(r13)
596 EXCEPTION_PROLOG_0(PACA_EXSLB)
597 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
598 std r3,PACA_EXSLB+EX_R3(r13)
599 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
600 mfspr r12,SPRN_SRR1
601 crclr 4*cr6+eq
602 #ifndef CONFIG_RELOCATABLE
603 b slb_miss_realmode
604 #else
605 mfctr r11
606 LOAD_HANDLER(r10, slb_miss_realmode)
607 mtctr r10
608 bctr
609 #endif
610 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
611 TRAMP_KVM(PACA_EXSLB, 0x480)
612
613
614 /* This handler is used by both 0x380 and 0x480 slb miss interrupts */
615 EXC_COMMON_BEGIN(slb_miss_realmode)
616 /*
617 * r13 points to the PACA, r9 contains the saved CR,
618 * r12 contain the saved SRR1, SRR0 is still ready for return
619 * r3 has the faulting address
620 * r9 - r13 are saved in paca->exslb.
621 * r3 is saved in paca->slb_r3
622 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
623 * We assume we aren't going to take any exceptions during this
624 * procedure.
625 */
626 mflr r10
627 #ifdef CONFIG_RELOCATABLE
628 mtctr r11
629 #endif
630
631 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
632 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
633 std r3,PACA_EXSLB+EX_DAR(r13)
634
635 crset 4*cr0+eq
636 #ifdef CONFIG_PPC_STD_MMU_64
637 BEGIN_MMU_FTR_SECTION
638 bl slb_allocate_realmode
639 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
640 #endif
641
642 ld r10,PACA_EXSLB+EX_LR(r13)
643 ld r3,PACA_EXSLB+EX_R3(r13)
644 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
645 mtlr r10
646
647 beq 8f /* if bad address, make full stack frame */
648
649 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
650 beq- 2f
651
652 /* All done -- return from exception. */
653
654 .machine push
655 .machine "power4"
656 mtcrf 0x80,r9
657 mtcrf 0x02,r9 /* I/D indication is in cr6 */
658 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
659 .machine pop
660
661 RESTORE_PPR_PACA(PACA_EXSLB, r9)
662 ld r9,PACA_EXSLB+EX_R9(r13)
663 ld r10,PACA_EXSLB+EX_R10(r13)
664 ld r11,PACA_EXSLB+EX_R11(r13)
665 ld r12,PACA_EXSLB+EX_R12(r13)
666 ld r13,PACA_EXSLB+EX_R13(r13)
667 rfid
668 b . /* prevent speculative execution */
669
670 2: mfspr r11,SPRN_SRR0
671 LOAD_HANDLER(r10,unrecov_slb)
672 mtspr SPRN_SRR0,r10
673 ld r10,PACAKMSR(r13)
674 mtspr SPRN_SRR1,r10
675 rfid
676 b .
677
678 8: mfspr r11,SPRN_SRR0
679 LOAD_HANDLER(r10,bad_addr_slb)
680 mtspr SPRN_SRR0,r10
681 ld r10,PACAKMSR(r13)
682 mtspr SPRN_SRR1,r10
683 rfid
684 b .
685
686 EXC_COMMON_BEGIN(unrecov_slb)
687 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
688 RECONCILE_IRQ_STATE(r10, r11)
689 bl save_nvgprs
690 1: addi r3,r1,STACK_FRAME_OVERHEAD
691 bl unrecoverable_exception
692 b 1b
693
694 EXC_COMMON_BEGIN(bad_addr_slb)
695 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
696 RECONCILE_IRQ_STATE(r10, r11)
697 ld r3, PACA_EXSLB+EX_DAR(r13)
698 std r3, _DAR(r1)
699 beq cr6, 2f
700 li r10, 0x480 /* fix trap number for I-SLB miss */
701 std r10, _TRAP(r1)
702 2: bl save_nvgprs
703 addi r3, r1, STACK_FRAME_OVERHEAD
704 bl slb_miss_bad_addr
705 b ret_from_except
706
707 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
708 .globl hardware_interrupt_hv;
709 hardware_interrupt_hv:
710 BEGIN_FTR_SECTION
711 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
712 EXC_HV, SOFTEN_TEST_HV)
713 FTR_SECTION_ELSE
714 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
715 EXC_STD, SOFTEN_TEST_PR)
716 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
717 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
718
719 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
720 .globl hardware_interrupt_relon_hv;
721 hardware_interrupt_relon_hv:
722 BEGIN_FTR_SECTION
723 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
724 FTR_SECTION_ELSE
725 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
726 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
727 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
728
729 TRAMP_KVM(PACA_EXGEN, 0x500)
730 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
731 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
732
733
734 EXC_REAL(alignment, 0x600, 0x100)
735 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
736 TRAMP_KVM(PACA_EXGEN, 0x600)
737 EXC_COMMON_BEGIN(alignment_common)
738 mfspr r10,SPRN_DAR
739 std r10,PACA_EXGEN+EX_DAR(r13)
740 mfspr r10,SPRN_DSISR
741 stw r10,PACA_EXGEN+EX_DSISR(r13)
742 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
743 ld r3,PACA_EXGEN+EX_DAR(r13)
744 lwz r4,PACA_EXGEN+EX_DSISR(r13)
745 std r3,_DAR(r1)
746 std r4,_DSISR(r1)
747 bl save_nvgprs
748 RECONCILE_IRQ_STATE(r10, r11)
749 addi r3,r1,STACK_FRAME_OVERHEAD
750 bl alignment_exception
751 b ret_from_except
752
753
754 EXC_REAL(program_check, 0x700, 0x100)
755 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
756 TRAMP_KVM(PACA_EXGEN, 0x700)
757 EXC_COMMON_BEGIN(program_check_common)
758 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
759 bl save_nvgprs
760 RECONCILE_IRQ_STATE(r10, r11)
761 addi r3,r1,STACK_FRAME_OVERHEAD
762 bl program_check_exception
763 b ret_from_except
764
765
766 EXC_REAL(fp_unavailable, 0x800, 0x100)
767 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
768 TRAMP_KVM(PACA_EXGEN, 0x800)
769 EXC_COMMON_BEGIN(fp_unavailable_common)
770 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
771 bne 1f /* if from user, just load it up */
772 bl save_nvgprs
773 RECONCILE_IRQ_STATE(r10, r11)
774 addi r3,r1,STACK_FRAME_OVERHEAD
775 bl kernel_fp_unavailable_exception
776 BUG_OPCODE
777 1:
778 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
779 BEGIN_FTR_SECTION
780 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
781 * transaction), go do TM stuff
782 */
783 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
784 bne- 2f
785 END_FTR_SECTION_IFSET(CPU_FTR_TM)
786 #endif
787 bl load_up_fpu
788 b fast_exception_return
789 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
790 2: /* User process was in a transaction */
791 bl save_nvgprs
792 RECONCILE_IRQ_STATE(r10, r11)
793 addi r3,r1,STACK_FRAME_OVERHEAD
794 bl fp_unavailable_tm
795 b ret_from_except
796 #endif
797
798
799 EXC_REAL_MASKABLE(decrementer, 0x900, 0x80)
800 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900)
801 TRAMP_KVM(PACA_EXGEN, 0x900)
802 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
803
804
805 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
806 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
807 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
808 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
809
810
811 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100)
812 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00)
813 TRAMP_KVM(PACA_EXGEN, 0xa00)
814 #ifdef CONFIG_PPC_DOORBELL
815 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
816 #else
817 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
818 #endif
819
820
821 EXC_REAL(trap_0b, 0xb00, 0x100)
822 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
823 TRAMP_KVM(PACA_EXGEN, 0xb00)
824 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
825
826 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
827 /*
828 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems
829 * that support it) before changing to HMT_MEDIUM. That allows the KVM
830 * code to save that value into the guest state (it is the guest's PPR
831 * value). Otherwise just change to HMT_MEDIUM as userspace has
832 * already saved the PPR.
833 */
834 #define SYSCALL_KVMTEST \
835 SET_SCRATCH0(r13); \
836 GET_PACA(r13); \
837 std r9,PACA_EXGEN+EX_R9(r13); \
838 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
839 HMT_MEDIUM; \
840 std r10,PACA_EXGEN+EX_R10(r13); \
841 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); \
842 mfcr r9; \
843 KVMTEST_PR(0xc00); \
844 GET_SCRATCH0(r13)
845
846 #else
847 #define SYSCALL_KVMTEST \
848 HMT_MEDIUM
849 #endif
850
851 #define LOAD_SYSCALL_HANDLER(reg) \
852 __LOAD_HANDLER(reg, system_call_common)
853
854 /* Syscall routine is used twice, in reloc-off and reloc-on paths */
855 #define SYSCALL_PSERIES_1 \
856 BEGIN_FTR_SECTION \
857 cmpdi r0,0x1ebe ; \
858 beq- 1f ; \
859 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
860 mr r9,r13 ; \
861 GET_PACA(r13) ; \
862 mfspr r11,SPRN_SRR0 ; \
863 0:
864
865 #define SYSCALL_PSERIES_2_RFID \
866 mfspr r12,SPRN_SRR1 ; \
867 LOAD_SYSCALL_HANDLER(r10) ; \
868 mtspr SPRN_SRR0,r10 ; \
869 ld r10,PACAKMSR(r13) ; \
870 mtspr SPRN_SRR1,r10 ; \
871 rfid ; \
872 b . ; /* prevent speculative execution */
873
874 #define SYSCALL_PSERIES_3 \
875 /* Fast LE/BE switch system call */ \
876 1: mfspr r12,SPRN_SRR1 ; \
877 xori r12,r12,MSR_LE ; \
878 mtspr SPRN_SRR1,r12 ; \
879 rfid ; /* return to userspace */ \
880 b . ; /* prevent speculative execution */
881
882 #if defined(CONFIG_RELOCATABLE)
883 /*
884 * We can't branch directly so we do it via the CTR which
885 * is volatile across system calls.
886 */
887 #define SYSCALL_PSERIES_2_DIRECT \
888 LOAD_SYSCALL_HANDLER(r12) ; \
889 mtctr r12 ; \
890 mfspr r12,SPRN_SRR1 ; \
891 li r10,MSR_RI ; \
892 mtmsrd r10,1 ; \
893 bctr ;
894 #else
895 /* We can branch directly */
896 #define SYSCALL_PSERIES_2_DIRECT \
897 mfspr r12,SPRN_SRR1 ; \
898 li r10,MSR_RI ; \
899 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
900 b system_call_common ;
901 #endif
902
903 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
904 SYSCALL_KVMTEST
905 SYSCALL_PSERIES_1
906 SYSCALL_PSERIES_2_RFID
907 SYSCALL_PSERIES_3
908 EXC_REAL_END(system_call, 0xc00, 0x100)
909
910 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
911 SYSCALL_KVMTEST
912 SYSCALL_PSERIES_1
913 SYSCALL_PSERIES_2_DIRECT
914 SYSCALL_PSERIES_3
915 EXC_VIRT_END(system_call, 0x4c00, 0x100)
916
917 TRAMP_KVM(PACA_EXGEN, 0xc00)
918
919
920 EXC_REAL(single_step, 0xd00, 0x100)
921 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
922 TRAMP_KVM(PACA_EXGEN, 0xd00)
923 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
924
925 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
926 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
927 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
928 EXC_COMMON_BEGIN(h_data_storage_common)
929 mfspr r10,SPRN_HDAR
930 std r10,PACA_EXGEN+EX_DAR(r13)
931 mfspr r10,SPRN_HDSISR
932 stw r10,PACA_EXGEN+EX_DSISR(r13)
933 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
934 bl save_nvgprs
935 RECONCILE_IRQ_STATE(r10, r11)
936 addi r3,r1,STACK_FRAME_OVERHEAD
937 bl unknown_exception
938 b ret_from_except
939
940
941 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
942 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
943 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
944 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
945
946
947 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
948 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
949 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
950 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
951
952
953 /*
954 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
955 * first, and then eventaully from there to the trampoline to get into virtual
956 * mode.
957 */
958 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
959 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
960 EXC_VIRT_NONE(0x4e60, 0x20)
961 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
962 TRAMP_REAL_BEGIN(hmi_exception_early)
963 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
964 mr r10,r1 /* Save r1 */
965 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
966 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
967 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
968 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
969 EXCEPTION_PROLOG_COMMON_1()
970 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
971 EXCEPTION_PROLOG_COMMON_3(0xe60)
972 addi r3,r1,STACK_FRAME_OVERHEAD
973 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
974 /* Windup the stack. */
975 /* Move original HSRR0 and HSRR1 into the respective regs */
976 ld r9,_MSR(r1)
977 mtspr SPRN_HSRR1,r9
978 ld r3,_NIP(r1)
979 mtspr SPRN_HSRR0,r3
980 ld r9,_CTR(r1)
981 mtctr r9
982 ld r9,_XER(r1)
983 mtxer r9
984 ld r9,_LINK(r1)
985 mtlr r9
986 REST_GPR(0, r1)
987 REST_8GPRS(2, r1)
988 REST_GPR(10, r1)
989 ld r11,_CCR(r1)
990 mtcr r11
991 REST_GPR(11, r1)
992 REST_2GPRS(12, r1)
993 /* restore original r1. */
994 ld r1,GPR1(r1)
995
996 /*
997 * Go to virtual mode and pull the HMI event information from
998 * firmware.
999 */
1000 .globl hmi_exception_after_realmode
1001 hmi_exception_after_realmode:
1002 SET_SCRATCH0(r13)
1003 EXCEPTION_PROLOG_0(PACA_EXGEN)
1004 b tramp_real_hmi_exception
1005
1006 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1007
1008
1009 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20)
1010 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80)
1011 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1012 #ifdef CONFIG_PPC_DOORBELL
1013 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1014 #else
1015 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1016 #endif
1017
1018
1019 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20)
1020 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0)
1021 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1022 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1023
1024
1025 EXC_REAL_NONE(0xec0, 0x20)
1026 EXC_VIRT_NONE(0x4ec0, 0x20)
1027 EXC_REAL_NONE(0xee0, 0x20)
1028 EXC_VIRT_NONE(0x4ee0, 0x20)
1029
1030
1031 EXC_REAL_OOL(performance_monitor, 0xf00, 0x20)
1032 EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00)
1033 TRAMP_KVM(PACA_EXGEN, 0xf00)
1034 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1035
1036
1037 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1038 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1039 TRAMP_KVM(PACA_EXGEN, 0xf20)
1040 EXC_COMMON_BEGIN(altivec_unavailable_common)
1041 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1042 #ifdef CONFIG_ALTIVEC
1043 BEGIN_FTR_SECTION
1044 beq 1f
1045 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1046 BEGIN_FTR_SECTION_NESTED(69)
1047 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1048 * transaction), go do TM stuff
1049 */
1050 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1051 bne- 2f
1052 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1053 #endif
1054 bl load_up_altivec
1055 b fast_exception_return
1056 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1057 2: /* User process was in a transaction */
1058 bl save_nvgprs
1059 RECONCILE_IRQ_STATE(r10, r11)
1060 addi r3,r1,STACK_FRAME_OVERHEAD
1061 bl altivec_unavailable_tm
1062 b ret_from_except
1063 #endif
1064 1:
1065 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1066 #endif
1067 bl save_nvgprs
1068 RECONCILE_IRQ_STATE(r10, r11)
1069 addi r3,r1,STACK_FRAME_OVERHEAD
1070 bl altivec_unavailable_exception
1071 b ret_from_except
1072
1073
1074 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1075 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1076 TRAMP_KVM(PACA_EXGEN, 0xf40)
1077 EXC_COMMON_BEGIN(vsx_unavailable_common)
1078 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1079 #ifdef CONFIG_VSX
1080 BEGIN_FTR_SECTION
1081 beq 1f
1082 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1083 BEGIN_FTR_SECTION_NESTED(69)
1084 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1085 * transaction), go do TM stuff
1086 */
1087 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1088 bne- 2f
1089 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1090 #endif
1091 b load_up_vsx
1092 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1093 2: /* User process was in a transaction */
1094 bl save_nvgprs
1095 RECONCILE_IRQ_STATE(r10, r11)
1096 addi r3,r1,STACK_FRAME_OVERHEAD
1097 bl vsx_unavailable_tm
1098 b ret_from_except
1099 #endif
1100 1:
1101 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1102 #endif
1103 bl save_nvgprs
1104 RECONCILE_IRQ_STATE(r10, r11)
1105 addi r3,r1,STACK_FRAME_OVERHEAD
1106 bl vsx_unavailable_exception
1107 b ret_from_except
1108
1109
1110 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1111 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1112 TRAMP_KVM(PACA_EXGEN, 0xf60)
1113 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1114
1115
1116 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1117 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1118 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1119 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1120
1121
1122 EXC_REAL_NONE(0xfa0, 0x20)
1123 EXC_VIRT_NONE(0x4fa0, 0x20)
1124 EXC_REAL_NONE(0xfc0, 0x20)
1125 EXC_VIRT_NONE(0x4fc0, 0x20)
1126 EXC_REAL_NONE(0xfe0, 0x20)
1127 EXC_VIRT_NONE(0x4fe0, 0x20)
1128
1129 EXC_REAL_NONE(0x1000, 0x100)
1130 EXC_VIRT_NONE(0x5000, 0x100)
1131 EXC_REAL_NONE(0x1100, 0x100)
1132 EXC_VIRT_NONE(0x5100, 0x100)
1133
1134 #ifdef CONFIG_CBE_RAS
1135 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1136 EXC_VIRT_NONE(0x5200, 0x100)
1137 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1138 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1139 #else /* CONFIG_CBE_RAS */
1140 EXC_REAL_NONE(0x1200, 0x100)
1141 EXC_VIRT_NONE(0x5200, 0x100)
1142 #endif
1143
1144
1145 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1146 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1147 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1148 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1149
1150 EXC_REAL_NONE(0x1400, 0x100)
1151 EXC_VIRT_NONE(0x5400, 0x100)
1152
1153 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1154 mtspr SPRN_SPRG_HSCRATCH0,r13
1155 EXCEPTION_PROLOG_0(PACA_EXGEN)
1156 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1157
1158 #ifdef CONFIG_PPC_DENORMALISATION
1159 mfspr r10,SPRN_HSRR1
1160 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1161 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1162 addi r11,r11,-4 /* HSRR0 is next instruction */
1163 bne+ denorm_assist
1164 #endif
1165
1166 KVMTEST_PR(0x1500)
1167 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1168 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1169
1170 #ifdef CONFIG_PPC_DENORMALISATION
1171 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1172 b exc_real_0x1500_denorm_exception_hv
1173 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1174 #else
1175 EXC_VIRT_NONE(0x5500, 0x100)
1176 #endif
1177
1178 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1179
1180 #ifdef CONFIG_PPC_DENORMALISATION
1181 TRAMP_REAL_BEGIN(denorm_assist)
1182 BEGIN_FTR_SECTION
1183 /*
1184 * To denormalise we need to move a copy of the register to itself.
1185 * For POWER6 do that here for all FP regs.
1186 */
1187 mfmsr r10
1188 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1189 xori r10,r10,(MSR_FE0|MSR_FE1)
1190 mtmsrd r10
1191 sync
1192
1193 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1194 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1195 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1196 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1197 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1198 FMR32(0)
1199
1200 FTR_SECTION_ELSE
1201 /*
1202 * To denormalise we need to move a copy of the register to itself.
1203 * For POWER7 do that here for the first 32 VSX registers only.
1204 */
1205 mfmsr r10
1206 oris r10,r10,MSR_VSX@h
1207 mtmsrd r10
1208 sync
1209
1210 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1211 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1212 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1213 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1214 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1215 XVCPSGNDP32(0)
1216
1217 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1218
1219 BEGIN_FTR_SECTION
1220 b denorm_done
1221 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1222 /*
1223 * To denormalise we need to move a copy of the register to itself.
1224 * For POWER8 we need to do that for all 64 VSX registers
1225 */
1226 XVCPSGNDP32(32)
1227 denorm_done:
1228 mtspr SPRN_HSRR0,r11
1229 mtcrf 0x80,r9
1230 ld r9,PACA_EXGEN+EX_R9(r13)
1231 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1232 BEGIN_FTR_SECTION
1233 ld r10,PACA_EXGEN+EX_CFAR(r13)
1234 mtspr SPRN_CFAR,r10
1235 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1236 ld r10,PACA_EXGEN+EX_R10(r13)
1237 ld r11,PACA_EXGEN+EX_R11(r13)
1238 ld r12,PACA_EXGEN+EX_R12(r13)
1239 ld r13,PACA_EXGEN+EX_R13(r13)
1240 HRFID
1241 b .
1242 #endif
1243
1244 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1245
1246
1247 #ifdef CONFIG_CBE_RAS
1248 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1249 EXC_VIRT_NONE(0x5600, 0x100)
1250 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1251 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1252 #else /* CONFIG_CBE_RAS */
1253 EXC_REAL_NONE(0x1600, 0x100)
1254 EXC_VIRT_NONE(0x5600, 0x100)
1255 #endif
1256
1257
1258 EXC_REAL(altivec_assist, 0x1700, 0x100)
1259 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1260 TRAMP_KVM(PACA_EXGEN, 0x1700)
1261 #ifdef CONFIG_ALTIVEC
1262 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1263 #else
1264 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1265 #endif
1266
1267
1268 #ifdef CONFIG_CBE_RAS
1269 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1270 EXC_VIRT_NONE(0x5800, 0x100)
1271 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1272 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1273 #else /* CONFIG_CBE_RAS */
1274 EXC_REAL_NONE(0x1800, 0x100)
1275 EXC_VIRT_NONE(0x5800, 0x100)
1276 #endif
1277
1278
1279 /*
1280 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1281 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1282 * - If it was a doorbell we return immediately since doorbells are edge
1283 * triggered and won't automatically refire.
1284 * - If it was a HMI we return immediately since we handled it in realmode
1285 * and it won't refire.
1286 * - else we hard disable and return.
1287 * This is called with r10 containing the value to OR to the paca field.
1288 */
1289 #define MASKED_INTERRUPT(_H) \
1290 masked_##_H##interrupt: \
1291 std r11,PACA_EXGEN+EX_R11(r13); \
1292 lbz r11,PACAIRQHAPPENED(r13); \
1293 or r11,r11,r10; \
1294 stb r11,PACAIRQHAPPENED(r13); \
1295 cmpwi r10,PACA_IRQ_DEC; \
1296 bne 1f; \
1297 lis r10,0x7fff; \
1298 ori r10,r10,0xffff; \
1299 mtspr SPRN_DEC,r10; \
1300 b 2f; \
1301 1: cmpwi r10,PACA_IRQ_DBELL; \
1302 beq 2f; \
1303 cmpwi r10,PACA_IRQ_HMI; \
1304 beq 2f; \
1305 mfspr r10,SPRN_##_H##SRR1; \
1306 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1307 rotldi r10,r10,16; \
1308 mtspr SPRN_##_H##SRR1,r10; \
1309 2: mtcrf 0x80,r9; \
1310 ld r9,PACA_EXGEN+EX_R9(r13); \
1311 ld r10,PACA_EXGEN+EX_R10(r13); \
1312 ld r11,PACA_EXGEN+EX_R11(r13); \
1313 GET_SCRATCH0(r13); \
1314 ##_H##rfid; \
1315 b .
1316
1317 /*
1318 * Real mode exceptions actually use this too, but alternate
1319 * instruction code patches (which end up in the common .text area)
1320 * cannot reach these if they are put there.
1321 */
1322 USE_FIXED_SECTION(virt_trampolines)
1323 MASKED_INTERRUPT()
1324 MASKED_INTERRUPT(H)
1325
1326 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1327 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1328 /*
1329 * Here all GPRs are unchanged from when the interrupt happened
1330 * except for r13, which is saved in SPRG_SCRATCH0.
1331 */
1332 mfspr r13, SPRN_SRR0
1333 addi r13, r13, 4
1334 mtspr SPRN_SRR0, r13
1335 GET_SCRATCH0(r13)
1336 rfid
1337 b .
1338
1339 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1340 /*
1341 * Here all GPRs are unchanged from when the interrupt happened
1342 * except for r13, which is saved in SPRG_SCRATCH0.
1343 */
1344 mfspr r13, SPRN_HSRR0
1345 addi r13, r13, 4
1346 mtspr SPRN_HSRR0, r13
1347 GET_SCRATCH0(r13)
1348 hrfid
1349 b .
1350 #endif
1351
1352 /*
1353 * Ensure that any handlers that get invoked from the exception prologs
1354 * above are below the first 64KB (0x10000) of the kernel image because
1355 * the prologs assemble the addresses of these handlers using the
1356 * LOAD_HANDLER macro, which uses an ori instruction.
1357 */
1358
1359 /*** Common interrupt handlers ***/
1360
1361
1362 /*
1363 * Relocation-on interrupts: A subset of the interrupts can be delivered
1364 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1365 * it. Addresses are the same as the original interrupt addresses, but
1366 * offset by 0xc000000000004000.
1367 * It's impossible to receive interrupts below 0x300 via this mechanism.
1368 * KVM: None of these traps are from the guest ; anything that escalated
1369 * to HV=1 from HV=0 is delivered via real mode handlers.
1370 */
1371
1372 /*
1373 * This uses the standard macro, since the original 0x300 vector
1374 * only has extra guff for STAB-based processors -- which never
1375 * come here.
1376 */
1377
1378 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1379 b __ppc64_runlatch_on
1380
1381 USE_FIXED_SECTION(virt_trampolines)
1382 /*
1383 * The __end_interrupts marker must be past the out-of-line (OOL)
1384 * handlers, so that they are copied to real address 0x100 when running
1385 * a relocatable kernel. This ensures they can be reached from the short
1386 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1387 * directly, without using LOAD_HANDLER().
1388 */
1389 .align 7
1390 .globl __end_interrupts
1391 __end_interrupts:
1392 DEFINE_FIXED_SYMBOL(__end_interrupts)
1393
1394 #ifdef CONFIG_PPC_970_NAP
1395 EXC_COMMON_BEGIN(power4_fixup_nap)
1396 andc r9,r9,r10
1397 std r9,TI_LOCAL_FLAGS(r11)
1398 ld r10,_LINK(r1) /* make idle task do the */
1399 std r10,_NIP(r1) /* equivalent of a blr */
1400 blr
1401 #endif
1402
1403 CLOSE_FIXED_SECTION(real_vectors);
1404 CLOSE_FIXED_SECTION(real_trampolines);
1405 CLOSE_FIXED_SECTION(virt_vectors);
1406 CLOSE_FIXED_SECTION(virt_trampolines);
1407
1408 USE_TEXT_SECTION()
1409
1410 /*
1411 * Hash table stuff
1412 */
1413 .balign IFETCH_ALIGN_BYTES
1414 do_hash_page:
1415 #ifdef CONFIG_PPC_STD_MMU_64
1416 andis. r0,r4,0xa410 /* weird error? */
1417 bne- handle_page_fault /* if not, try to insert a HPTE */
1418 andis. r0,r4,DSISR_DABRMATCH@h
1419 bne- handle_dabr_fault
1420 CURRENT_THREAD_INFO(r11, r1)
1421 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1422 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1423 bne 77f /* then don't call hash_page now */
1424
1425 /*
1426 * r3 contains the faulting address
1427 * r4 msr
1428 * r5 contains the trap number
1429 * r6 contains dsisr
1430 *
1431 * at return r3 = 0 for success, 1 for page fault, negative for error
1432 */
1433 mr r4,r12
1434 ld r6,_DSISR(r1)
1435 bl __hash_page /* build HPTE if possible */
1436 cmpdi r3,0 /* see if __hash_page succeeded */
1437
1438 /* Success */
1439 beq fast_exc_return_irq /* Return from exception on success */
1440
1441 /* Error */
1442 blt- 13f
1443 #endif /* CONFIG_PPC_STD_MMU_64 */
1444
1445 /* Here we have a page fault that hash_page can't handle. */
1446 handle_page_fault:
1447 11: ld r4,_DAR(r1)
1448 ld r5,_DSISR(r1)
1449 addi r3,r1,STACK_FRAME_OVERHEAD
1450 bl do_page_fault
1451 cmpdi r3,0
1452 beq+ 12f
1453 bl save_nvgprs
1454 mr r5,r3
1455 addi r3,r1,STACK_FRAME_OVERHEAD
1456 lwz r4,_DAR(r1)
1457 bl bad_page_fault
1458 b ret_from_except
1459
1460 /* We have a data breakpoint exception - handle it */
1461 handle_dabr_fault:
1462 bl save_nvgprs
1463 ld r4,_DAR(r1)
1464 ld r5,_DSISR(r1)
1465 addi r3,r1,STACK_FRAME_OVERHEAD
1466 bl do_break
1467 12: b ret_from_except_lite
1468
1469
1470 #ifdef CONFIG_PPC_STD_MMU_64
1471 /* We have a page fault that hash_page could handle but HV refused
1472 * the PTE insertion
1473 */
1474 13: bl save_nvgprs
1475 mr r5,r3
1476 addi r3,r1,STACK_FRAME_OVERHEAD
1477 ld r4,_DAR(r1)
1478 bl low_hash_fault
1479 b ret_from_except
1480 #endif
1481
1482 /*
1483 * We come here as a result of a DSI at a point where we don't want
1484 * to call hash_page, such as when we are accessing memory (possibly
1485 * user memory) inside a PMU interrupt that occurred while interrupts
1486 * were soft-disabled. We want to invoke the exception handler for
1487 * the access, or panic if there isn't a handler.
1488 */
1489 77: bl save_nvgprs
1490 mr r4,r3
1491 addi r3,r1,STACK_FRAME_OVERHEAD
1492 li r5,SIGSEGV
1493 bl bad_page_fault
1494 b ret_from_except
1495
1496 /*
1497 * Here we have detected that the kernel stack pointer is bad.
1498 * R9 contains the saved CR, r13 points to the paca,
1499 * r10 contains the (bad) kernel stack pointer,
1500 * r11 and r12 contain the saved SRR0 and SRR1.
1501 * We switch to using an emergency stack, save the registers there,
1502 * and call kernel_bad_stack(), which panics.
1503 */
1504 bad_stack:
1505 ld r1,PACAEMERGSP(r13)
1506 subi r1,r1,64+INT_FRAME_SIZE
1507 std r9,_CCR(r1)
1508 std r10,GPR1(r1)
1509 std r11,_NIP(r1)
1510 std r12,_MSR(r1)
1511 mfspr r11,SPRN_DAR
1512 mfspr r12,SPRN_DSISR
1513 std r11,_DAR(r1)
1514 std r12,_DSISR(r1)
1515 mflr r10
1516 mfctr r11
1517 mfxer r12
1518 std r10,_LINK(r1)
1519 std r11,_CTR(r1)
1520 std r12,_XER(r1)
1521 SAVE_GPR(0,r1)
1522 SAVE_GPR(2,r1)
1523 ld r10,EX_R3(r3)
1524 std r10,GPR3(r1)
1525 SAVE_GPR(4,r1)
1526 SAVE_4GPRS(5,r1)
1527 ld r9,EX_R9(r3)
1528 ld r10,EX_R10(r3)
1529 SAVE_2GPRS(9,r1)
1530 ld r9,EX_R11(r3)
1531 ld r10,EX_R12(r3)
1532 ld r11,EX_R13(r3)
1533 std r9,GPR11(r1)
1534 std r10,GPR12(r1)
1535 std r11,GPR13(r1)
1536 BEGIN_FTR_SECTION
1537 ld r10,EX_CFAR(r3)
1538 std r10,ORIG_GPR3(r1)
1539 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1540 SAVE_8GPRS(14,r1)
1541 SAVE_10GPRS(22,r1)
1542 lhz r12,PACA_TRAP_SAVE(r13)
1543 std r12,_TRAP(r1)
1544 addi r11,r1,INT_FRAME_SIZE
1545 std r11,0(r1)
1546 li r12,0
1547 std r12,0(r11)
1548 ld r2,PACATOC(r13)
1549 ld r11,exception_marker@toc(r2)
1550 std r12,RESULT(r1)
1551 std r11,STACK_FRAME_OVERHEAD-16(r1)
1552 1: addi r3,r1,STACK_FRAME_OVERHEAD
1553 bl kernel_bad_stack
1554 b 1b
1555
1556 /*
1557 * Called from arch_local_irq_enable when an interrupt needs
1558 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1559 * which kind of interrupt. MSR:EE is already off. We generate a
1560 * stackframe like if a real interrupt had happened.
1561 *
1562 * Note: While MSR:EE is off, we need to make sure that _MSR
1563 * in the generated frame has EE set to 1 or the exception
1564 * handler will not properly re-enable them.
1565 */
1566 _GLOBAL(__replay_interrupt)
1567 /* We are going to jump to the exception common code which
1568 * will retrieve various register values from the PACA which
1569 * we don't give a damn about, so we don't bother storing them.
1570 */
1571 mfmsr r12
1572 mflr r11
1573 mfcr r9
1574 ori r12,r12,MSR_EE
1575 cmpwi r3,0x900
1576 beq decrementer_common
1577 cmpwi r3,0x500
1578 beq hardware_interrupt_common
1579 BEGIN_FTR_SECTION
1580 cmpwi r3,0xe80
1581 beq h_doorbell_common
1582 cmpwi r3,0xea0
1583 beq h_virt_irq_common
1584 cmpwi r3,0xe60
1585 beq hmi_exception_common
1586 FTR_SECTION_ELSE
1587 cmpwi r3,0xa00
1588 beq doorbell_super_common
1589 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1590 blr