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Merge branch 'bind_unbind' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / arch / powerpc / kernel / exceptions-64s.S
1 /*
2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
6 *
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
9 *
10 * Most of this originates from head_64.S and thus has the same
11 * copyright history.
12 *
13 */
14
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
20
21 /*
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
27 * must be used.
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
29 * virtual 0xc00...
30 * - Conditional branch targets must be within +/-32K of caller.
31 *
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
37 *
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
44 *
45 * It's impossible to receive interrupts below 0x300 via AIL.
46 *
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
49 *
50 *
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
60 *
61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
63 * vectors there.
64 */
65 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
66 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
67 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
68 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
69 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
70 /*
71 * Data area reserved for FWNMI option.
72 * This address (0x7000) is fixed by the RPA.
73 * pseries and powernv need to keep the whole page from
74 * 0x7000 to 0x8000 free for use by the firmware
75 */
76 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
77 OPEN_TEXT_SECTION(0x8000)
78 #else
79 OPEN_TEXT_SECTION(0x7000)
80 #endif
81
82 USE_FIXED_SECTION(real_vectors)
83
84 /*
85 * This is the start of the interrupt handlers for pSeries
86 * This code runs with relocation off.
87 * Code from here to __end_interrupts gets copied down to real
88 * address 0x100 when we are running a relocatable kernel.
89 * Therefore any relative branches in this section must only
90 * branch to labels in this section.
91 */
92 .globl __start_interrupts
93 __start_interrupts:
94
95 /* No virt vectors corresponding with 0x0..0x100 */
96 EXC_VIRT_NONE(0x4000, 0x100)
97
98
99 #ifdef CONFIG_PPC_P7_NAP
100 /*
101 * If running native on arch 2.06 or later, check if we are waking up
102 * from nap/sleep/winkle, and branch to idle handler.
103 */
104 #define IDLETEST(n) \
105 BEGIN_FTR_SECTION ; \
106 mfspr r10,SPRN_SRR1 ; \
107 rlwinm. r10,r10,47-31,30,31 ; \
108 beq- 1f ; \
109 cmpwi cr3,r10,2 ; \
110 BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \
111 1: \
112 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
113 #else
114 #define IDLETEST NOTEST
115 #endif
116
117 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
118 SET_SCRATCH0(r13)
119 /*
120 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
121 * being used, so a nested NMI exception would corrupt it.
122 */
123 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
124 IDLETEST, 0x100)
125
126 EXC_REAL_END(system_reset, 0x100, 0x100)
127 EXC_VIRT_NONE(0x4100, 0x100)
128
129 #ifdef CONFIG_PPC_P7_NAP
130 EXC_COMMON_BEGIN(system_reset_idle_common)
131 b pnv_powersave_wakeup
132 #endif
133
134 EXC_COMMON_BEGIN(system_reset_common)
135 /*
136 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
137 * to recover, but nested NMI will notice in_nmi and not recover
138 * because of the use of the NMI stack. in_nmi reentrancy is tested in
139 * system_reset_exception.
140 */
141 lhz r10,PACA_IN_NMI(r13)
142 addi r10,r10,1
143 sth r10,PACA_IN_NMI(r13)
144 li r10,MSR_RI
145 mtmsrd r10,1
146
147 mr r10,r1
148 ld r1,PACA_NMI_EMERG_SP(r13)
149 subi r1,r1,INT_FRAME_SIZE
150 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
151 system_reset, system_reset_exception,
152 ADD_NVGPRS;ADD_RECONCILE)
153
154 /*
155 * The stack is no longer in use, decrement in_nmi.
156 */
157 lhz r10,PACA_IN_NMI(r13)
158 subi r10,r10,1
159 sth r10,PACA_IN_NMI(r13)
160
161 b ret_from_except
162
163 #ifdef CONFIG_PPC_PSERIES
164 /*
165 * Vectors for the FWNMI option. Share common code.
166 */
167 TRAMP_REAL_BEGIN(system_reset_fwnmi)
168 SET_SCRATCH0(r13) /* save r13 */
169 /* See comment at system_reset exception */
170 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
171 EXC_STD, NOTEST, 0x100)
172 #endif /* CONFIG_PPC_PSERIES */
173
174
175 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
176 /* This is moved out of line as it can be patched by FW, but
177 * some code path might still want to branch into the original
178 * vector
179 */
180 SET_SCRATCH0(r13) /* save r13 */
181 EXCEPTION_PROLOG_0(PACA_EXMC)
182 BEGIN_FTR_SECTION
183 b machine_check_powernv_early
184 FTR_SECTION_ELSE
185 b machine_check_pSeries_0
186 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
187 EXC_REAL_END(machine_check, 0x200, 0x100)
188 EXC_VIRT_NONE(0x4200, 0x100)
189 TRAMP_REAL_BEGIN(machine_check_powernv_early)
190 BEGIN_FTR_SECTION
191 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
192 /*
193 * Register contents:
194 * R13 = PACA
195 * R9 = CR
196 * Original R9 to R13 is saved on PACA_EXMC
197 *
198 * Switch to mc_emergency stack and handle re-entrancy (we limit
199 * the nested MCE upto level 4 to avoid stack overflow).
200 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
201 *
202 * We use paca->in_mce to check whether this is the first entry or
203 * nested machine check. We increment paca->in_mce to track nested
204 * machine checks.
205 *
206 * If this is the first entry then set stack pointer to
207 * paca->mc_emergency_sp, otherwise r1 is already pointing to
208 * stack frame on mc_emergency stack.
209 *
210 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
211 * checkstop if we get another machine check exception before we do
212 * rfid with MSR_ME=1.
213 *
214 * This interrupt can wake directly from idle. If that is the case,
215 * the machine check is handled then the idle wakeup code is called
216 * to restore state. In that case, the POWER9 DD1 idle PACA workaround
217 * is not applied in the early machine check code, which will cause
218 * bugs.
219 */
220 mr r11,r1 /* Save r1 */
221 lhz r10,PACA_IN_MCE(r13)
222 cmpwi r10,0 /* Are we in nested machine check */
223 bne 0f /* Yes, we are. */
224 /* First machine check entry */
225 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
226 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
227 addi r10,r10,1 /* increment paca->in_mce */
228 sth r10,PACA_IN_MCE(r13)
229 /* Limit nested MCE to level 4 to avoid stack overflow */
230 cmpwi r10,4
231 bgt 2f /* Check if we hit limit of 4 */
232 std r11,GPR1(r1) /* Save r1 on the stack. */
233 std r11,0(r1) /* make stack chain pointer */
234 mfspr r11,SPRN_SRR0 /* Save SRR0 */
235 std r11,_NIP(r1)
236 mfspr r11,SPRN_SRR1 /* Save SRR1 */
237 std r11,_MSR(r1)
238 mfspr r11,SPRN_DAR /* Save DAR */
239 std r11,_DAR(r1)
240 mfspr r11,SPRN_DSISR /* Save DSISR */
241 std r11,_DSISR(r1)
242 std r9,_CCR(r1) /* Save CR in stackframe */
243 /* Save r9 through r13 from EXMC save area to stack frame. */
244 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
245 mfmsr r11 /* get MSR value */
246 ori r11,r11,MSR_ME /* turn on ME bit */
247 ori r11,r11,MSR_RI /* turn on RI bit */
248 LOAD_HANDLER(r12, machine_check_handle_early)
249 1: mtspr SPRN_SRR0,r12
250 mtspr SPRN_SRR1,r11
251 rfid
252 b . /* prevent speculative execution */
253 2:
254 /* Stack overflow. Stay on emergency stack and panic.
255 * Keep the ME bit off while panic-ing, so that if we hit
256 * another machine check we checkstop.
257 */
258 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
259 ld r11,PACAKMSR(r13)
260 LOAD_HANDLER(r12, unrecover_mce)
261 li r10,MSR_ME
262 andc r11,r11,r10 /* Turn off MSR_ME */
263 b 1b
264 b . /* prevent speculative execution */
265 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
266
267 TRAMP_REAL_BEGIN(machine_check_pSeries)
268 .globl machine_check_fwnmi
269 machine_check_fwnmi:
270 SET_SCRATCH0(r13) /* save r13 */
271 EXCEPTION_PROLOG_0(PACA_EXMC)
272 machine_check_pSeries_0:
273 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
274 /*
275 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
276 * nested machine check corrupts it. machine_check_common enables
277 * MSR_RI.
278 */
279 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
280
281 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
282
283 EXC_COMMON_BEGIN(machine_check_common)
284 /*
285 * Machine check is different because we use a different
286 * save area: PACA_EXMC instead of PACA_EXGEN.
287 */
288 mfspr r10,SPRN_DAR
289 std r10,PACA_EXMC+EX_DAR(r13)
290 mfspr r10,SPRN_DSISR
291 stw r10,PACA_EXMC+EX_DSISR(r13)
292 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
293 FINISH_NAP
294 RECONCILE_IRQ_STATE(r10, r11)
295 ld r3,PACA_EXMC+EX_DAR(r13)
296 lwz r4,PACA_EXMC+EX_DSISR(r13)
297 /* Enable MSR_RI when finished with PACA_EXMC */
298 li r10,MSR_RI
299 mtmsrd r10,1
300 std r3,_DAR(r1)
301 std r4,_DSISR(r1)
302 bl save_nvgprs
303 addi r3,r1,STACK_FRAME_OVERHEAD
304 bl machine_check_exception
305 b ret_from_except
306
307 #define MACHINE_CHECK_HANDLER_WINDUP \
308 /* Clear MSR_RI before setting SRR0 and SRR1. */\
309 li r0,MSR_RI; \
310 mfmsr r9; /* get MSR value */ \
311 andc r9,r9,r0; \
312 mtmsrd r9,1; /* Clear MSR_RI */ \
313 /* Move original SRR0 and SRR1 into the respective regs */ \
314 ld r9,_MSR(r1); \
315 mtspr SPRN_SRR1,r9; \
316 ld r3,_NIP(r1); \
317 mtspr SPRN_SRR0,r3; \
318 ld r9,_CTR(r1); \
319 mtctr r9; \
320 ld r9,_XER(r1); \
321 mtxer r9; \
322 ld r9,_LINK(r1); \
323 mtlr r9; \
324 REST_GPR(0, r1); \
325 REST_8GPRS(2, r1); \
326 REST_GPR(10, r1); \
327 ld r11,_CCR(r1); \
328 mtcr r11; \
329 /* Decrement paca->in_mce. */ \
330 lhz r12,PACA_IN_MCE(r13); \
331 subi r12,r12,1; \
332 sth r12,PACA_IN_MCE(r13); \
333 REST_GPR(11, r1); \
334 REST_2GPRS(12, r1); \
335 /* restore original r1. */ \
336 ld r1,GPR1(r1)
337
338 #ifdef CONFIG_PPC_P7_NAP
339 /*
340 * This is an idle wakeup. Low level machine check has already been
341 * done. Queue the event then call the idle code to do the wake up.
342 */
343 EXC_COMMON_BEGIN(machine_check_idle_common)
344 bl machine_check_queue_event
345
346 /*
347 * We have not used any non-volatile GPRs here, and as a rule
348 * most exception code including machine check does not.
349 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
350 * wakeup will restore volatile registers.
351 *
352 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
353 *
354 * Then decrement MCE nesting after finishing with the stack.
355 */
356 ld r3,_MSR(r1)
357
358 lhz r11,PACA_IN_MCE(r13)
359 subi r11,r11,1
360 sth r11,PACA_IN_MCE(r13)
361
362 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
363 /* Recoverability could be improved by reducing the use of SRR1. */
364 li r11,0
365 mtmsrd r11,1
366
367 b pnv_powersave_wakeup_mce
368 #endif
369 /*
370 * Handle machine check early in real mode. We come here with
371 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
372 */
373 EXC_COMMON_BEGIN(machine_check_handle_early)
374 std r0,GPR0(r1) /* Save r0 */
375 EXCEPTION_PROLOG_COMMON_3(0x200)
376 bl save_nvgprs
377 addi r3,r1,STACK_FRAME_OVERHEAD
378 bl machine_check_early
379 std r3,RESULT(r1) /* Save result */
380 ld r12,_MSR(r1)
381
382 #ifdef CONFIG_PPC_P7_NAP
383 /*
384 * Check if thread was in power saving mode. We come here when any
385 * of the following is true:
386 * a. thread wasn't in power saving mode
387 * b. thread was in power saving mode with no state loss,
388 * supervisor state loss or hypervisor state loss.
389 *
390 * Go back to nap/sleep/winkle mode again if (b) is true.
391 */
392 BEGIN_FTR_SECTION
393 rlwinm. r11,r12,47-31,30,31
394 bne machine_check_idle_common
395 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
396 #endif
397
398 /*
399 * Check if we are coming from hypervisor userspace. If yes then we
400 * continue in host kernel in V mode to deliver the MC event.
401 */
402 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
403 beq 5f
404 andi. r11,r12,MSR_PR /* See if coming from user. */
405 bne 9f /* continue in V mode if we are. */
406
407 5:
408 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
409 /*
410 * We are coming from kernel context. Check if we are coming from
411 * guest. if yes, then we can continue. We will fall through
412 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
413 */
414 lbz r11,HSTATE_IN_GUEST(r13)
415 cmpwi r11,0 /* Check if coming from guest */
416 bne 9f /* continue if we are. */
417 #endif
418 /*
419 * At this point we are not sure about what context we come from.
420 * Queue up the MCE event and return from the interrupt.
421 * But before that, check if this is an un-recoverable exception.
422 * If yes, then stay on emergency stack and panic.
423 */
424 andi. r11,r12,MSR_RI
425 bne 2f
426 1: mfspr r11,SPRN_SRR0
427 LOAD_HANDLER(r10,unrecover_mce)
428 mtspr SPRN_SRR0,r10
429 ld r10,PACAKMSR(r13)
430 /*
431 * We are going down. But there are chances that we might get hit by
432 * another MCE during panic path and we may run into unstable state
433 * with no way out. Hence, turn ME bit off while going down, so that
434 * when another MCE is hit during panic path, system will checkstop
435 * and hypervisor will get restarted cleanly by SP.
436 */
437 li r3,MSR_ME
438 andc r10,r10,r3 /* Turn off MSR_ME */
439 mtspr SPRN_SRR1,r10
440 rfid
441 b .
442 2:
443 /*
444 * Check if we have successfully handled/recovered from error, if not
445 * then stay on emergency stack and panic.
446 */
447 ld r3,RESULT(r1) /* Load result */
448 cmpdi r3,0 /* see if we handled MCE successfully */
449
450 beq 1b /* if !handled then panic */
451 /*
452 * Return from MC interrupt.
453 * Queue up the MCE event so that we can log it later, while
454 * returning from kernel or opal call.
455 */
456 bl machine_check_queue_event
457 MACHINE_CHECK_HANDLER_WINDUP
458 rfid
459 9:
460 /* Deliver the machine check to host kernel in V mode. */
461 MACHINE_CHECK_HANDLER_WINDUP
462 b machine_check_pSeries
463
464 EXC_COMMON_BEGIN(unrecover_mce)
465 /* Invoke machine_check_exception to print MCE event and panic. */
466 addi r3,r1,STACK_FRAME_OVERHEAD
467 bl machine_check_exception
468 /*
469 * We will not reach here. Even if we did, there is no way out. Call
470 * unrecoverable_exception and die.
471 */
472 1: addi r3,r1,STACK_FRAME_OVERHEAD
473 bl unrecoverable_exception
474 b 1b
475
476
477 EXC_REAL(data_access, 0x300, 0x80)
478 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
479 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
480
481 EXC_COMMON_BEGIN(data_access_common)
482 /*
483 * Here r13 points to the paca, r9 contains the saved CR,
484 * SRR0 and SRR1 are saved in r11 and r12,
485 * r9 - r13 are saved in paca->exgen.
486 */
487 mfspr r10,SPRN_DAR
488 std r10,PACA_EXGEN+EX_DAR(r13)
489 mfspr r10,SPRN_DSISR
490 stw r10,PACA_EXGEN+EX_DSISR(r13)
491 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
492 RECONCILE_IRQ_STATE(r10, r11)
493 ld r12,_MSR(r1)
494 ld r3,PACA_EXGEN+EX_DAR(r13)
495 lwz r4,PACA_EXGEN+EX_DSISR(r13)
496 li r5,0x300
497 std r3,_DAR(r1)
498 std r4,_DSISR(r1)
499 BEGIN_MMU_FTR_SECTION
500 b do_hash_page /* Try to handle as hpte fault */
501 MMU_FTR_SECTION_ELSE
502 b handle_page_fault
503 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
504
505
506 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
507 SET_SCRATCH0(r13)
508 EXCEPTION_PROLOG_0(PACA_EXSLB)
509 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
510 std r3,PACA_EXSLB+EX_R3(r13)
511 mfspr r3,SPRN_DAR
512 mfspr r12,SPRN_SRR1
513 crset 4*cr6+eq
514 #ifndef CONFIG_RELOCATABLE
515 b slb_miss_realmode
516 #else
517 /*
518 * We can't just use a direct branch to slb_miss_realmode
519 * because the distance from here to there depends on where
520 * the kernel ends up being put.
521 */
522 mfctr r11
523 LOAD_HANDLER(r10, slb_miss_realmode)
524 mtctr r10
525 bctr
526 #endif
527 EXC_REAL_END(data_access_slb, 0x380, 0x80)
528
529 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
530 SET_SCRATCH0(r13)
531 EXCEPTION_PROLOG_0(PACA_EXSLB)
532 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
533 std r3,PACA_EXSLB+EX_R3(r13)
534 mfspr r3,SPRN_DAR
535 mfspr r12,SPRN_SRR1
536 crset 4*cr6+eq
537 #ifndef CONFIG_RELOCATABLE
538 b slb_miss_realmode
539 #else
540 /*
541 * We can't just use a direct branch to slb_miss_realmode
542 * because the distance from here to there depends on where
543 * the kernel ends up being put.
544 */
545 mfctr r11
546 LOAD_HANDLER(r10, slb_miss_realmode)
547 mtctr r10
548 bctr
549 #endif
550 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
551 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
552
553
554 EXC_REAL(instruction_access, 0x400, 0x80)
555 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
556 TRAMP_KVM(PACA_EXGEN, 0x400)
557
558 EXC_COMMON_BEGIN(instruction_access_common)
559 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
560 RECONCILE_IRQ_STATE(r10, r11)
561 ld r12,_MSR(r1)
562 ld r3,_NIP(r1)
563 andis. r4,r12,0x5820
564 li r5,0x400
565 std r3,_DAR(r1)
566 std r4,_DSISR(r1)
567 BEGIN_MMU_FTR_SECTION
568 b do_hash_page /* Try to handle as hpte fault */
569 MMU_FTR_SECTION_ELSE
570 b handle_page_fault
571 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
572
573
574 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
575 SET_SCRATCH0(r13)
576 EXCEPTION_PROLOG_0(PACA_EXSLB)
577 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
578 std r3,PACA_EXSLB+EX_R3(r13)
579 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
580 mfspr r12,SPRN_SRR1
581 crclr 4*cr6+eq
582 #ifndef CONFIG_RELOCATABLE
583 b slb_miss_realmode
584 #else
585 mfctr r11
586 LOAD_HANDLER(r10, slb_miss_realmode)
587 mtctr r10
588 bctr
589 #endif
590 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
591
592 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
593 SET_SCRATCH0(r13)
594 EXCEPTION_PROLOG_0(PACA_EXSLB)
595 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
596 std r3,PACA_EXSLB+EX_R3(r13)
597 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
598 mfspr r12,SPRN_SRR1
599 crclr 4*cr6+eq
600 #ifndef CONFIG_RELOCATABLE
601 b slb_miss_realmode
602 #else
603 mfctr r11
604 LOAD_HANDLER(r10, slb_miss_realmode)
605 mtctr r10
606 bctr
607 #endif
608 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
609 TRAMP_KVM(PACA_EXSLB, 0x480)
610
611
612 /* This handler is used by both 0x380 and 0x480 slb miss interrupts */
613 EXC_COMMON_BEGIN(slb_miss_realmode)
614 /*
615 * r13 points to the PACA, r9 contains the saved CR,
616 * r12 contain the saved SRR1, SRR0 is still ready for return
617 * r3 has the faulting address
618 * r9 - r13 are saved in paca->exslb.
619 * r3 is saved in paca->slb_r3
620 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
621 * We assume we aren't going to take any exceptions during this
622 * procedure.
623 */
624 mflr r10
625 #ifdef CONFIG_RELOCATABLE
626 mtctr r11
627 #endif
628
629 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
630 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
631 std r3,PACA_EXSLB+EX_DAR(r13)
632
633 crset 4*cr0+eq
634 #ifdef CONFIG_PPC_STD_MMU_64
635 BEGIN_MMU_FTR_SECTION
636 bl slb_allocate_realmode
637 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
638 #endif
639
640 ld r10,PACA_EXSLB+EX_LR(r13)
641 ld r3,PACA_EXSLB+EX_R3(r13)
642 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
643 mtlr r10
644
645 beq 8f /* if bad address, make full stack frame */
646
647 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
648 beq- 2f
649
650 /* All done -- return from exception. */
651
652 .machine push
653 .machine "power4"
654 mtcrf 0x80,r9
655 mtcrf 0x02,r9 /* I/D indication is in cr6 */
656 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
657 .machine pop
658
659 RESTORE_PPR_PACA(PACA_EXSLB, r9)
660 ld r9,PACA_EXSLB+EX_R9(r13)
661 ld r10,PACA_EXSLB+EX_R10(r13)
662 ld r11,PACA_EXSLB+EX_R11(r13)
663 ld r12,PACA_EXSLB+EX_R12(r13)
664 ld r13,PACA_EXSLB+EX_R13(r13)
665 rfid
666 b . /* prevent speculative execution */
667
668 2: mfspr r11,SPRN_SRR0
669 LOAD_HANDLER(r10,unrecov_slb)
670 mtspr SPRN_SRR0,r10
671 ld r10,PACAKMSR(r13)
672 mtspr SPRN_SRR1,r10
673 rfid
674 b .
675
676 8: mfspr r11,SPRN_SRR0
677 LOAD_HANDLER(r10,bad_addr_slb)
678 mtspr SPRN_SRR0,r10
679 ld r10,PACAKMSR(r13)
680 mtspr SPRN_SRR1,r10
681 rfid
682 b .
683
684 EXC_COMMON_BEGIN(unrecov_slb)
685 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
686 RECONCILE_IRQ_STATE(r10, r11)
687 bl save_nvgprs
688 1: addi r3,r1,STACK_FRAME_OVERHEAD
689 bl unrecoverable_exception
690 b 1b
691
692 EXC_COMMON_BEGIN(bad_addr_slb)
693 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
694 RECONCILE_IRQ_STATE(r10, r11)
695 ld r3, PACA_EXSLB+EX_DAR(r13)
696 std r3, _DAR(r1)
697 beq cr6, 2f
698 li r10, 0x480 /* fix trap number for I-SLB miss */
699 std r10, _TRAP(r1)
700 2: bl save_nvgprs
701 addi r3, r1, STACK_FRAME_OVERHEAD
702 bl slb_miss_bad_addr
703 b ret_from_except
704
705 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
706 .globl hardware_interrupt_hv;
707 hardware_interrupt_hv:
708 BEGIN_FTR_SECTION
709 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
710 EXC_HV, SOFTEN_TEST_HV)
711 FTR_SECTION_ELSE
712 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
713 EXC_STD, SOFTEN_TEST_PR)
714 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
715 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
716
717 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
718 .globl hardware_interrupt_relon_hv;
719 hardware_interrupt_relon_hv:
720 BEGIN_FTR_SECTION
721 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
722 FTR_SECTION_ELSE
723 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
724 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
725 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
726
727 TRAMP_KVM(PACA_EXGEN, 0x500)
728 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
729 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
730
731
732 EXC_REAL(alignment, 0x600, 0x100)
733 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
734 TRAMP_KVM(PACA_EXGEN, 0x600)
735 EXC_COMMON_BEGIN(alignment_common)
736 mfspr r10,SPRN_DAR
737 std r10,PACA_EXGEN+EX_DAR(r13)
738 mfspr r10,SPRN_DSISR
739 stw r10,PACA_EXGEN+EX_DSISR(r13)
740 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
741 ld r3,PACA_EXGEN+EX_DAR(r13)
742 lwz r4,PACA_EXGEN+EX_DSISR(r13)
743 std r3,_DAR(r1)
744 std r4,_DSISR(r1)
745 bl save_nvgprs
746 RECONCILE_IRQ_STATE(r10, r11)
747 addi r3,r1,STACK_FRAME_OVERHEAD
748 bl alignment_exception
749 b ret_from_except
750
751
752 EXC_REAL(program_check, 0x700, 0x100)
753 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
754 TRAMP_KVM(PACA_EXGEN, 0x700)
755 EXC_COMMON_BEGIN(program_check_common)
756 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
757 bl save_nvgprs
758 RECONCILE_IRQ_STATE(r10, r11)
759 addi r3,r1,STACK_FRAME_OVERHEAD
760 bl program_check_exception
761 b ret_from_except
762
763
764 EXC_REAL(fp_unavailable, 0x800, 0x100)
765 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
766 TRAMP_KVM(PACA_EXGEN, 0x800)
767 EXC_COMMON_BEGIN(fp_unavailable_common)
768 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
769 bne 1f /* if from user, just load it up */
770 bl save_nvgprs
771 RECONCILE_IRQ_STATE(r10, r11)
772 addi r3,r1,STACK_FRAME_OVERHEAD
773 bl kernel_fp_unavailable_exception
774 BUG_OPCODE
775 1:
776 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
777 BEGIN_FTR_SECTION
778 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
779 * transaction), go do TM stuff
780 */
781 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
782 bne- 2f
783 END_FTR_SECTION_IFSET(CPU_FTR_TM)
784 #endif
785 bl load_up_fpu
786 b fast_exception_return
787 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
788 2: /* User process was in a transaction */
789 bl save_nvgprs
790 RECONCILE_IRQ_STATE(r10, r11)
791 addi r3,r1,STACK_FRAME_OVERHEAD
792 bl fp_unavailable_tm
793 b ret_from_except
794 #endif
795
796
797 EXC_REAL_MASKABLE(decrementer, 0x900, 0x80)
798 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900)
799 TRAMP_KVM(PACA_EXGEN, 0x900)
800 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
801
802
803 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
804 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
805 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
806 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
807
808
809 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100)
810 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00)
811 TRAMP_KVM(PACA_EXGEN, 0xa00)
812 #ifdef CONFIG_PPC_DOORBELL
813 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
814 #else
815 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
816 #endif
817
818
819 EXC_REAL(trap_0b, 0xb00, 0x100)
820 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
821 TRAMP_KVM(PACA_EXGEN, 0xb00)
822 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
823
824 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
825 /*
826 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems
827 * that support it) before changing to HMT_MEDIUM. That allows the KVM
828 * code to save that value into the guest state (it is the guest's PPR
829 * value). Otherwise just change to HMT_MEDIUM as userspace has
830 * already saved the PPR.
831 */
832 #define SYSCALL_KVMTEST \
833 SET_SCRATCH0(r13); \
834 GET_PACA(r13); \
835 std r9,PACA_EXGEN+EX_R9(r13); \
836 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
837 HMT_MEDIUM; \
838 std r10,PACA_EXGEN+EX_R10(r13); \
839 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); \
840 mfcr r9; \
841 KVMTEST_PR(0xc00); \
842 GET_SCRATCH0(r13)
843
844 #else
845 #define SYSCALL_KVMTEST \
846 HMT_MEDIUM
847 #endif
848
849 #define LOAD_SYSCALL_HANDLER(reg) \
850 __LOAD_HANDLER(reg, system_call_common)
851
852 /* Syscall routine is used twice, in reloc-off and reloc-on paths */
853 #define SYSCALL_PSERIES_1 \
854 BEGIN_FTR_SECTION \
855 cmpdi r0,0x1ebe ; \
856 beq- 1f ; \
857 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
858 mr r9,r13 ; \
859 GET_PACA(r13) ; \
860 mfspr r11,SPRN_SRR0 ; \
861 0:
862
863 #define SYSCALL_PSERIES_2_RFID \
864 mfspr r12,SPRN_SRR1 ; \
865 LOAD_SYSCALL_HANDLER(r10) ; \
866 mtspr SPRN_SRR0,r10 ; \
867 ld r10,PACAKMSR(r13) ; \
868 mtspr SPRN_SRR1,r10 ; \
869 rfid ; \
870 b . ; /* prevent speculative execution */
871
872 #define SYSCALL_PSERIES_3 \
873 /* Fast LE/BE switch system call */ \
874 1: mfspr r12,SPRN_SRR1 ; \
875 xori r12,r12,MSR_LE ; \
876 mtspr SPRN_SRR1,r12 ; \
877 rfid ; /* return to userspace */ \
878 b . ; /* prevent speculative execution */
879
880 #if defined(CONFIG_RELOCATABLE)
881 /*
882 * We can't branch directly so we do it via the CTR which
883 * is volatile across system calls.
884 */
885 #define SYSCALL_PSERIES_2_DIRECT \
886 LOAD_SYSCALL_HANDLER(r12) ; \
887 mtctr r12 ; \
888 mfspr r12,SPRN_SRR1 ; \
889 li r10,MSR_RI ; \
890 mtmsrd r10,1 ; \
891 bctr ;
892 #else
893 /* We can branch directly */
894 #define SYSCALL_PSERIES_2_DIRECT \
895 mfspr r12,SPRN_SRR1 ; \
896 li r10,MSR_RI ; \
897 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
898 b system_call_common ;
899 #endif
900
901 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
902 SYSCALL_KVMTEST
903 SYSCALL_PSERIES_1
904 SYSCALL_PSERIES_2_RFID
905 SYSCALL_PSERIES_3
906 EXC_REAL_END(system_call, 0xc00, 0x100)
907
908 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
909 SYSCALL_KVMTEST
910 SYSCALL_PSERIES_1
911 SYSCALL_PSERIES_2_DIRECT
912 SYSCALL_PSERIES_3
913 EXC_VIRT_END(system_call, 0x4c00, 0x100)
914
915 TRAMP_KVM(PACA_EXGEN, 0xc00)
916
917
918 EXC_REAL(single_step, 0xd00, 0x100)
919 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
920 TRAMP_KVM(PACA_EXGEN, 0xd00)
921 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
922
923 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
924 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
925 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
926 EXC_COMMON_BEGIN(h_data_storage_common)
927 mfspr r10,SPRN_HDAR
928 std r10,PACA_EXGEN+EX_DAR(r13)
929 mfspr r10,SPRN_HDSISR
930 stw r10,PACA_EXGEN+EX_DSISR(r13)
931 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
932 bl save_nvgprs
933 RECONCILE_IRQ_STATE(r10, r11)
934 addi r3,r1,STACK_FRAME_OVERHEAD
935 bl unknown_exception
936 b ret_from_except
937
938
939 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
940 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
941 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
942 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
943
944
945 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
946 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
947 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
948 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
949
950
951 /*
952 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
953 * first, and then eventaully from there to the trampoline to get into virtual
954 * mode.
955 */
956 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
957 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
958 EXC_VIRT_NONE(0x4e60, 0x20)
959 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
960 TRAMP_REAL_BEGIN(hmi_exception_early)
961 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
962 mr r10,r1 /* Save r1 */
963 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
964 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
965 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
966 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
967 EXCEPTION_PROLOG_COMMON_1()
968 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
969 EXCEPTION_PROLOG_COMMON_3(0xe60)
970 addi r3,r1,STACK_FRAME_OVERHEAD
971 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
972 /* Windup the stack. */
973 /* Move original HSRR0 and HSRR1 into the respective regs */
974 ld r9,_MSR(r1)
975 mtspr SPRN_HSRR1,r9
976 ld r3,_NIP(r1)
977 mtspr SPRN_HSRR0,r3
978 ld r9,_CTR(r1)
979 mtctr r9
980 ld r9,_XER(r1)
981 mtxer r9
982 ld r9,_LINK(r1)
983 mtlr r9
984 REST_GPR(0, r1)
985 REST_8GPRS(2, r1)
986 REST_GPR(10, r1)
987 ld r11,_CCR(r1)
988 mtcr r11
989 REST_GPR(11, r1)
990 REST_2GPRS(12, r1)
991 /* restore original r1. */
992 ld r1,GPR1(r1)
993
994 /*
995 * Go to virtual mode and pull the HMI event information from
996 * firmware.
997 */
998 .globl hmi_exception_after_realmode
999 hmi_exception_after_realmode:
1000 SET_SCRATCH0(r13)
1001 EXCEPTION_PROLOG_0(PACA_EXGEN)
1002 b tramp_real_hmi_exception
1003
1004 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1005
1006
1007 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20)
1008 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80)
1009 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1010 #ifdef CONFIG_PPC_DOORBELL
1011 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1012 #else
1013 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1014 #endif
1015
1016
1017 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20)
1018 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0)
1019 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1020 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1021
1022
1023 EXC_REAL_NONE(0xec0, 0x20)
1024 EXC_VIRT_NONE(0x4ec0, 0x20)
1025 EXC_REAL_NONE(0xee0, 0x20)
1026 EXC_VIRT_NONE(0x4ee0, 0x20)
1027
1028
1029 EXC_REAL_OOL(performance_monitor, 0xf00, 0x20)
1030 EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00)
1031 TRAMP_KVM(PACA_EXGEN, 0xf00)
1032 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1033
1034
1035 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1036 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1037 TRAMP_KVM(PACA_EXGEN, 0xf20)
1038 EXC_COMMON_BEGIN(altivec_unavailable_common)
1039 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1040 #ifdef CONFIG_ALTIVEC
1041 BEGIN_FTR_SECTION
1042 beq 1f
1043 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1044 BEGIN_FTR_SECTION_NESTED(69)
1045 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1046 * transaction), go do TM stuff
1047 */
1048 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1049 bne- 2f
1050 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1051 #endif
1052 bl load_up_altivec
1053 b fast_exception_return
1054 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1055 2: /* User process was in a transaction */
1056 bl save_nvgprs
1057 RECONCILE_IRQ_STATE(r10, r11)
1058 addi r3,r1,STACK_FRAME_OVERHEAD
1059 bl altivec_unavailable_tm
1060 b ret_from_except
1061 #endif
1062 1:
1063 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1064 #endif
1065 bl save_nvgprs
1066 RECONCILE_IRQ_STATE(r10, r11)
1067 addi r3,r1,STACK_FRAME_OVERHEAD
1068 bl altivec_unavailable_exception
1069 b ret_from_except
1070
1071
1072 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1073 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1074 TRAMP_KVM(PACA_EXGEN, 0xf40)
1075 EXC_COMMON_BEGIN(vsx_unavailable_common)
1076 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1077 #ifdef CONFIG_VSX
1078 BEGIN_FTR_SECTION
1079 beq 1f
1080 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1081 BEGIN_FTR_SECTION_NESTED(69)
1082 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1083 * transaction), go do TM stuff
1084 */
1085 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1086 bne- 2f
1087 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1088 #endif
1089 b load_up_vsx
1090 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1091 2: /* User process was in a transaction */
1092 bl save_nvgprs
1093 RECONCILE_IRQ_STATE(r10, r11)
1094 addi r3,r1,STACK_FRAME_OVERHEAD
1095 bl vsx_unavailable_tm
1096 b ret_from_except
1097 #endif
1098 1:
1099 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1100 #endif
1101 bl save_nvgprs
1102 RECONCILE_IRQ_STATE(r10, r11)
1103 addi r3,r1,STACK_FRAME_OVERHEAD
1104 bl vsx_unavailable_exception
1105 b ret_from_except
1106
1107
1108 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1109 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1110 TRAMP_KVM(PACA_EXGEN, 0xf60)
1111 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1112
1113
1114 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1115 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1116 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1117 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1118
1119
1120 EXC_REAL_NONE(0xfa0, 0x20)
1121 EXC_VIRT_NONE(0x4fa0, 0x20)
1122 EXC_REAL_NONE(0xfc0, 0x20)
1123 EXC_VIRT_NONE(0x4fc0, 0x20)
1124 EXC_REAL_NONE(0xfe0, 0x20)
1125 EXC_VIRT_NONE(0x4fe0, 0x20)
1126
1127 EXC_REAL_NONE(0x1000, 0x100)
1128 EXC_VIRT_NONE(0x5000, 0x100)
1129 EXC_REAL_NONE(0x1100, 0x100)
1130 EXC_VIRT_NONE(0x5100, 0x100)
1131
1132 #ifdef CONFIG_CBE_RAS
1133 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1134 EXC_VIRT_NONE(0x5200, 0x100)
1135 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1136 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1137 #else /* CONFIG_CBE_RAS */
1138 EXC_REAL_NONE(0x1200, 0x100)
1139 EXC_VIRT_NONE(0x5200, 0x100)
1140 #endif
1141
1142
1143 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1144 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1145 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1146 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1147
1148 EXC_REAL_NONE(0x1400, 0x100)
1149 EXC_VIRT_NONE(0x5400, 0x100)
1150
1151 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1152 mtspr SPRN_SPRG_HSCRATCH0,r13
1153 EXCEPTION_PROLOG_0(PACA_EXGEN)
1154 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1155
1156 #ifdef CONFIG_PPC_DENORMALISATION
1157 mfspr r10,SPRN_HSRR1
1158 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1159 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1160 addi r11,r11,-4 /* HSRR0 is next instruction */
1161 bne+ denorm_assist
1162 #endif
1163
1164 KVMTEST_PR(0x1500)
1165 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1166 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1167
1168 #ifdef CONFIG_PPC_DENORMALISATION
1169 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1170 b exc_real_0x1500_denorm_exception_hv
1171 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1172 #else
1173 EXC_VIRT_NONE(0x5500, 0x100)
1174 #endif
1175
1176 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1177
1178 #ifdef CONFIG_PPC_DENORMALISATION
1179 TRAMP_REAL_BEGIN(denorm_assist)
1180 BEGIN_FTR_SECTION
1181 /*
1182 * To denormalise we need to move a copy of the register to itself.
1183 * For POWER6 do that here for all FP regs.
1184 */
1185 mfmsr r10
1186 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1187 xori r10,r10,(MSR_FE0|MSR_FE1)
1188 mtmsrd r10
1189 sync
1190
1191 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1192 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1193 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1194 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1195 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1196 FMR32(0)
1197
1198 FTR_SECTION_ELSE
1199 /*
1200 * To denormalise we need to move a copy of the register to itself.
1201 * For POWER7 do that here for the first 32 VSX registers only.
1202 */
1203 mfmsr r10
1204 oris r10,r10,MSR_VSX@h
1205 mtmsrd r10
1206 sync
1207
1208 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1209 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1210 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1211 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1212 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1213 XVCPSGNDP32(0)
1214
1215 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1216
1217 BEGIN_FTR_SECTION
1218 b denorm_done
1219 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1220 /*
1221 * To denormalise we need to move a copy of the register to itself.
1222 * For POWER8 we need to do that for all 64 VSX registers
1223 */
1224 XVCPSGNDP32(32)
1225 denorm_done:
1226 mtspr SPRN_HSRR0,r11
1227 mtcrf 0x80,r9
1228 ld r9,PACA_EXGEN+EX_R9(r13)
1229 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1230 BEGIN_FTR_SECTION
1231 ld r10,PACA_EXGEN+EX_CFAR(r13)
1232 mtspr SPRN_CFAR,r10
1233 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1234 ld r10,PACA_EXGEN+EX_R10(r13)
1235 ld r11,PACA_EXGEN+EX_R11(r13)
1236 ld r12,PACA_EXGEN+EX_R12(r13)
1237 ld r13,PACA_EXGEN+EX_R13(r13)
1238 HRFID
1239 b .
1240 #endif
1241
1242 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1243
1244
1245 #ifdef CONFIG_CBE_RAS
1246 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1247 EXC_VIRT_NONE(0x5600, 0x100)
1248 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1249 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1250 #else /* CONFIG_CBE_RAS */
1251 EXC_REAL_NONE(0x1600, 0x100)
1252 EXC_VIRT_NONE(0x5600, 0x100)
1253 #endif
1254
1255
1256 EXC_REAL(altivec_assist, 0x1700, 0x100)
1257 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1258 TRAMP_KVM(PACA_EXGEN, 0x1700)
1259 #ifdef CONFIG_ALTIVEC
1260 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1261 #else
1262 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1263 #endif
1264
1265
1266 #ifdef CONFIG_CBE_RAS
1267 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1268 EXC_VIRT_NONE(0x5800, 0x100)
1269 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1270 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1271 #else /* CONFIG_CBE_RAS */
1272 EXC_REAL_NONE(0x1800, 0x100)
1273 EXC_VIRT_NONE(0x5800, 0x100)
1274 #endif
1275
1276
1277 /*
1278 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1279 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1280 * - If it was a doorbell we return immediately since doorbells are edge
1281 * triggered and won't automatically refire.
1282 * - If it was a HMI we return immediately since we handled it in realmode
1283 * and it won't refire.
1284 * - else we hard disable and return.
1285 * This is called with r10 containing the value to OR to the paca field.
1286 */
1287 #define MASKED_INTERRUPT(_H) \
1288 masked_##_H##interrupt: \
1289 std r11,PACA_EXGEN+EX_R11(r13); \
1290 lbz r11,PACAIRQHAPPENED(r13); \
1291 or r11,r11,r10; \
1292 stb r11,PACAIRQHAPPENED(r13); \
1293 cmpwi r10,PACA_IRQ_DEC; \
1294 bne 1f; \
1295 lis r10,0x7fff; \
1296 ori r10,r10,0xffff; \
1297 mtspr SPRN_DEC,r10; \
1298 b 2f; \
1299 1: cmpwi r10,PACA_IRQ_DBELL; \
1300 beq 2f; \
1301 cmpwi r10,PACA_IRQ_HMI; \
1302 beq 2f; \
1303 mfspr r10,SPRN_##_H##SRR1; \
1304 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1305 rotldi r10,r10,16; \
1306 mtspr SPRN_##_H##SRR1,r10; \
1307 2: mtcrf 0x80,r9; \
1308 ld r9,PACA_EXGEN+EX_R9(r13); \
1309 ld r10,PACA_EXGEN+EX_R10(r13); \
1310 ld r11,PACA_EXGEN+EX_R11(r13); \
1311 GET_SCRATCH0(r13); \
1312 ##_H##rfid; \
1313 b .
1314
1315 /*
1316 * Real mode exceptions actually use this too, but alternate
1317 * instruction code patches (which end up in the common .text area)
1318 * cannot reach these if they are put there.
1319 */
1320 USE_FIXED_SECTION(virt_trampolines)
1321 MASKED_INTERRUPT()
1322 MASKED_INTERRUPT(H)
1323
1324 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1325 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1326 /*
1327 * Here all GPRs are unchanged from when the interrupt happened
1328 * except for r13, which is saved in SPRG_SCRATCH0.
1329 */
1330 mfspr r13, SPRN_SRR0
1331 addi r13, r13, 4
1332 mtspr SPRN_SRR0, r13
1333 GET_SCRATCH0(r13)
1334 rfid
1335 b .
1336
1337 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1338 /*
1339 * Here all GPRs are unchanged from when the interrupt happened
1340 * except for r13, which is saved in SPRG_SCRATCH0.
1341 */
1342 mfspr r13, SPRN_HSRR0
1343 addi r13, r13, 4
1344 mtspr SPRN_HSRR0, r13
1345 GET_SCRATCH0(r13)
1346 hrfid
1347 b .
1348 #endif
1349
1350 /*
1351 * Ensure that any handlers that get invoked from the exception prologs
1352 * above are below the first 64KB (0x10000) of the kernel image because
1353 * the prologs assemble the addresses of these handlers using the
1354 * LOAD_HANDLER macro, which uses an ori instruction.
1355 */
1356
1357 /*** Common interrupt handlers ***/
1358
1359
1360 /*
1361 * Relocation-on interrupts: A subset of the interrupts can be delivered
1362 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1363 * it. Addresses are the same as the original interrupt addresses, but
1364 * offset by 0xc000000000004000.
1365 * It's impossible to receive interrupts below 0x300 via this mechanism.
1366 * KVM: None of these traps are from the guest ; anything that escalated
1367 * to HV=1 from HV=0 is delivered via real mode handlers.
1368 */
1369
1370 /*
1371 * This uses the standard macro, since the original 0x300 vector
1372 * only has extra guff for STAB-based processors -- which never
1373 * come here.
1374 */
1375
1376 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1377 b __ppc64_runlatch_on
1378
1379 USE_FIXED_SECTION(virt_trampolines)
1380 /*
1381 * The __end_interrupts marker must be past the out-of-line (OOL)
1382 * handlers, so that they are copied to real address 0x100 when running
1383 * a relocatable kernel. This ensures they can be reached from the short
1384 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1385 * directly, without using LOAD_HANDLER().
1386 */
1387 .align 7
1388 .globl __end_interrupts
1389 __end_interrupts:
1390 DEFINE_FIXED_SYMBOL(__end_interrupts)
1391
1392 #ifdef CONFIG_PPC_970_NAP
1393 EXC_COMMON_BEGIN(power4_fixup_nap)
1394 andc r9,r9,r10
1395 std r9,TI_LOCAL_FLAGS(r11)
1396 ld r10,_LINK(r1) /* make idle task do the */
1397 std r10,_NIP(r1) /* equivalent of a blr */
1398 blr
1399 #endif
1400
1401 CLOSE_FIXED_SECTION(real_vectors);
1402 CLOSE_FIXED_SECTION(real_trampolines);
1403 CLOSE_FIXED_SECTION(virt_vectors);
1404 CLOSE_FIXED_SECTION(virt_trampolines);
1405
1406 USE_TEXT_SECTION()
1407
1408 /*
1409 * Hash table stuff
1410 */
1411 .balign IFETCH_ALIGN_BYTES
1412 do_hash_page:
1413 #ifdef CONFIG_PPC_STD_MMU_64
1414 andis. r0,r4,0xa450 /* weird error? */
1415 bne- handle_page_fault /* if not, try to insert a HPTE */
1416 CURRENT_THREAD_INFO(r11, r1)
1417 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1418 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1419 bne 77f /* then don't call hash_page now */
1420
1421 /*
1422 * r3 contains the faulting address
1423 * r4 msr
1424 * r5 contains the trap number
1425 * r6 contains dsisr
1426 *
1427 * at return r3 = 0 for success, 1 for page fault, negative for error
1428 */
1429 mr r4,r12
1430 ld r6,_DSISR(r1)
1431 bl __hash_page /* build HPTE if possible */
1432 cmpdi r3,0 /* see if __hash_page succeeded */
1433
1434 /* Success */
1435 beq fast_exc_return_irq /* Return from exception on success */
1436
1437 /* Error */
1438 blt- 13f
1439
1440 /* Reload DSISR into r4 for the DABR check below */
1441 ld r4,_DSISR(r1)
1442 #endif /* CONFIG_PPC_STD_MMU_64 */
1443
1444 /* Here we have a page fault that hash_page can't handle. */
1445 handle_page_fault:
1446 11: andis. r0,r4,DSISR_DABRMATCH@h
1447 bne- handle_dabr_fault
1448 ld r4,_DAR(r1)
1449 ld r5,_DSISR(r1)
1450 addi r3,r1,STACK_FRAME_OVERHEAD
1451 bl do_page_fault
1452 cmpdi r3,0
1453 beq+ 12f
1454 bl save_nvgprs
1455 mr r5,r3
1456 addi r3,r1,STACK_FRAME_OVERHEAD
1457 lwz r4,_DAR(r1)
1458 bl bad_page_fault
1459 b ret_from_except
1460
1461 /* We have a data breakpoint exception - handle it */
1462 handle_dabr_fault:
1463 bl save_nvgprs
1464 ld r4,_DAR(r1)
1465 ld r5,_DSISR(r1)
1466 addi r3,r1,STACK_FRAME_OVERHEAD
1467 bl do_break
1468 12: b ret_from_except_lite
1469
1470
1471 #ifdef CONFIG_PPC_STD_MMU_64
1472 /* We have a page fault that hash_page could handle but HV refused
1473 * the PTE insertion
1474 */
1475 13: bl save_nvgprs
1476 mr r5,r3
1477 addi r3,r1,STACK_FRAME_OVERHEAD
1478 ld r4,_DAR(r1)
1479 bl low_hash_fault
1480 b ret_from_except
1481 #endif
1482
1483 /*
1484 * We come here as a result of a DSI at a point where we don't want
1485 * to call hash_page, such as when we are accessing memory (possibly
1486 * user memory) inside a PMU interrupt that occurred while interrupts
1487 * were soft-disabled. We want to invoke the exception handler for
1488 * the access, or panic if there isn't a handler.
1489 */
1490 77: bl save_nvgprs
1491 mr r4,r3
1492 addi r3,r1,STACK_FRAME_OVERHEAD
1493 li r5,SIGSEGV
1494 bl bad_page_fault
1495 b ret_from_except
1496
1497 /*
1498 * Here we have detected that the kernel stack pointer is bad.
1499 * R9 contains the saved CR, r13 points to the paca,
1500 * r10 contains the (bad) kernel stack pointer,
1501 * r11 and r12 contain the saved SRR0 and SRR1.
1502 * We switch to using an emergency stack, save the registers there,
1503 * and call kernel_bad_stack(), which panics.
1504 */
1505 bad_stack:
1506 ld r1,PACAEMERGSP(r13)
1507 subi r1,r1,64+INT_FRAME_SIZE
1508 std r9,_CCR(r1)
1509 std r10,GPR1(r1)
1510 std r11,_NIP(r1)
1511 std r12,_MSR(r1)
1512 mfspr r11,SPRN_DAR
1513 mfspr r12,SPRN_DSISR
1514 std r11,_DAR(r1)
1515 std r12,_DSISR(r1)
1516 mflr r10
1517 mfctr r11
1518 mfxer r12
1519 std r10,_LINK(r1)
1520 std r11,_CTR(r1)
1521 std r12,_XER(r1)
1522 SAVE_GPR(0,r1)
1523 SAVE_GPR(2,r1)
1524 ld r10,EX_R3(r3)
1525 std r10,GPR3(r1)
1526 SAVE_GPR(4,r1)
1527 SAVE_4GPRS(5,r1)
1528 ld r9,EX_R9(r3)
1529 ld r10,EX_R10(r3)
1530 SAVE_2GPRS(9,r1)
1531 ld r9,EX_R11(r3)
1532 ld r10,EX_R12(r3)
1533 ld r11,EX_R13(r3)
1534 std r9,GPR11(r1)
1535 std r10,GPR12(r1)
1536 std r11,GPR13(r1)
1537 BEGIN_FTR_SECTION
1538 ld r10,EX_CFAR(r3)
1539 std r10,ORIG_GPR3(r1)
1540 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1541 SAVE_8GPRS(14,r1)
1542 SAVE_10GPRS(22,r1)
1543 lhz r12,PACA_TRAP_SAVE(r13)
1544 std r12,_TRAP(r1)
1545 addi r11,r1,INT_FRAME_SIZE
1546 std r11,0(r1)
1547 li r12,0
1548 std r12,0(r11)
1549 ld r2,PACATOC(r13)
1550 ld r11,exception_marker@toc(r2)
1551 std r12,RESULT(r1)
1552 std r11,STACK_FRAME_OVERHEAD-16(r1)
1553 1: addi r3,r1,STACK_FRAME_OVERHEAD
1554 bl kernel_bad_stack
1555 b 1b
1556
1557 /*
1558 * Called from arch_local_irq_enable when an interrupt needs
1559 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1560 * which kind of interrupt. MSR:EE is already off. We generate a
1561 * stackframe like if a real interrupt had happened.
1562 *
1563 * Note: While MSR:EE is off, we need to make sure that _MSR
1564 * in the generated frame has EE set to 1 or the exception
1565 * handler will not properly re-enable them.
1566 */
1567 _GLOBAL(__replay_interrupt)
1568 /* We are going to jump to the exception common code which
1569 * will retrieve various register values from the PACA which
1570 * we don't give a damn about, so we don't bother storing them.
1571 */
1572 mfmsr r12
1573 mflr r11
1574 mfcr r9
1575 ori r12,r12,MSR_EE
1576 cmpwi r3,0x900
1577 beq decrementer_common
1578 cmpwi r3,0x500
1579 beq hardware_interrupt_common
1580 BEGIN_FTR_SECTION
1581 cmpwi r3,0xe80
1582 beq h_doorbell_common
1583 cmpwi r3,0xea0
1584 beq h_virt_irq_common
1585 cmpwi r3,0xe60
1586 beq hmi_exception_common
1587 FTR_SECTION_ELSE
1588 cmpwi r3,0xa00
1589 beq doorbell_super_common
1590 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1591 blr