arch/powerpc/include/asm/pci-bridge.h

   1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
   2 #define _ASM_POWERPC_PCI_BRIDGE_H
   3 #ifdef __KERNEL__
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10 #include <linux/pci.h>
  11 #include <linux/list.h>
  12 #include <linux/ioport.h>
  13 #include <asm-generic/pci-bridge.h>
  14
  15 struct device_node;
  16
  17 /*
  18  * Structure of a PCI controller (host bridge)
  19  */
  20 struct pci_controller {
  21         struct pci_bus *bus;
  22         char is_dynamic;
  23 #ifdef CONFIG_PPC64
  24         int node;
  25 #endif
  26         struct device_node *dn;
  27         struct list_head list_node;
  28         struct device *parent;
  29
  30         int first_busno;
  31         int last_busno;
  32         int self_busno;
  33         struct resource busn;
  34
  35         void __iomem *io_base_virt;
  36 #ifdef CONFIG_PPC64
  37         void *io_base_alloc;
  38 #endif
  39         resource_size_t io_base_phys;
  40         resource_size_t pci_io_size;
  41
  42         /* Some machines have a special region to forward the ISA
  43          * "memory" cycles such as VGA memory regions. Left to 0
  44          * if unsupported
  45          */
  46         resource_size_t isa_mem_phys;
  47         resource_size_t isa_mem_size;
  48
  49         struct pci_ops *ops;
  50         unsigned int __iomem *cfg_addr;
  51         void __iomem *cfg_data;
  52
  53         /*
  54          * Used for variants of PCI indirect handling and possible quirks:
  55          *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
  56          *  EXT_REG - provides access to PCI-e extended registers
  57          *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
  58          *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
  59          *   to determine which bus number to match on when generating type0
  60          *   config cycles
  61          *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
  62          *   hanging if we don't have link and try to do config cycles to
  63          *   anything but the PHB.  Only allow talking to the PHB if this is
  64          *   set.
  65          *  BIG_ENDIAN - cfg_addr is a big endian register
  66          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
  67          *   the PLB4.  Effectively disable MRM commands by setting this.
  68          *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
  69          *   link status is in a RC PCIe cfg register (vs being a SoC register)
  70          */
  71 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
  72 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
  73 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
  74 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
  75 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
  76 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
  77 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK      0x00000040
  78         u32 indirect_type;
  79         /* Currently, we limit ourselves to 1 IO range and 3 mem
  80          * ranges since the common pci_bus structure can't handle more
  81          */
  82         struct resource io_resource;
  83         struct resource mem_resources[3];
  84         resource_size_t mem_offset[3];
  85         int global_number;              /* PCI domain number */
  86
  87         resource_size_t dma_window_base_cur;
  88         resource_size_t dma_window_size;
  89
  90 #ifdef CONFIG_PPC64
  91         unsigned long buid;
  92 #endif  /* CONFIG_PPC64 */
  93
  94         void *private_data;
  95 };
  96
  97 /* These are used for config access before all the PCI probing
  98    has been done. */
  99 extern int early_read_config_byte(struct pci_controller *hose, int bus,
 100                         int dev_fn, int where, u8 *val);
 101 extern int early_read_config_word(struct pci_controller *hose, int bus,
 102                         int dev_fn, int where, u16 *val);
 103 extern int early_read_config_dword(struct pci_controller *hose, int bus,
 104                         int dev_fn, int where, u32 *val);
 105 extern int early_write_config_byte(struct pci_controller *hose, int bus,
 106                         int dev_fn, int where, u8 val);
 107 extern int early_write_config_word(struct pci_controller *hose, int bus,
 108                         int dev_fn, int where, u16 val);
 109 extern int early_write_config_dword(struct pci_controller *hose, int bus,
 110                         int dev_fn, int where, u32 val);
 111
 112 extern int early_find_capability(struct pci_controller *hose, int bus,
 113                                  int dev_fn, int cap);
 114
 115 extern void setup_indirect_pci(struct pci_controller* hose,
 116                                resource_size_t cfg_addr,
 117                                resource_size_t cfg_data, u32 flags);
 118
 119 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
 120                                 int offset, int len, u32 *val);
 121
 122 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
 123                                  int offset, int len, u32 val);
 124
 125 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 126 {
 127         return bus->sysdata;
 128 }
 129
 130 #ifndef CONFIG_PPC64
 131
 132 extern int pci_device_from_OF_node(struct device_node *node,
 133                                    u8 *bus, u8 *devfn);
 134 extern void pci_create_OF_bus_map(void);
 135
 136 static inline int isa_vaddr_is_ioport(void __iomem *address)
 137 {
 138         /* No specific ISA handling on ppc32 at this stage, it
 139          * all goes through PCI
 140          */
 141         return 0;
 142 }
 143
 144 #else   /* CONFIG_PPC64 */
 145
 146 /*
 147  * PCI stuff, for nodes representing PCI devices, pointed to
 148  * by device_node->data.
 149  */
 150 struct iommu_table;
 151
 152 struct pci_dn {
 153         int     busno;                  /* pci bus number */
 154         int     devfn;                  /* pci device and function number */
 155
 156         struct  pci_controller *phb;    /* for pci devices */
 157         struct  iommu_table *iommu_table;       /* for phb's or bridges */
 158         struct  device_node *node;      /* back-pointer to the device_node */
 159
 160         int     pci_ext_config_space;   /* for pci devices */
 161
 162         int     force_32bit_msi:1;
 163
 164         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 165 #ifdef CONFIG_EEH
 166         struct eeh_dev *edev;           /* eeh device */
 167 #endif
 168 #define IODA_INVALID_PE         (-1)
 169 #ifdef CONFIG_PPC_POWERNV
 170         int     pe_number;
 171 #endif
 172 };
 173
 174 /* Get the pointer to a device_node's pci_dn */
 175 #define PCI_DN(dn)      ((struct pci_dn *) (dn)->data)
 176
 177 extern void * update_dn_pci_info(struct device_node *dn, void *data);
 178
 179 static inline int pci_device_from_OF_node(struct device_node *np,
 180                                           u8 *bus, u8 *devfn)
 181 {
 182         if (!PCI_DN(np))
 183                 return -ENODEV;
 184         *bus = PCI_DN(np)->busno;
 185         *devfn = PCI_DN(np)->devfn;
 186         return 0;
 187 }
 188
 189 #if defined(CONFIG_EEH)
 190 static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn)
 191 {
 192         /*
 193          * For those OF nodes whose parent isn't PCI bridge, they
 194          * don't have PCI_DN actually. So we have to skip them for
 195          * any EEH operations.
 196          */
 197         if (!dn || !PCI_DN(dn))
 198                 return NULL;
 199
 200         return PCI_DN(dn)->edev;
 201 }
 202 #else
 203 #define of_node_to_eeh_dev(x) (NULL)
 204 #endif
 205
 206 /** Find the bus corresponding to the indicated device node */
 207 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
 208
 209 /** Remove all of the PCI devices under this bus */
 210 extern void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe);
 211 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
 212
 213 /** Discover new pci devices under this bus, and add them */
 214 extern void pcibios_add_pci_devices(struct pci_bus *bus);
 215
 216
 217 extern void isa_bridge_find_early(struct pci_controller *hose);
 218
 219 static inline int isa_vaddr_is_ioport(void __iomem *address)
 220 {
 221         /* Check if address hits the reserved legacy IO range */
 222         unsigned long ea = (unsigned long)address;
 223         return ea >= ISA_IO_BASE && ea < ISA_IO_END;
 224 }
 225
 226 extern int pcibios_unmap_io_space(struct pci_bus *bus);
 227 extern int pcibios_map_io_space(struct pci_bus *bus);
 228
 229 #ifdef CONFIG_NUMA
 230 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
 231 #else
 232 #define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
 233 #endif
 234
 235 #endif  /* CONFIG_PPC64 */
 236
 237 /* Get the PCI host controller for an OF device */
 238 extern struct pci_controller *pci_find_hose_for_OF_device(
 239                         struct device_node* node);
 240
 241 /* Fill up host controller resources from the OF node */
 242 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 243                         struct device_node *dev, int primary);
 244
 245 /* Allocate & free a PCI host bridge structure */
 246 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
 247 extern void pcibios_free_controller(struct pci_controller *phb);
 248
 249 #ifdef CONFIG_PCI
 250 extern int pcibios_vaddr_is_ioport(void __iomem *address);
 251 #else
 252 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
 253 {
 254         return 0;
 255 }
 256 #endif  /* CONFIG_PCI */
 257
 258 #endif  /* __KERNEL__ */
 259 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */