arch/powerpc/include/asm/mmu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_MMU_H_
   3 #define _ASM_POWERPC_MMU_H_
   4 #ifdef __KERNEL__
   5
   6 #include <linux/types.h>
   7
   8 #include <asm/asm-compat.h>
   9 #include <asm/feature-fixups.h>
  10
  11 /*
  12  * MMU features bit definitions
  13  */
  14
  15 /*
  16  * MMU families
  17  */
  18 #define MMU_FTR_HPTE_TABLE              ASM_CONST(0x00000001)
  19 #define MMU_FTR_TYPE_8xx                ASM_CONST(0x00000002)
  20 #define MMU_FTR_TYPE_40x                ASM_CONST(0x00000004)
  21 #define MMU_FTR_TYPE_44x                ASM_CONST(0x00000008)
  22 #define MMU_FTR_TYPE_FSL_E              ASM_CONST(0x00000010)
  23 #define MMU_FTR_TYPE_47x                ASM_CONST(0x00000020)
  24
  25 /* Radix page table supported and enabled */
  26 #define MMU_FTR_TYPE_RADIX              ASM_CONST(0x00000040)
  27
  28 /*
  29  * Individual features below.
  30  */
  31
  32 /*
  33  * Support for 68 bit VA space. We added that from ISA 2.05
  34  */
  35 #define MMU_FTR_68_BIT_VA               ASM_CONST(0x00002000)
  36 /*
  37  * Kernel read only support.
  38  * We added the ppp value 0b110 in ISA 2.04.
  39  */
  40 #define MMU_FTR_KERNEL_RO               ASM_CONST(0x00004000)
  41
  42 /*
  43  * We need to clear top 16bits of va (from the remaining 64 bits )in
  44  * tlbie* instructions
  45  */
  46 #define MMU_FTR_TLBIE_CROP_VA           ASM_CONST(0x00008000)
  47
  48 /* Enable use of high BAT registers */
  49 #define MMU_FTR_USE_HIGH_BATS           ASM_CONST(0x00010000)
  50
  51 /* Enable >32-bit physical addresses on 32-bit processor, only used
  52  * by CONFIG_6xx currently as BookE supports that from day 1
  53  */
  54 #define MMU_FTR_BIG_PHYS                ASM_CONST(0x00020000)
  55
  56 /* Enable use of broadcast TLB invalidations. We don't always set it
  57  * on processors that support it due to other constraints with the
  58  * use of such invalidations
  59  */
  60 #define MMU_FTR_USE_TLBIVAX_BCAST       ASM_CONST(0x00040000)
  61
  62 /* Enable use of tlbilx invalidate instructions.
  63  */
  64 #define MMU_FTR_USE_TLBILX              ASM_CONST(0x00080000)
  65
  66 /* This indicates that the processor cannot handle multiple outstanding
  67  * broadcast tlbivax or tlbsync. This makes the code use a spinlock
  68  * around such invalidate forms.
  69  */
  70 #define MMU_FTR_LOCK_BCAST_INVAL        ASM_CONST(0x00100000)
  71
  72 /* This indicates that the processor doesn't handle way selection
  73  * properly and needs SW to track and update the LRU state.  This
  74  * is specific to an errata on e300c2/c3/c4 class parts
  75  */
  76 #define MMU_FTR_NEED_DTLB_SW_LRU        ASM_CONST(0x00200000)
  77
  78 /* Enable use of TLB reservation.  Processor should support tlbsrx.
  79  * instruction and MAS0[WQ].
  80  */
  81 #define MMU_FTR_USE_TLBRSRV             ASM_CONST(0x00800000)
  82
  83 /* Use paired MAS registers (MAS7||MAS3, etc.)
  84  */
  85 #define MMU_FTR_USE_PAIRED_MAS          ASM_CONST(0x01000000)
  86
  87 /* Doesn't support the B bit (1T segment) in SLBIE
  88  */
  89 #define MMU_FTR_NO_SLBIE_B              ASM_CONST(0x02000000)
  90
  91 /* Support 16M large pages
  92  */
  93 #define MMU_FTR_16M_PAGE                ASM_CONST(0x04000000)
  94
  95 /* Supports TLBIEL variant
  96  */
  97 #define MMU_FTR_TLBIEL                  ASM_CONST(0x08000000)
  98
  99 /* Supports tlbies w/o locking
 100  */
 101 #define MMU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x10000000)
 102
 103 /* Large pages can be marked CI
 104  */
 105 #define MMU_FTR_CI_LARGE_PAGE           ASM_CONST(0x20000000)
 106
 107 /* 1T segments available
 108  */
 109 #define MMU_FTR_1T_SEGMENT              ASM_CONST(0x40000000)
 110
 111 /* MMU feature bit sets for various CPUs */
 112 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2   \
 113         MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
 114 #define MMU_FTRS_POWER4         MMU_FTRS_DEFAULT_HPTE_ARCH_V2
 115 #define MMU_FTRS_PPC970         MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
 116 #define MMU_FTRS_POWER5         MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
 117 #define MMU_FTRS_POWER6         MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA
 118 #define MMU_FTRS_POWER7         MMU_FTRS_POWER6
 119 #define MMU_FTRS_POWER8         MMU_FTRS_POWER6
 120 #define MMU_FTRS_POWER9         MMU_FTRS_POWER6
 121 #define MMU_FTRS_CELL           MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
 122                                 MMU_FTR_CI_LARGE_PAGE
 123 #define MMU_FTRS_PA6T           MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
 124                                 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
 125 #ifndef __ASSEMBLY__
 126 #include <linux/bug.h>
 127 #include <asm/cputable.h>
 128
 129 #ifdef CONFIG_PPC_FSL_BOOK3E
 130 #include <asm/percpu.h>
 131 DECLARE_PER_CPU(int, next_tlbcam_idx);
 132 #endif
 133
 134 enum {
 135         MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx |
 136                 MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E |
 137                 MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS |
 138                 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX |
 139                 MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU |
 140                 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
 141                 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
 142                 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
 143                 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
 144                 MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
 145 #ifdef CONFIG_PPC_RADIX_MMU
 146                 MMU_FTR_TYPE_RADIX |
 147 #endif
 148                 0,
 149 };
 150
 151 static inline bool early_mmu_has_feature(unsigned long feature)
 152 {
 153         return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
 154 }
 155
 156 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
 157 #include <linux/jump_label.h>
 158
 159 #define NUM_MMU_FTR_KEYS        32
 160
 161 extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
 162
 163 extern void mmu_feature_keys_init(void);
 164
 165 static __always_inline bool mmu_has_feature(unsigned long feature)
 166 {
 167         int i;
 168
 169 #ifndef __clang__ /* clang can't cope with this */
 170         BUILD_BUG_ON(!__builtin_constant_p(feature));
 171 #endif
 172
 173 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
 174         if (!static_key_initialized) {
 175                 printk("Warning! mmu_has_feature() used prior to jump label init!\n");
 176                 dump_stack();
 177                 return early_mmu_has_feature(feature);
 178         }
 179 #endif
 180
 181         if (!(MMU_FTRS_POSSIBLE & feature))
 182                 return false;
 183
 184         i = __builtin_ctzl(feature);
 185         return static_branch_likely(&mmu_feature_keys[i]);
 186 }
 187
 188 static inline void mmu_clear_feature(unsigned long feature)
 189 {
 190         int i;
 191
 192         i = __builtin_ctzl(feature);
 193         cur_cpu_spec->mmu_features &= ~feature;
 194         static_branch_disable(&mmu_feature_keys[i]);
 195 }
 196 #else
 197
 198 static inline void mmu_feature_keys_init(void)
 199 {
 200
 201 }
 202
 203 static inline bool mmu_has_feature(unsigned long feature)
 204 {
 205         return early_mmu_has_feature(feature);
 206 }
 207
 208 static inline void mmu_clear_feature(unsigned long feature)
 209 {
 210         cur_cpu_spec->mmu_features &= ~feature;
 211 }
 212 #endif /* CONFIG_JUMP_LABEL */
 213
 214 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
 215
 216 #ifdef CONFIG_PPC64
 217 /* This is our real memory area size on ppc64 server, on embedded, we
 218  * make it match the size our of bolted TLB area
 219  */
 220 extern u64 ppc64_rma_size;
 221
 222 /* Cleanup function used by kexec */
 223 extern void mmu_cleanup_all(void);
 224 extern void radix__mmu_cleanup_all(void);
 225
 226 /* Functions for creating and updating partition table on POWER9 */
 227 extern void mmu_partition_table_init(void);
 228 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
 229                                           unsigned long dw1);
 230 #endif /* CONFIG_PPC64 */
 231
 232 struct mm_struct;
 233 #ifdef CONFIG_DEBUG_VM
 234 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
 235 #else /* CONFIG_DEBUG_VM */
 236 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
 237 {
 238 }
 239 #endif /* !CONFIG_DEBUG_VM */
 240
 241 #ifdef CONFIG_PPC_RADIX_MMU
 242 static inline bool radix_enabled(void)
 243 {
 244         return mmu_has_feature(MMU_FTR_TYPE_RADIX);
 245 }
 246
 247 static inline bool early_radix_enabled(void)
 248 {
 249         return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
 250 }
 251 #else
 252 static inline bool radix_enabled(void)
 253 {
 254         return false;
 255 }
 256
 257 static inline bool early_radix_enabled(void)
 258 {
 259         return false;
 260 }
 261 #endif
 262
 263 #endif /* !__ASSEMBLY__ */
 264
 265 /* The kernel use the constants below to index in the page sizes array.
 266  * The use of fixed constants for this purpose is better for performances
 267  * of the low level hash refill handlers.
 268  *
 269  * A non supported page size has a "shift" field set to 0
 270  *
 271  * Any new page size being implemented can get a new entry in here. Whether
 272  * the kernel will use it or not is a different matter though. The actual page
 273  * size used by hugetlbfs is not defined here and may be made variable
 274  *
 275  * Note: This array ended up being a false good idea as it's growing to the
 276  * point where I wonder if we should replace it with something different,
 277  * to think about, feedback welcome. --BenH.
 278  */
 279
 280 /* These are #defines as they have to be used in assembly */
 281 #define MMU_PAGE_4K     0
 282 #define MMU_PAGE_16K    1
 283 #define MMU_PAGE_64K    2
 284 #define MMU_PAGE_64K_AP 3       /* "Admixed pages" (hash64 only) */
 285 #define MMU_PAGE_256K   4
 286 #define MMU_PAGE_512K   5
 287 #define MMU_PAGE_1M     6
 288 #define MMU_PAGE_2M     7
 289 #define MMU_PAGE_4M     8
 290 #define MMU_PAGE_8M     9
 291 #define MMU_PAGE_16M    10
 292 #define MMU_PAGE_64M    11
 293 #define MMU_PAGE_256M   12
 294 #define MMU_PAGE_1G     13
 295 #define MMU_PAGE_16G    14
 296 #define MMU_PAGE_64G    15
 297
 298 /*
 299  * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16
 300  * Also we need to change he type of mm_context.low/high_slices_psize.
 301  */
 302 #define MMU_PAGE_COUNT  16
 303
 304 #ifdef CONFIG_PPC_BOOK3S_64
 305 #include <asm/book3s/64/mmu.h>
 306 #else /* CONFIG_PPC_BOOK3S_64 */
 307
 308 #ifndef __ASSEMBLY__
 309 /* MMU initialization */
 310 extern void early_init_mmu(void);
 311 extern void early_init_mmu_secondary(void);
 312 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 313                                        phys_addr_t first_memblock_size);
 314 static inline void mmu_early_init_devtree(void) { }
 315 #endif /* __ASSEMBLY__ */
 316 #endif
 317
 318 #if defined(CONFIG_PPC_STD_MMU_32)
 319 /* 32-bit classic hash table MMU */
 320 #include <asm/book3s/32/mmu-hash.h>
 321 #elif defined(CONFIG_40x)
 322 /* 40x-style software loaded TLB */
 323 #  include <asm/mmu-40x.h>
 324 #elif defined(CONFIG_44x)
 325 /* 44x-style software loaded TLB */
 326 #  include <asm/mmu-44x.h>
 327 #elif defined(CONFIG_PPC_BOOK3E_MMU)
 328 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
 329 #  include <asm/mmu-book3e.h>
 330 #elif defined (CONFIG_PPC_8xx)
 331 /* Motorola/Freescale 8xx software loaded TLB */
 332 #  include <asm/mmu-8xx.h>
 333 #endif
 334
 335 #endif /* __KERNEL__ */
 336 #endif /* _ASM_POWERPC_MMU_H_ */