arch/powerpc/include/asm/mmu-hash64.h

   1 #ifndef _ASM_POWERPC_MMU_HASH64_H_
   2 #define _ASM_POWERPC_MMU_HASH64_H_
   3 /*
   4  * PowerPC64 memory management structures
   5  *
   6  * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
   7  *   PPC64 rework.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <asm/asm-compat.h>
  16 #include <asm/page.h>
  17
  18 /*
  19  * Segment table
  20  */
  21
  22 #define STE_ESID_V      0x80
  23 #define STE_ESID_KS     0x20
  24 #define STE_ESID_KP     0x10
  25 #define STE_ESID_N      0x08
  26
  27 #define STE_VSID_SHIFT  12
  28
  29 /* Location of cpu0's segment table */
  30 #define STAB0_PAGE      0x6
  31 #define STAB0_OFFSET    (STAB0_PAGE << 12)
  32 #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
  33
  34 #ifndef __ASSEMBLY__
  35 extern char initial_stab[];
  36 #endif /* ! __ASSEMBLY */
  37
  38 /*
  39  * SLB
  40  */
  41
  42 #define SLB_NUM_BOLTED          3
  43 #define SLB_CACHE_ENTRIES       8
  44 #define SLB_MIN_SIZE            32
  45
  46 /* Bits in the SLB ESID word */
  47 #define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
  48
  49 /* Bits in the SLB VSID word */
  50 #define SLB_VSID_SHIFT          12
  51 #define SLB_VSID_SHIFT_1T       24
  52 #define SLB_VSID_SSIZE_SHIFT    62
  53 #define SLB_VSID_B              ASM_CONST(0xc000000000000000)
  54 #define SLB_VSID_B_256M         ASM_CONST(0x0000000000000000)
  55 #define SLB_VSID_B_1T           ASM_CONST(0x4000000000000000)
  56 #define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
  57 #define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
  58 #define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
  59 #define SLB_VSID_L              ASM_CONST(0x0000000000000100)
  60 #define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
  61 #define SLB_VSID_LP             ASM_CONST(0x0000000000000030)
  62 #define SLB_VSID_LP_00          ASM_CONST(0x0000000000000000)
  63 #define SLB_VSID_LP_01          ASM_CONST(0x0000000000000010)
  64 #define SLB_VSID_LP_10          ASM_CONST(0x0000000000000020)
  65 #define SLB_VSID_LP_11          ASM_CONST(0x0000000000000030)
  66 #define SLB_VSID_LLP            (SLB_VSID_L|SLB_VSID_LP)
  67
  68 #define SLB_VSID_KERNEL         (SLB_VSID_KP)
  69 #define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
  70
  71 #define SLBIE_C                 (0x08000000)
  72 #define SLBIE_SSIZE_SHIFT       25
  73
  74 /*
  75  * Hash table
  76  */
  77
  78 #define HPTES_PER_GROUP 8
  79
  80 #define HPTE_V_SSIZE_SHIFT      62
  81 #define HPTE_V_AVPN_SHIFT       7
  82 #define HPTE_V_AVPN             ASM_CONST(0x3fffffffffffff80)
  83 #define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
  84 #define HPTE_V_COMPARE(x,y)     (!(((x) ^ (y)) & 0xffffffffffffff80UL))
  85 #define HPTE_V_BOLTED           ASM_CONST(0x0000000000000010)
  86 #define HPTE_V_LOCK             ASM_CONST(0x0000000000000008)
  87 #define HPTE_V_LARGE            ASM_CONST(0x0000000000000004)
  88 #define HPTE_V_SECONDARY        ASM_CONST(0x0000000000000002)
  89 #define HPTE_V_VALID            ASM_CONST(0x0000000000000001)
  90
  91 #define HPTE_R_PP0              ASM_CONST(0x8000000000000000)
  92 #define HPTE_R_TS               ASM_CONST(0x4000000000000000)
  93 #define HPTE_R_RPN_SHIFT        12
  94 #define HPTE_R_RPN              ASM_CONST(0x3ffffffffffff000)
  95 #define HPTE_R_FLAGS            ASM_CONST(0x00000000000003ff)
  96 #define HPTE_R_PP               ASM_CONST(0x0000000000000003)
  97 #define HPTE_R_N                ASM_CONST(0x0000000000000004)
  98 #define HPTE_R_C                ASM_CONST(0x0000000000000080)
  99 #define HPTE_R_R                ASM_CONST(0x0000000000000100)
 100
 101 #define HPTE_V_1TB_SEG          ASM_CONST(0x4000000000000000)
 102 #define HPTE_V_VRMA_MASK        ASM_CONST(0x4001ffffff000000)
 103
 104 /* Values for PP (assumes Ks=0, Kp=1) */
 105 /* pp0 will always be 0 for linux     */
 106 #define PP_RWXX 0       /* Supervisor read/write, User none */
 107 #define PP_RWRX 1       /* Supervisor read/write, User read */
 108 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
 109 #define PP_RXRX 3       /* Supervisor read,       User read */
 110
 111 #ifndef __ASSEMBLY__
 112
 113 struct hash_pte {
 114         unsigned long v;
 115         unsigned long r;
 116 };
 117
 118 extern struct hash_pte *htab_address;
 119 extern unsigned long htab_size_bytes;
 120 extern unsigned long htab_hash_mask;
 121
 122 /*
 123  * Page size definition
 124  *
 125  *    shift : is the "PAGE_SHIFT" value for that page size
 126  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 127  *            directly to a slbmte "vsid" value
 128  *    penc  : is the HPTE encoding mask for the "LP" field:
 129  *
 130  */
 131 struct mmu_psize_def
 132 {
 133         unsigned int    shift;  /* number of bits */
 134         unsigned int    penc;   /* HPTE encoding */
 135         unsigned int    tlbiel; /* tlbiel supported for that page size */
 136         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
 137         unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
 138 };
 139
 140 #endif /* __ASSEMBLY__ */
 141
 142 /*
 143  * Segment sizes.
 144  * These are the values used by hardware in the B field of
 145  * SLB entries and the first dword of MMU hashtable entries.
 146  * The B field is 2 bits; the values 2 and 3 are unused and reserved.
 147  */
 148 #define MMU_SEGSIZE_256M        0
 149 #define MMU_SEGSIZE_1T          1
 150
 151
 152 #ifndef __ASSEMBLY__
 153
 154 /*
 155  * The current system page and segment sizes
 156  */
 157 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 158 extern int mmu_linear_psize;
 159 extern int mmu_virtual_psize;
 160 extern int mmu_vmalloc_psize;
 161 extern int mmu_vmemmap_psize;
 162 extern int mmu_io_psize;
 163 extern int mmu_kernel_ssize;
 164 extern int mmu_highuser_ssize;
 165 extern u16 mmu_slb_size;
 166 extern unsigned long tce_alloc_start, tce_alloc_end;
 167
 168 /*
 169  * If the processor supports 64k normal pages but not 64k cache
 170  * inhibited pages, we have to be prepared to switch processes
 171  * to use 4k pages when they create cache-inhibited mappings.
 172  * If this is the case, mmu_ci_restrictions will be set to 1.
 173  */
 174 extern int mmu_ci_restrictions;
 175
 176 #ifdef CONFIG_HUGETLB_PAGE
 177 /*
 178  * The page size indexes of the huge pages for use by hugetlbfs
 179  */
 180 extern unsigned int mmu_huge_psizes[MMU_PAGE_COUNT];
 181
 182 #endif /* CONFIG_HUGETLB_PAGE */
 183
 184 /*
 185  * This function sets the AVPN and L fields of the HPTE  appropriately
 186  * for the page size
 187  */
 188 static inline unsigned long hpte_encode_v(unsigned long va, int psize,
 189                                           int ssize)
 190 {
 191         unsigned long v;
 192         v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
 193         v <<= HPTE_V_AVPN_SHIFT;
 194         if (psize != MMU_PAGE_4K)
 195                 v |= HPTE_V_LARGE;
 196         v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
 197         return v;
 198 }
 199
 200 /*
 201  * This function sets the ARPN, and LP fields of the HPTE appropriately
 202  * for the page size. We assume the pa is already "clean" that is properly
 203  * aligned for the requested page size
 204  */
 205 static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
 206 {
 207         unsigned long r;
 208
 209         /* A 4K page needs no special encoding */
 210         if (psize == MMU_PAGE_4K)
 211                 return pa & HPTE_R_RPN;
 212         else {
 213                 unsigned int penc = mmu_psize_defs[psize].penc;
 214                 unsigned int shift = mmu_psize_defs[psize].shift;
 215                 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
 216         }
 217         return r;
 218 }
 219
 220 /*
 221  * Build a VA given VSID, EA and segment size
 222  */
 223 static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
 224                                    int ssize)
 225 {
 226         if (ssize == MMU_SEGSIZE_256M)
 227                 return (vsid << 28) | (ea & 0xfffffffUL);
 228         return (vsid << 40) | (ea & 0xffffffffffUL);
 229 }
 230
 231 /*
 232  * This hashes a virtual address
 233  */
 234
 235 static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
 236                                      int ssize)
 237 {
 238         unsigned long hash, vsid;
 239
 240         if (ssize == MMU_SEGSIZE_256M) {
 241                 hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
 242         } else {
 243                 vsid = va >> 40;
 244                 hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
 245         }
 246         return hash & 0x7fffffffffUL;
 247 }
 248
 249 extern int __hash_page_4K(unsigned long ea, unsigned long access,
 250                           unsigned long vsid, pte_t *ptep, unsigned long trap,
 251                           unsigned int local, int ssize, int subpage_prot);
 252 extern int __hash_page_64K(unsigned long ea, unsigned long access,
 253                            unsigned long vsid, pte_t *ptep, unsigned long trap,
 254                            unsigned int local, int ssize);
 255 struct mm_struct;
 256 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
 257 extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
 258                           unsigned long ea, unsigned long vsid, int local,
 259                           unsigned long trap);
 260
 261 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 262                              unsigned long pstart, unsigned long prot,
 263                              int psize, int ssize);
 264 extern void add_gpage(unsigned long addr, unsigned long page_size,
 265                           unsigned long number_of_pages);
 266 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
 267
 268 extern void hpte_init_native(void);
 269 extern void hpte_init_lpar(void);
 270 extern void hpte_init_iSeries(void);
 271 extern void hpte_init_beat(void);
 272 extern void hpte_init_beat_v3(void);
 273
 274 extern void stabs_alloc(void);
 275 extern void slb_initialize(void);
 276 extern void slb_flush_and_rebolt(void);
 277 extern void stab_initialize(unsigned long stab);
 278
 279 extern void slb_vmalloc_update(void);
 280 extern void slb_set_size(u16 size);
 281 #endif /* __ASSEMBLY__ */
 282
 283 /*
 284  * VSID allocation
 285  *
 286  * We first generate a 36-bit "proto-VSID".  For kernel addresses this
 287  * is equal to the ESID, for user addresses it is:
 288  *      (context << 15) | (esid & 0x7fff)
 289  *
 290  * The two forms are distinguishable because the top bit is 0 for user
 291  * addresses, whereas the top two bits are 1 for kernel addresses.
 292  * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
 293  * now.
 294  *
 295  * The proto-VSIDs are then scrambled into real VSIDs with the
 296  * multiplicative hash:
 297  *
 298  *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 299  *      where   VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
 300  *              VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
 301  *
 302  * This scramble is only well defined for proto-VSIDs below
 303  * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
 304  * reserved.  VSID_MULTIPLIER is prime, so in particular it is
 305  * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 306  * Because the modulus is 2^n-1 we can compute it efficiently without
 307  * a divide or extra multiply (see below).
 308  *
 309  * This scheme has several advantages over older methods:
 310  *
 311  *      - We have VSIDs allocated for every kernel address
 312  * (i.e. everything above 0xC000000000000000), except the very top
 313  * segment, which simplifies several things.
 314  *
 315  *      - We allow for 15 significant bits of ESID and 20 bits of
 316  * context for user addresses.  i.e. 8T (43 bits) of address space for
 317  * up to 1M contexts (although the page table structure and context
 318  * allocation will need changes to take advantage of this).
 319  *
 320  *      - The scramble function gives robust scattering in the hash
 321  * table (at least based on some initial results).  The previous
 322  * method was more susceptible to pathological cases giving excessive
 323  * hash collisions.
 324  */
 325 /*
 326  * WARNING - If you change these you must make sure the asm
 327  * implementations in slb_allocate (slb_low.S), do_stab_bolted
 328  * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
 329  *
 330  * You'll also need to change the precomputed VSID values in head.S
 331  * which are used by the iSeries firmware.
 332  */
 333
 334 #define VSID_MULTIPLIER_256M    ASM_CONST(200730139)    /* 28-bit prime */
 335 #define VSID_BITS_256M          36
 336 #define VSID_MODULUS_256M       ((1UL<<VSID_BITS_256M)-1)
 337
 338 #define VSID_MULTIPLIER_1T      ASM_CONST(12538073)     /* 24-bit prime */
 339 #define VSID_BITS_1T            24
 340 #define VSID_MODULUS_1T         ((1UL<<VSID_BITS_1T)-1)
 341
 342 #define CONTEXT_BITS            19
 343 #define USER_ESID_BITS          16
 344 #define USER_ESID_BITS_1T       4
 345
 346 #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
 347
 348 /*
 349  * This macro generates asm code to compute the VSID scramble
 350  * function.  Used in slb_allocate() and do_stab_bolted.  The function
 351  * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
 352  *
 353  *      rt = register continaing the proto-VSID and into which the
 354  *              VSID will be stored
 355  *      rx = scratch register (clobbered)
 356  *
 357  *      - rt and rx must be different registers
 358  *      - The answer will end up in the low VSID_BITS bits of rt.  The higher
 359  *        bits may contain other garbage, so you may need to mask the
 360  *        result.
 361  */
 362 #define ASM_VSID_SCRAMBLE(rt, rx, size)                                 \
 363         lis     rx,VSID_MULTIPLIER_##size@h;                            \
 364         ori     rx,rx,VSID_MULTIPLIER_##size@l;                         \
 365         mulld   rt,rt,rx;               /* rt = rt * MULTIPLIER */      \
 366                                                                         \
 367         srdi    rx,rt,VSID_BITS_##size;                                 \
 368         clrldi  rt,rt,(64-VSID_BITS_##size);                            \
 369         add     rt,rt,rx;               /* add high and low bits */     \
 370         /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and         \
 371          * 2^36-1+2^28-1.  That in particular means that if r3 >=       \
 372          * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has     \
 373          * the bit clear, r3 already has the answer we want, if it      \
 374          * doesn't, the answer is the low 36 bits of r3+1.  So in all   \
 375          * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
 376         addi    rx,rt,1;                                                \
 377         srdi    rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */   \
 378         add     rt,rt,rx
 379
 380
 381 #ifndef __ASSEMBLY__
 382
 383 typedef unsigned long mm_context_id_t;
 384
 385 typedef struct {
 386         mm_context_id_t id;
 387         u16 user_psize;         /* page size index */
 388
 389 #ifdef CONFIG_PPC_MM_SLICES
 390         u64 low_slices_psize;   /* SLB page size encodings */
 391         u64 high_slices_psize;  /* 4 bits per slice for now */
 392 #else
 393         u16 sllp;               /* SLB page size encoding */
 394 #endif
 395         unsigned long vdso_base;
 396 } mm_context_t;
 397
 398
 399 #if 0
 400 /*
 401  * The code below is equivalent to this function for arguments
 402  * < 2^VSID_BITS, which is all this should ever be called
 403  * with.  However gcc is not clever enough to compute the
 404  * modulus (2^n-1) without a second multiply.
 405  */
 406 #define vsid_scrample(protovsid, size) \
 407         ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
 408
 409 #else /* 1 */
 410 #define vsid_scramble(protovsid, size) \
 411         ({                                                               \
 412                 unsigned long x;                                         \
 413                 x = (protovsid) * VSID_MULTIPLIER_##size;                \
 414                 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
 415                 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
 416         })
 417 #endif /* 1 */
 418
 419 /* This is only valid for addresses >= PAGE_OFFSET */
 420 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
 421 {
 422         if (ssize == MMU_SEGSIZE_256M)
 423                 return vsid_scramble(ea >> SID_SHIFT, 256M);
 424         return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
 425 }
 426
 427 /* Returns the segment size indicator for a user address */
 428 static inline int user_segment_size(unsigned long addr)
 429 {
 430         /* Use 1T segments if possible for addresses >= 1T */
 431         if (addr >= (1UL << SID_SHIFT_1T))
 432                 return mmu_highuser_ssize;
 433         return MMU_SEGSIZE_256M;
 434 }
 435
 436 /* This is only valid for user addresses (which are below 2^44) */
 437 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
 438                                      int ssize)
 439 {
 440         if (ssize == MMU_SEGSIZE_256M)
 441                 return vsid_scramble((context << USER_ESID_BITS)
 442                                      | (ea >> SID_SHIFT), 256M);
 443         return vsid_scramble((context << USER_ESID_BITS_1T)
 444                              | (ea >> SID_SHIFT_1T), 1T);
 445 }
 446
 447 /*
 448  * This is only used on legacy iSeries in lparmap.c,
 449  * hence the 256MB segment assumption.
 450  */
 451 #define VSID_SCRAMBLE(pvsid)    (((pvsid) * VSID_MULTIPLIER_256M) %     \
 452                                  VSID_MODULUS_256M)
 453 #define KERNEL_VSID(ea)         VSID_SCRAMBLE(GET_ESID(ea))
 454
 455 #endif /* __ASSEMBLY__ */
 456
 457 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */