arch/powerpc/boot/dts/sbc8641d.dts

   1 /*
   2  * SBC8641D Device Tree Source
   3  *
   4  * Copyright 2008 Wind River Systems Inc.
   5  *
   6  * Paul Gortmaker (see MAINTAINERS for contact information)
   7  *
   8  * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 /dts-v1/;
  17
  18 / {
  19         model = "SBC8641D";
  20         compatible = "wind,sbc8641";
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 ethernet0 = &enet0;
  26                 ethernet1 = &enet1;
  27                 ethernet2 = &enet2;
  28                 ethernet3 = &enet3;
  29                 serial0 = &serial0;
  30                 serial1 = &serial1;
  31                 pci0 = &pci0;
  32                 pci1 = &pci1;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 PowerPC,8641@0 {
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                         d-cache-line-size = <32>;
  43                         i-cache-line-size = <32>;
  44                         d-cache-size = <32768>;         // L1
  45                         i-cache-size = <32768>;         // L1
  46                         timebase-frequency = <0>;       // From uboot
  47                         bus-frequency = <0>;            // From uboot
  48                         clock-frequency = <0>;          // From uboot
  49                 };
  50                 PowerPC,8641@1 {
  51                         device_type = "cpu";
  52                         reg = <1>;
  53                         d-cache-line-size = <32>;
  54                         i-cache-line-size = <32>;
  55                         d-cache-size = <32768>;
  56                         i-cache-size = <32768>;
  57                         timebase-frequency = <0>;       // From uboot
  58                         bus-frequency = <0>;            // From uboot
  59                         clock-frequency = <0>;          // From uboot
  60                 };
  61         };
  62
  63         memory {
  64                 device_type = "memory";
  65                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
  66         };
  67
  68         localbus@f8005000 {
  69                 #address-cells = <2>;
  70                 #size-cells = <1>;
  71                 compatible = "fsl,mpc8641-localbus", "simple-bus";
  72                 reg = <0xf8005000 0x1000>;
  73                 interrupts = <19 2>;
  74                 interrupt-parent = <&mpic>;
  75
  76                 ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
  77                           1 0 0xf0000000 0x00010000     // 64KB EEPROM
  78                           2 0 0xf1000000 0x00100000     // EPLD (1MB)
  79                           3 0 0xe0000000 0x04000000     // 64MB LB SDRAM (CS3)
  80                           4 0 0xe4000000 0x04000000     // 64MB LB SDRAM (CS4)
  81                           6 0 0xf4000000 0x00100000     // LCD display (1MB)
  82                           7 0 0xe8000000 0x04000000>;   // 64MB OneNAND
  83
  84                 flash@0,0 {
  85                         compatible = "cfi-flash";
  86                         reg = <0 0 0x01000000>;
  87                         bank-width = <2>;
  88                         device-width = <2>;
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         partition@0 {
  92                                 label = "dtb";
  93                                 reg = <0x00000000 0x00100000>;
  94                                 read-only;
  95                         };
  96                         partition@300000 {
  97                                 label = "kernel";
  98                                 reg = <0x00100000 0x00400000>;
  99                                 read-only;
 100                         };
 101                         partition@400000 {
 102                                 label = "fs";
 103                                 reg = <0x00500000 0x00a00000>;
 104                         };
 105                         partition@700000 {
 106                                 label = "firmware";
 107                                 reg = <0x00f00000 0x00100000>;
 108                                 read-only;
 109                         };
 110                 };
 111
 112                 epld@2,0 {
 113                         compatible = "wrs,epld-localbus";
 114                         #address-cells = <2>;
 115                         #size-cells = <1>;
 116                         reg = <2 0 0x100000>;
 117                         ranges = <0 0 5 0 1     // User switches
 118                                   1 0 5 1 1     // Board ID/Rev
 119                                   3 0 5 3 1>;   // LEDs
 120                 };
 121         };
 122
 123         soc@f8000000 {
 124                 #address-cells = <1>;
 125                 #size-cells = <1>;
 126                 device_type = "soc";
 127                 compatible = "simple-bus";
 128                 ranges = <0x00000000 0xf8000000 0x00100000>;
 129                 reg = <0xf8000000 0x00001000>;  // CCSRBAR
 130                 bus-frequency = <0>;
 131
 132                 i2c@3000 {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         cell-index = <0>;
 136                         compatible = "fsl-i2c";
 137                         reg = <0x3000 0x100>;
 138                         interrupts = <43 2>;
 139                         interrupt-parent = <&mpic>;
 140                         dfsrr;
 141                 };
 142
 143                 i2c@3100 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         cell-index = <1>;
 147                         compatible = "fsl-i2c";
 148                         reg = <0x3100 0x100>;
 149                         interrupts = <43 2>;
 150                         interrupt-parent = <&mpic>;
 151                         dfsrr;
 152                 };
 153
 154                 mdio@24520 {
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157                         compatible = "fsl,gianfar-mdio";
 158                         reg = <0x24520 0x20>;
 159
 160                         phy0: ethernet-phy@1f {
 161                                 interrupt-parent = <&mpic>;
 162                                 interrupts = <10 1>;
 163                                 reg = <0x1f>;
 164                                 device_type = "ethernet-phy";
 165                         };
 166                         phy1: ethernet-phy@0 {
 167                                 interrupt-parent = <&mpic>;
 168                                 interrupts = <10 1>;
 169                                 reg = <0>;
 170                                 device_type = "ethernet-phy";
 171                         };
 172                         phy2: ethernet-phy@1 {
 173                                 interrupt-parent = <&mpic>;
 174                                 interrupts = <10 1>;
 175                                 reg = <1>;
 176                                 device_type = "ethernet-phy";
 177                         };
 178                         phy3: ethernet-phy@2 {
 179                                 interrupt-parent = <&mpic>;
 180                                 interrupts = <10 1>;
 181                                 reg = <2>;
 182                                 device_type = "ethernet-phy";
 183                         };
 184                 };
 185
 186                 enet0: ethernet@24000 {
 187                         cell-index = <0>;
 188                         device_type = "network";
 189                         model = "TSEC";
 190                         compatible = "gianfar";
 191                         reg = <0x24000 0x1000>;
 192                         local-mac-address = [ 00 00 00 00 00 00 ];
 193                         interrupts = <29 2 30  2 34 2>;
 194                         interrupt-parent = <&mpic>;
 195                         phy-handle = <&phy0>;
 196                         phy-connection-type = "rgmii-id";
 197                 };
 198
 199                 enet1: ethernet@25000 {
 200                         cell-index = <1>;
 201                         device_type = "network";
 202                         model = "TSEC";
 203                         compatible = "gianfar";
 204                         reg = <0x25000 0x1000>;
 205                         local-mac-address = [ 00 00 00 00 00 00 ];
 206                         interrupts = <35 2 36 2 40 2>;
 207                         interrupt-parent = <&mpic>;
 208                         phy-handle = <&phy1>;
 209                         phy-connection-type = "rgmii-id";
 210                 };
 211
 212                 enet2: ethernet@26000 {
 213                         cell-index = <2>;
 214                         device_type = "network";
 215                         model = "TSEC";
 216                         compatible = "gianfar";
 217                         reg = <0x26000 0x1000>;
 218                         local-mac-address = [ 00 00 00 00 00 00 ];
 219                         interrupts = <31 2 32 2 33 2>;
 220                         interrupt-parent = <&mpic>;
 221                         phy-handle = <&phy2>;
 222                         phy-connection-type = "rgmii-id";
 223                 };
 224
 225                 enet3: ethernet@27000 {
 226                         cell-index = <3>;
 227                         device_type = "network";
 228                         model = "TSEC";
 229                         compatible = "gianfar";
 230                         reg = <0x27000 0x1000>;
 231                         local-mac-address = [ 00 00 00 00 00 00 ];
 232                         interrupts = <37 2 38 2 39 2>;
 233                         interrupt-parent = <&mpic>;
 234                         phy-handle = <&phy3>;
 235                         phy-connection-type = "rgmii-id";
 236                 };
 237
 238                 serial0: serial@4500 {
 239                         cell-index = <0>;
 240                         device_type = "serial";
 241                         compatible = "ns16550";
 242                         reg = <0x4500 0x100>;
 243                         clock-frequency = <0>;
 244                         interrupts = <42 2>;
 245                         interrupt-parent = <&mpic>;
 246                 };
 247
 248                 serial1: serial@4600 {
 249                         cell-index = <1>;
 250                         device_type = "serial";
 251                         compatible = "ns16550";
 252                         reg = <0x4600 0x100>;
 253                         clock-frequency = <0>;
 254                         interrupts = <28 2>;
 255                         interrupt-parent = <&mpic>;
 256                 };
 257
 258                 mpic: pic@40000 {
 259                         clock-frequency = <0>;
 260                         interrupt-controller;
 261                         #address-cells = <0>;
 262                         #interrupt-cells = <2>;
 263                         reg = <0x40000 0x40000>;
 264                         compatible = "chrp,open-pic";
 265                         device_type = "open-pic";
 266                         big-endian;
 267                 };
 268
 269                 global-utilities@e0000 {
 270                         compatible = "fsl,mpc8641-guts";
 271                         reg = <0xe0000 0x1000>;
 272                         fsl,has-rstcr;
 273                 };
 274         };
 275
 276         pci0: pcie@f8008000 {
 277                 cell-index = <0>;
 278                 compatible = "fsl,mpc8641-pcie";
 279                 device_type = "pci";
 280                 #interrupt-cells = <1>;
 281                 #size-cells = <2>;
 282                 #address-cells = <3>;
 283                 reg = <0xf8008000 0x1000>;
 284                 bus-range = <0x0 0xff>;
 285                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 286                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
 287                 clock-frequency = <33333333>;
 288                 interrupt-parent = <&mpic>;
 289                 interrupts = <24 2>;
 290                 interrupt-map-mask = <0xff00 0 0 7>;
 291                 interrupt-map = <
 292                         /* IDSEL 0x0 */
 293                         0x0000 0 0 1 &mpic 0 1
 294                         0x0000 0 0 2 &mpic 1 1
 295                         0x0000 0 0 3 &mpic 2 1
 296                         0x0000 0 0 4 &mpic 3 1
 297                         >;
 298
 299                 pcie@0 {
 300                         reg = <0 0 0 0 0>;
 301                         #size-cells = <2>;
 302                         #address-cells = <3>;
 303                         device_type = "pci";
 304                         ranges = <0x02000000 0x0 0x80000000
 305                                   0x02000000 0x0 0x80000000
 306                                   0x0 0x20000000
 307
 308                                   0x01000000 0x0 0x00000000
 309                                   0x01000000 0x0 0x00000000
 310                                   0x0 0x00100000>;
 311                 };
 312
 313         };
 314
 315         pci1: pcie@f8009000 {
 316                 cell-index = <1>;
 317                 compatible = "fsl,mpc8641-pcie";
 318                 device_type = "pci";
 319                 #interrupt-cells = <1>;
 320                 #size-cells = <2>;
 321                 #address-cells = <3>;
 322                 reg = <0xf8009000 0x1000>;
 323                 bus-range = <0 0xff>;
 324                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 325                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
 326                 clock-frequency = <33333333>;
 327                 interrupt-parent = <&mpic>;
 328                 interrupts = <25 2>;
 329                 interrupt-map-mask = <0xf800 0 0 7>;
 330                 interrupt-map = <
 331                         /* IDSEL 0x0 */
 332                         0x0000 0 0 1 &mpic 4 1
 333                         0x0000 0 0 2 &mpic 5 1
 334                         0x0000 0 0 3 &mpic 6 1
 335                         0x0000 0 0 4 &mpic 7 1
 336                         >;
 337
 338                 pcie@0 {
 339                         reg = <0 0 0 0 0>;
 340                         #size-cells = <2>;
 341                         #address-cells = <3>;
 342                         device_type = "pci";
 343                         ranges = <0x02000000 0x0 0xa0000000
 344                                   0x02000000 0x0 0xa0000000
 345                                   0x0 0x20000000
 346
 347                                   0x01000000 0x0 0x00000000
 348                                   0x01000000 0x0 0x00000000
 349                                   0x0 0x00100000>;
 350                 };
 351         };
 352 };