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mpc52xx/wdt: remove obsolete old WDT implementation
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / katmai.dts
1 /*
2 * Device Tree Source for AMCC Katmai eval board
3 *
4 * Copyright (c) 2006, 2007 IBM Corp.
5 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
6 *
7 * Copyright (c) 2006, 2007 IBM Corp.
8 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
13 */
14
15 /dts-v1/;
16
17 / {
18 #address-cells = <2>;
19 #size-cells = <1>;
20 model = "amcc,katmai";
21 compatible = "amcc,katmai";
22 dcr-parent = <&{/cpus/cpu@0}>;
23
24 aliases {
25 ethernet0 = &EMAC0;
26 serial0 = &UART0;
27 serial1 = &UART1;
28 serial2 = &UART2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 model = "PowerPC,440SPe";
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
41 i-cache-line-size = <32>;
42 d-cache-line-size = <32>;
43 i-cache-size = <32768>;
44 d-cache-size = <32768>;
45 dcr-controller;
46 dcr-access-method = "native";
47 };
48 };
49
50 memory {
51 device_type = "memory";
52 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
53 };
54
55 UIC0: interrupt-controller0 {
56 compatible = "ibm,uic-440spe","ibm,uic";
57 interrupt-controller;
58 cell-index = <0>;
59 dcr-reg = <0x0c0 0x009>;
60 #address-cells = <0>;
61 #size-cells = <0>;
62 #interrupt-cells = <2>;
63 };
64
65 UIC1: interrupt-controller1 {
66 compatible = "ibm,uic-440spe","ibm,uic";
67 interrupt-controller;
68 cell-index = <1>;
69 dcr-reg = <0x0d0 0x009>;
70 #address-cells = <0>;
71 #size-cells = <0>;
72 #interrupt-cells = <2>;
73 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
74 interrupt-parent = <&UIC0>;
75 };
76
77 UIC2: interrupt-controller2 {
78 compatible = "ibm,uic-440spe","ibm,uic";
79 interrupt-controller;
80 cell-index = <2>;
81 dcr-reg = <0x0e0 0x009>;
82 #address-cells = <0>;
83 #size-cells = <0>;
84 #interrupt-cells = <2>;
85 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
86 interrupt-parent = <&UIC0>;
87 };
88
89 UIC3: interrupt-controller3 {
90 compatible = "ibm,uic-440spe","ibm,uic";
91 interrupt-controller;
92 cell-index = <3>;
93 dcr-reg = <0x0f0 0x009>;
94 #address-cells = <0>;
95 #size-cells = <0>;
96 #interrupt-cells = <2>;
97 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
98 interrupt-parent = <&UIC0>;
99 };
100
101 SDR0: sdr {
102 compatible = "ibm,sdr-440spe";
103 dcr-reg = <0x00e 0x002>;
104 };
105
106 CPR0: cpr {
107 compatible = "ibm,cpr-440spe";
108 dcr-reg = <0x00c 0x002>;
109 };
110
111 plb {
112 compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
113 #address-cells = <2>;
114 #size-cells = <1>;
115 ranges;
116 clock-frequency = <0>; /* Filled in by zImage */
117
118 SDRAM0: sdram {
119 compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
120 dcr-reg = <0x010 0x002>;
121 };
122
123 MAL0: mcmal {
124 compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
125 dcr-reg = <0x180 0x062>;
126 num-tx-chans = <2>;
127 num-rx-chans = <1>;
128 interrupt-parent = <&MAL0>;
129 interrupts = <0x0 0x1 0x2 0x3 0x4>;
130 #interrupt-cells = <1>;
131 #address-cells = <0>;
132 #size-cells = <0>;
133 interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
134 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
135 /*SERR*/ 0x2 &UIC1 0x1 0x4
136 /*TXDE*/ 0x3 &UIC1 0x2 0x4
137 /*RXDE*/ 0x4 &UIC1 0x3 0x4>;
138 };
139
140 POB0: opb {
141 compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
145 clock-frequency = <0>; /* Filled in by zImage */
146
147 EBC0: ebc {
148 compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
149 dcr-reg = <0x012 0x002>;
150 #address-cells = <2>;
151 #size-cells = <1>;
152 clock-frequency = <0>; /* Filled in by zImage */
153 interrupts = <0x5 0x1>;
154 interrupt-parent = <&UIC1>;
155 };
156
157 UART0: serial@10000200 {
158 device_type = "serial";
159 compatible = "ns16550";
160 reg = <0x10000200 0x00000008>;
161 virtual-reg = <0xa0000200>;
162 clock-frequency = <0>; /* Filled in by zImage */
163 current-speed = <115200>;
164 interrupt-parent = <&UIC0>;
165 interrupts = <0x0 0x4>;
166 };
167
168 UART1: serial@10000300 {
169 device_type = "serial";
170 compatible = "ns16550";
171 reg = <0x10000300 0x00000008>;
172 virtual-reg = <0xa0000300>;
173 clock-frequency = <0>;
174 current-speed = <0>;
175 interrupt-parent = <&UIC0>;
176 interrupts = <0x1 0x4>;
177 };
178
179
180 UART2: serial@10000600 {
181 device_type = "serial";
182 compatible = "ns16550";
183 reg = <0x10000600 0x00000008>;
184 virtual-reg = <0xa0000600>;
185 clock-frequency = <0>;
186 current-speed = <0>;
187 interrupt-parent = <&UIC1>;
188 interrupts = <0x5 0x4>;
189 };
190
191 IIC0: i2c@10000400 {
192 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
193 reg = <0x10000400 0x00000014>;
194 interrupt-parent = <&UIC0>;
195 interrupts = <0x2 0x4>;
196 };
197
198 IIC1: i2c@10000500 {
199 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
200 reg = <0x10000500 0x00000014>;
201 interrupt-parent = <&UIC0>;
202 interrupts = <0x3 0x4>;
203 };
204
205 EMAC0: ethernet@10000800 {
206 linux,network-index = <0x0>;
207 device_type = "network";
208 compatible = "ibm,emac-440spe", "ibm,emac4";
209 interrupt-parent = <&UIC1>;
210 interrupts = <0x1c 0x4 0x1d 0x4>;
211 reg = <0x10000800 0x00000074>;
212 local-mac-address = [000000000000];
213 mal-device = <&MAL0>;
214 mal-tx-channel = <0>;
215 mal-rx-channel = <0>;
216 cell-index = <0>;
217 max-frame-size = <9000>;
218 rx-fifo-size = <4096>;
219 tx-fifo-size = <2048>;
220 phy-mode = "gmii";
221 phy-map = <0x00000000>;
222 has-inverted-stacr-oc;
223 has-new-stacr-staopc;
224 };
225 };
226
227 PCIX0: pci@c0ec00000 {
228 device_type = "pci";
229 #interrupt-cells = <1>;
230 #size-cells = <2>;
231 #address-cells = <3>;
232 compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
233 primary;
234 large-inbound-windows;
235 enable-msi-hole;
236 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
237 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
238 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
239 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
240 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
241
242 /* Outbound ranges, one memory and one IO,
243 * later cannot be changed
244 */
245 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
246 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
247
248 /* Inbound 2GB range starting at 0 */
249 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
250
251 /* This drives busses 0 to 0xf */
252 bus-range = <0x0 0xf>;
253
254 /*
255 * On Katmai, the following PCI-X interrupts signals
256 * have to be enabled via jumpers (only INTA is
257 * enabled per default):
258 *
259 * INTB: J3: 1-2
260 * INTC: J2: 1-2
261 * INTD: J1: 1-2
262 */
263 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
264 interrupt-map = <
265 /* IDSEL 1 */
266 0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
267 0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
268 0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
269 0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
270 >;
271 };
272
273 PCIE0: pciex@d00000000 {
274 device_type = "pci";
275 #interrupt-cells = <1>;
276 #size-cells = <2>;
277 #address-cells = <3>;
278 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
279 primary;
280 port = <0x0>; /* port number */
281 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
282 0x0000000c 0x10000000 0x00001000>; /* Registers */
283 dcr-reg = <0x100 0x020>;
284 sdr-base = <0x300>;
285
286 /* Outbound ranges, one memory and one IO,
287 * later cannot be changed
288 */
289 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
290 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
291
292 /* Inbound 2GB range starting at 0 */
293 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
294
295 /* This drives busses 10 to 0x1f */
296 bus-range = <0x10 0x1f>;
297
298 /* Legacy interrupts (note the weird polarity, the bridge seems
299 * to invert PCIe legacy interrupts).
300 * We are de-swizzling here because the numbers are actually for
301 * port of the root complex virtual P2P bridge. But I want
302 * to avoid putting a node for it in the tree, so the numbers
303 * below are basically de-swizzled numbers.
304 * The real slot is on idsel 0, so the swizzling is 1:1
305 */
306 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
307 interrupt-map = <
308 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
309 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
310 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
311 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
312 };
313
314 PCIE1: pciex@d20000000 {
315 device_type = "pci";
316 #interrupt-cells = <1>;
317 #size-cells = <2>;
318 #address-cells = <3>;
319 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
320 primary;
321 port = <0x1>; /* port number */
322 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
323 0x0000000c 0x10001000 0x00001000>; /* Registers */
324 dcr-reg = <0x120 0x020>;
325 sdr-base = <0x340>;
326
327 /* Outbound ranges, one memory and one IO,
328 * later cannot be changed
329 */
330 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
331 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
332
333 /* Inbound 2GB range starting at 0 */
334 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
335
336 /* This drives busses 10 to 0x1f */
337 bus-range = <0x20 0x2f>;
338
339 /* Legacy interrupts (note the weird polarity, the bridge seems
340 * to invert PCIe legacy interrupts).
341 * We are de-swizzling here because the numbers are actually for
342 * port of the root complex virtual P2P bridge. But I want
343 * to avoid putting a node for it in the tree, so the numbers
344 * below are basically de-swizzled numbers.
345 * The real slot is on idsel 0, so the swizzling is 1:1
346 */
347 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
348 interrupt-map = <
349 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
350 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
351 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
352 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
353 };
354
355 PCIE2: pciex@d40000000 {
356 device_type = "pci";
357 #interrupt-cells = <1>;
358 #size-cells = <2>;
359 #address-cells = <3>;
360 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
361 primary;
362 port = <0x2>; /* port number */
363 reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
364 0x0000000c 0x10002000 0x00001000>; /* Registers */
365 dcr-reg = <0x140 0x020>;
366 sdr-base = <0x370>;
367
368 /* Outbound ranges, one memory and one IO,
369 * later cannot be changed
370 */
371 ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
372 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
373
374 /* Inbound 2GB range starting at 0 */
375 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
376
377 /* This drives busses 10 to 0x1f */
378 bus-range = <0x30 0x3f>;
379
380 /* Legacy interrupts (note the weird polarity, the bridge seems
381 * to invert PCIe legacy interrupts).
382 * We are de-swizzling here because the numbers are actually for
383 * port of the root complex virtual P2P bridge. But I want
384 * to avoid putting a node for it in the tree, so the numbers
385 * below are basically de-swizzled numbers.
386 * The real slot is on idsel 0, so the swizzling is 1:1
387 */
388 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
389 interrupt-map = <
390 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
391 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
392 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
393 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
394 };
395 };
396
397 chosen {
398 linux,stdout-path = "/plb/opb/serial@10000200";
399 };
400 };
kernel source for telekom puls (alcatel/mediatek)