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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / glacier.dts
1 /*
2 * Device Tree Source for AMCC Glacier (460GT)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11 /dts-v1/;
12
13 / {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,glacier";
17 compatible = "amcc,glacier";
18 dcr-parent = <&{/cpus/cpu@0}>;
19
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 ethernet2 = &EMAC2;
24 ethernet3 = &EMAC3;
25 serial0 = &UART0;
26 serial1 = &UART1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 model = "PowerPC,460GT";
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
41 i-cache-size = <32768>;
42 d-cache-size = <32768>;
43 dcr-controller;
44 dcr-access-method = "native";
45 };
46 };
47
48 memory {
49 device_type = "memory";
50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
51 };
52
53 UIC0: interrupt-controller0 {
54 compatible = "ibm,uic-460gt","ibm,uic";
55 interrupt-controller;
56 cell-index = <0>;
57 dcr-reg = <0x0c0 0x009>;
58 #address-cells = <0>;
59 #size-cells = <0>;
60 #interrupt-cells = <2>;
61 };
62
63 UIC1: interrupt-controller1 {
64 compatible = "ibm,uic-460gt","ibm,uic";
65 interrupt-controller;
66 cell-index = <1>;
67 dcr-reg = <0x0d0 0x009>;
68 #address-cells = <0>;
69 #size-cells = <0>;
70 #interrupt-cells = <2>;
71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
72 interrupt-parent = <&UIC0>;
73 };
74
75 UIC2: interrupt-controller2 {
76 compatible = "ibm,uic-460gt","ibm,uic";
77 interrupt-controller;
78 cell-index = <2>;
79 dcr-reg = <0x0e0 0x009>;
80 #address-cells = <0>;
81 #size-cells = <0>;
82 #interrupt-cells = <2>;
83 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
84 interrupt-parent = <&UIC0>;
85 };
86
87 UIC3: interrupt-controller3 {
88 compatible = "ibm,uic-460gt","ibm,uic";
89 interrupt-controller;
90 cell-index = <3>;
91 dcr-reg = <0x0f0 0x009>;
92 #address-cells = <0>;
93 #size-cells = <0>;
94 #interrupt-cells = <2>;
95 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
96 interrupt-parent = <&UIC0>;
97 };
98
99 SDR0: sdr {
100 compatible = "ibm,sdr-460gt";
101 dcr-reg = <0x00e 0x002>;
102 };
103
104 CPR0: cpr {
105 compatible = "ibm,cpr-460gt";
106 dcr-reg = <0x00c 0x002>;
107 };
108
109 plb {
110 compatible = "ibm,plb-460gt", "ibm,plb4";
111 #address-cells = <2>;
112 #size-cells = <1>;
113 ranges;
114 clock-frequency = <0>; /* Filled in by U-Boot */
115
116 SDRAM0: sdram {
117 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
118 dcr-reg = <0x010 0x002>;
119 };
120
121 MAL0: mcmal {
122 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
123 dcr-reg = <0x180 0x062>;
124 num-tx-chans = <4>;
125 num-rx-chans = <32>;
126 #address-cells = <0>;
127 #size-cells = <0>;
128 interrupt-parent = <&UIC2>;
129 interrupts = < /*TXEOB*/ 0x6 0x4
130 /*RXEOB*/ 0x7 0x4
131 /*SERR*/ 0x3 0x4
132 /*TXDE*/ 0x4 0x4
133 /*RXDE*/ 0x5 0x4>;
134 desc-base-addr-high = <0x8>;
135 };
136
137 POB0: opb {
138 compatible = "ibm,opb-460gt", "ibm,opb";
139 #address-cells = <1>;
140 #size-cells = <1>;
141 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
142 clock-frequency = <0>; /* Filled in by U-Boot */
143
144 EBC0: ebc {
145 compatible = "ibm,ebc-460gt", "ibm,ebc";
146 dcr-reg = <0x012 0x002>;
147 #address-cells = <2>;
148 #size-cells = <1>;
149 clock-frequency = <0>; /* Filled in by U-Boot */
150 /* ranges property is supplied by U-Boot */
151 interrupts = <0x6 0x4>;
152 interrupt-parent = <&UIC1>;
153
154 nor_flash@0,0 {
155 compatible = "amd,s29gl512n", "cfi-flash";
156 bank-width = <2>;
157 reg = <0x00000000 0x00000000 0x04000000>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 partition@0 {
161 label = "kernel";
162 reg = <0x00000000 0x001e0000>;
163 };
164 partition@1e0000 {
165 label = "dtb";
166 reg = <0x001e0000 0x00020000>;
167 };
168 partition@200000 {
169 label = "ramdisk";
170 reg = <0x00200000 0x01400000>;
171 };
172 partition@1600000 {
173 label = "jffs2";
174 reg = <0x01600000 0x00400000>;
175 };
176 partition@1a00000 {
177 label = "user";
178 reg = <0x01a00000 0x02560000>;
179 };
180 partition@3f60000 {
181 label = "env";
182 reg = <0x03f60000 0x00040000>;
183 };
184 partition@3fa0000 {
185 label = "u-boot";
186 reg = <0x03fa0000 0x00060000>;
187 };
188 };
189 };
190
191 UART0: serial@ef600300 {
192 device_type = "serial";
193 compatible = "ns16550";
194 reg = <0xef600300 0x00000008>;
195 virtual-reg = <0xef600300>;
196 clock-frequency = <0>; /* Filled in by U-Boot */
197 current-speed = <0>; /* Filled in by U-Boot */
198 interrupt-parent = <&UIC1>;
199 interrupts = <0x1 0x4>;
200 };
201
202 UART1: serial@ef600400 {
203 device_type = "serial";
204 compatible = "ns16550";
205 reg = <0xef600400 0x00000008>;
206 virtual-reg = <0xef600400>;
207 clock-frequency = <0>; /* Filled in by U-Boot */
208 current-speed = <0>; /* Filled in by U-Boot */
209 interrupt-parent = <&UIC0>;
210 interrupts = <0x1 0x4>;
211 };
212
213 UART2: serial@ef600500 {
214 device_type = "serial";
215 compatible = "ns16550";
216 reg = <0xef600500 0x00000008>;
217 virtual-reg = <0xef600500>;
218 clock-frequency = <0>; /* Filled in by U-Boot */
219 current-speed = <0>; /* Filled in by U-Boot */
220 interrupt-parent = <&UIC1>;
221 interrupts = <0x1d 0x4>;
222 };
223
224 UART3: serial@ef600600 {
225 device_type = "serial";
226 compatible = "ns16550";
227 reg = <0xef600600 0x00000008>;
228 virtual-reg = <0xef600600>;
229 clock-frequency = <0>; /* Filled in by U-Boot */
230 current-speed = <0>; /* Filled in by U-Boot */
231 interrupt-parent = <&UIC1>;
232 interrupts = <0x1e 0x4>;
233 };
234
235 IIC0: i2c@ef600700 {
236 compatible = "ibm,iic-460gt", "ibm,iic";
237 reg = <0xef600700 0x00000014>;
238 interrupt-parent = <&UIC0>;
239 interrupts = <0x2 0x4>;
240 };
241
242 IIC1: i2c@ef600800 {
243 compatible = "ibm,iic-460gt", "ibm,iic";
244 reg = <0xef600800 0x00000014>;
245 interrupt-parent = <&UIC0>;
246 interrupts = <0x3 0x4>;
247 };
248
249 ZMII0: emac-zmii@ef600d00 {
250 compatible = "ibm,zmii-460gt", "ibm,zmii";
251 reg = <0xef600d00 0x0000000c>;
252 };
253
254 RGMII0: emac-rgmii@ef601500 {
255 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
256 reg = <0xef601500 0x00000008>;
257 has-mdio;
258 };
259
260 RGMII1: emac-rgmii@ef601600 {
261 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
262 reg = <0xef601600 0x00000008>;
263 has-mdio;
264 };
265
266 TAH0: emac-tah@ef601350 {
267 compatible = "ibm,tah-460gt", "ibm,tah";
268 reg = <0xef601350 0x00000030>;
269 };
270
271 TAH1: emac-tah@ef601450 {
272 compatible = "ibm,tah-460gt", "ibm,tah";
273 reg = <0xef601450 0x00000030>;
274 };
275
276 EMAC0: ethernet@ef600e00 {
277 device_type = "network";
278 compatible = "ibm,emac-460gt", "ibm,emac4";
279 interrupt-parent = <&EMAC0>;
280 interrupts = <0x0 0x1>;
281 #interrupt-cells = <1>;
282 #address-cells = <0>;
283 #size-cells = <0>;
284 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
285 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
286 reg = <0xef600e00 0x00000074>;
287 local-mac-address = [000000000000]; /* Filled in by U-Boot */
288 mal-device = <&MAL0>;
289 mal-tx-channel = <0>;
290 mal-rx-channel = <0>;
291 cell-index = <0>;
292 max-frame-size = <9000>;
293 rx-fifo-size = <4096>;
294 tx-fifo-size = <2048>;
295 rx-fifo-size-gige = <16384>;
296 phy-mode = "rgmii";
297 phy-map = <0x00000000>;
298 rgmii-device = <&RGMII0>;
299 rgmii-channel = <0>;
300 tah-device = <&TAH0>;
301 tah-channel = <0>;
302 has-inverted-stacr-oc;
303 has-new-stacr-staopc;
304 };
305
306 EMAC1: ethernet@ef600f00 {
307 device_type = "network";
308 compatible = "ibm,emac-460gt", "ibm,emac4";
309 interrupt-parent = <&EMAC1>;
310 interrupts = <0x0 0x1>;
311 #interrupt-cells = <1>;
312 #address-cells = <0>;
313 #size-cells = <0>;
314 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
315 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
316 reg = <0xef600f00 0x00000074>;
317 local-mac-address = [000000000000]; /* Filled in by U-Boot */
318 mal-device = <&MAL0>;
319 mal-tx-channel = <1>;
320 mal-rx-channel = <8>;
321 cell-index = <1>;
322 max-frame-size = <9000>;
323 rx-fifo-size = <4096>;
324 tx-fifo-size = <2048>;
325 rx-fifo-size-gige = <16384>;
326 phy-mode = "rgmii";
327 phy-map = <0x00000000>;
328 rgmii-device = <&RGMII0>;
329 rgmii-channel = <1>;
330 tah-device = <&TAH1>;
331 tah-channel = <1>;
332 has-inverted-stacr-oc;
333 has-new-stacr-staopc;
334 mdio-device = <&EMAC0>;
335 };
336
337 EMAC2: ethernet@ef601100 {
338 device_type = "network";
339 compatible = "ibm,emac-460gt", "ibm,emac4";
340 interrupt-parent = <&EMAC2>;
341 interrupts = <0x0 0x1>;
342 #interrupt-cells = <1>;
343 #address-cells = <0>;
344 #size-cells = <0>;
345 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
346 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
347 reg = <0xef601100 0x00000074>;
348 local-mac-address = [000000000000]; /* Filled in by U-Boot */
349 mal-device = <&MAL0>;
350 mal-tx-channel = <2>;
351 mal-rx-channel = <16>;
352 cell-index = <2>;
353 max-frame-size = <9000>;
354 rx-fifo-size = <4096>;
355 tx-fifo-size = <2048>;
356 rx-fifo-size-gige = <16384>;
357 tx-fifo-size-gige = <16384>; /* emac2&3 only */
358 phy-mode = "rgmii";
359 phy-map = <0x00000000>;
360 rgmii-device = <&RGMII1>;
361 rgmii-channel = <0>;
362 has-inverted-stacr-oc;
363 has-new-stacr-staopc;
364 mdio-device = <&EMAC0>;
365 };
366
367 EMAC3: ethernet@ef601200 {
368 device_type = "network";
369 compatible = "ibm,emac-460gt", "ibm,emac4";
370 interrupt-parent = <&EMAC3>;
371 interrupts = <0x0 0x1>;
372 #interrupt-cells = <1>;
373 #address-cells = <0>;
374 #size-cells = <0>;
375 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
376 /*Wake*/ 0x1 &UIC2 0x17 0x4>;
377 reg = <0xef601200 0x00000074>;
378 local-mac-address = [000000000000]; /* Filled in by U-Boot */
379 mal-device = <&MAL0>;
380 mal-tx-channel = <3>;
381 mal-rx-channel = <24>;
382 cell-index = <3>;
383 max-frame-size = <9000>;
384 rx-fifo-size = <4096>;
385 tx-fifo-size = <2048>;
386 rx-fifo-size-gige = <16384>;
387 tx-fifo-size-gige = <16384>; /* emac2&3 only */
388 phy-mode = "rgmii";
389 phy-map = <0x00000000>;
390 rgmii-device = <&RGMII1>;
391 rgmii-channel = <1>;
392 has-inverted-stacr-oc;
393 has-new-stacr-staopc;
394 mdio-device = <&EMAC0>;
395 };
396 };
397
398 PCIX0: pci@c0ec00000 {
399 device_type = "pci";
400 #interrupt-cells = <1>;
401 #size-cells = <2>;
402 #address-cells = <3>;
403 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
404 primary;
405 large-inbound-windows;
406 enable-msi-hole;
407 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
408 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
409 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
410 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
411 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
412
413 /* Outbound ranges, one memory and one IO,
414 * later cannot be changed
415 */
416 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
417 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
418
419 /* Inbound 2GB range starting at 0 */
420 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
421
422 /* This drives busses 0 to 0x3f */
423 bus-range = <0x0 0x3f>;
424
425 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
426 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
427 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
428 };
429
430 PCIE0: pciex@d00000000 {
431 device_type = "pci";
432 #interrupt-cells = <1>;
433 #size-cells = <2>;
434 #address-cells = <3>;
435 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
436 primary;
437 port = <0x0>; /* port number */
438 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
439 0x0000000c 0x08010000 0x00001000>; /* Registers */
440 dcr-reg = <0x100 0x020>;
441 sdr-base = <0x300>;
442
443 /* Outbound ranges, one memory and one IO,
444 * later cannot be changed
445 */
446 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
447 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
448
449 /* Inbound 2GB range starting at 0 */
450 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
451
452 /* This drives busses 40 to 0x7f */
453 bus-range = <0x40 0x7f>;
454
455 /* Legacy interrupts (note the weird polarity, the bridge seems
456 * to invert PCIe legacy interrupts).
457 * We are de-swizzling here because the numbers are actually for
458 * port of the root complex virtual P2P bridge. But I want
459 * to avoid putting a node for it in the tree, so the numbers
460 * below are basically de-swizzled numbers.
461 * The real slot is on idsel 0, so the swizzling is 1:1
462 */
463 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
464 interrupt-map = <
465 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
466 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
467 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
468 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
469 };
470
471 PCIE1: pciex@d20000000 {
472 device_type = "pci";
473 #interrupt-cells = <1>;
474 #size-cells = <2>;
475 #address-cells = <3>;
476 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
477 primary;
478 port = <0x1>; /* port number */
479 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
480 0x0000000c 0x08011000 0x00001000>; /* Registers */
481 dcr-reg = <0x120 0x020>;
482 sdr-base = <0x340>;
483
484 /* Outbound ranges, one memory and one IO,
485 * later cannot be changed
486 */
487 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
488 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
489
490 /* Inbound 2GB range starting at 0 */
491 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
492
493 /* This drives busses 80 to 0xbf */
494 bus-range = <0x80 0xbf>;
495
496 /* Legacy interrupts (note the weird polarity, the bridge seems
497 * to invert PCIe legacy interrupts).
498 * We are de-swizzling here because the numbers are actually for
499 * port of the root complex virtual P2P bridge. But I want
500 * to avoid putting a node for it in the tree, so the numbers
501 * below are basically de-swizzled numbers.
502 * The real slot is on idsel 0, so the swizzling is 1:1
503 */
504 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
505 interrupt-map = <
506 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
507 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
508 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
509 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
510 };
511 };
512 };
kernel source for telekom puls (alcatel/mediatek)