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[POWERPC] 4xx: Add NOR FLASH entries to Canyonlands and Glacier dts
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / glacier.dts
1 /*
2 * Device Tree Source for AMCC Glacier (460GT)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11 / {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "amcc,glacier";
15 compatible = "amcc,glacier", "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 ethernet2 = &EMAC2;
22 ethernet3 = &EMAC3;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,460GT";
34 reg = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <20>;
38 d-cache-line-size = <20>;
39 i-cache-size = <8000>;
40 d-cache-size = <8000>;
41 dcr-controller;
42 dcr-access-method = "native";
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0 0 0>; /* Filled in by U-Boot */
49 };
50
51 UIC0: interrupt-controller0 {
52 compatible = "ibm,uic-460gt","ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
55 dcr-reg = <0c0 009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 };
60
61 UIC1: interrupt-controller1 {
62 compatible = "ibm,uic-460gt","ibm,uic";
63 interrupt-controller;
64 cell-index = <1>;
65 dcr-reg = <0d0 009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
68 #interrupt-cells = <2>;
69 interrupts = <1e 4 1f 4>; /* cascade */
70 interrupt-parent = <&UIC0>;
71 };
72
73 UIC2: interrupt-controller2 {
74 compatible = "ibm,uic-460gt","ibm,uic";
75 interrupt-controller;
76 cell-index = <2>;
77 dcr-reg = <0e0 009>;
78 #address-cells = <0>;
79 #size-cells = <0>;
80 #interrupt-cells = <2>;
81 interrupts = <a 4 b 4>; /* cascade */
82 interrupt-parent = <&UIC0>;
83 };
84
85 UIC3: interrupt-controller3 {
86 compatible = "ibm,uic-460gt","ibm,uic";
87 interrupt-controller;
88 cell-index = <3>;
89 dcr-reg = <0f0 009>;
90 #address-cells = <0>;
91 #size-cells = <0>;
92 #interrupt-cells = <2>;
93 interrupts = <10 4 11 4>; /* cascade */
94 interrupt-parent = <&UIC0>;
95 };
96
97 SDR0: sdr {
98 compatible = "ibm,sdr-460gt";
99 dcr-reg = <00e 002>;
100 };
101
102 CPR0: cpr {
103 compatible = "ibm,cpr-460gt";
104 dcr-reg = <00c 002>;
105 };
106
107 plb {
108 compatible = "ibm,plb-460gt", "ibm,plb4";
109 #address-cells = <2>;
110 #size-cells = <1>;
111 ranges;
112 clock-frequency = <0>; /* Filled in by U-Boot */
113
114 SDRAM0: sdram {
115 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
116 dcr-reg = <010 2>;
117 };
118
119 MAL0: mcmal {
120 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
121 dcr-reg = <180 62>;
122 num-tx-chans = <4>;
123 num-rx-chans = <20>;
124 #address-cells = <0>;
125 #size-cells = <0>;
126 interrupt-parent = <&UIC2>;
127 interrupts = < /*TXEOB*/ 6 4
128 /*RXEOB*/ 7 4
129 /*SERR*/ 3 4
130 /*TXDE*/ 4 4
131 /*RXDE*/ 5 4>;
132 desc-base-addr-high = <8>;
133 };
134
135 POB0: opb {
136 compatible = "ibm,opb-460gt", "ibm,opb";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <b0000000 4 b0000000 50000000>;
140 clock-frequency = <0>; /* Filled in by U-Boot */
141
142 EBC0: ebc {
143 compatible = "ibm,ebc-460gt", "ibm,ebc";
144 dcr-reg = <012 2>;
145 #address-cells = <2>;
146 #size-cells = <1>;
147 clock-frequency = <0>; /* Filled in by U-Boot */
148 /* ranges property is supplied by U-Boot */
149 interrupts = <6 4>;
150 interrupt-parent = <&UIC1>;
151
152 nor_flash@0,0 {
153 compatible = "amd,s29gl512n", "cfi-flash";
154 bank-width = <2>;
155 reg = <0 000000 4000000>;
156 #address-cells = <1>;
157 #size-cells = <1>;
158 partition@0 {
159 label = "kernel";
160 reg = <0 1e0000>;
161 };
162 partition@1e0000 {
163 label = "dtb";
164 reg = <1e0000 20000>;
165 };
166 partition@200000 {
167 label = "ramdisk";
168 reg = <200000 1400000>;
169 };
170 partition@1600000 {
171 label = "jffs2";
172 reg = <1600000 400000>;
173 };
174 partition@1a00000 {
175 label = "user";
176 reg = <1a00000 2560000>;
177 };
178 partition@3f60000 {
179 label = "env";
180 reg = <3f60000 40000>;
181 };
182 partition@3fa0000 {
183 label = "u-boot";
184 reg = <3fa0000 60000>;
185 };
186 };
187 };
188
189 UART0: serial@ef600300 {
190 device_type = "serial";
191 compatible = "ns16550";
192 reg = <ef600300 8>;
193 virtual-reg = <ef600300>;
194 clock-frequency = <0>; /* Filled in by U-Boot */
195 current-speed = <0>; /* Filled in by U-Boot */
196 interrupt-parent = <&UIC1>;
197 interrupts = <1 4>;
198 };
199
200 UART1: serial@ef600400 {
201 device_type = "serial";
202 compatible = "ns16550";
203 reg = <ef600400 8>;
204 virtual-reg = <ef600400>;
205 clock-frequency = <0>; /* Filled in by U-Boot */
206 current-speed = <0>; /* Filled in by U-Boot */
207 interrupt-parent = <&UIC0>;
208 interrupts = <1 4>;
209 };
210
211 UART2: serial@ef600500 {
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <ef600500 8>;
215 virtual-reg = <ef600500>;
216 clock-frequency = <0>; /* Filled in by U-Boot */
217 current-speed = <0>; /* Filled in by U-Boot */
218 interrupt-parent = <&UIC1>;
219 interrupts = <1d 4>;
220 };
221
222 UART3: serial@ef600600 {
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <ef600600 8>;
226 virtual-reg = <ef600600>;
227 clock-frequency = <0>; /* Filled in by U-Boot */
228 current-speed = <0>; /* Filled in by U-Boot */
229 interrupt-parent = <&UIC1>;
230 interrupts = <1e 4>;
231 };
232
233 IIC0: i2c@ef600700 {
234 compatible = "ibm,iic-460gt", "ibm,iic";
235 reg = <ef600700 14>;
236 interrupt-parent = <&UIC0>;
237 interrupts = <2 4>;
238 };
239
240 IIC1: i2c@ef600800 {
241 compatible = "ibm,iic-460gt", "ibm,iic";
242 reg = <ef600800 14>;
243 interrupt-parent = <&UIC0>;
244 interrupts = <3 4>;
245 };
246
247 ZMII0: emac-zmii@ef600d00 {
248 compatible = "ibm,zmii-460gt", "ibm,zmii";
249 reg = <ef600d00 c>;
250 };
251
252 RGMII0: emac-rgmii@ef601500 {
253 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
254 reg = <ef601500 8>;
255 has-mdio;
256 };
257
258 RGMII1: emac-rgmii@ef601600 {
259 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
260 reg = <ef601600 8>;
261 has-mdio;
262 };
263
264 TAH0: emac-tah@ef601350 {
265 compatible = "ibm,tah-460gt", "ibm,tah";
266 reg = <ef601350 30>;
267 };
268
269 TAH1: emac-tah@ef601450 {
270 compatible = "ibm,tah-460gt", "ibm,tah";
271 reg = <ef601450 30>;
272 };
273
274 EMAC0: ethernet@ef600e00 {
275 device_type = "network";
276 compatible = "ibm,emac-460gt", "ibm,emac4";
277 interrupt-parent = <&EMAC0>;
278 interrupts = <0 1>;
279 #interrupt-cells = <1>;
280 #address-cells = <0>;
281 #size-cells = <0>;
282 interrupt-map = </*Status*/ 0 &UIC2 10 4
283 /*Wake*/ 1 &UIC2 14 4>;
284 reg = <ef600e00 70>;
285 local-mac-address = [000000000000]; /* Filled in by U-Boot */
286 mal-device = <&MAL0>;
287 mal-tx-channel = <0>;
288 mal-rx-channel = <0>;
289 cell-index = <0>;
290 max-frame-size = <2328>;
291 rx-fifo-size = <1000>;
292 tx-fifo-size = <800>;
293 phy-mode = "rgmii";
294 phy-map = <00000000>;
295 rgmii-device = <&RGMII0>;
296 rgmii-channel = <0>;
297 tah-device = <&TAH0>;
298 tah-channel = <0>;
299 has-inverted-stacr-oc;
300 has-new-stacr-staopc;
301 };
302
303 EMAC1: ethernet@ef600f00 {
304 device_type = "network";
305 compatible = "ibm,emac-460gt", "ibm,emac4";
306 interrupt-parent = <&EMAC1>;
307 interrupts = <0 1>;
308 #interrupt-cells = <1>;
309 #address-cells = <0>;
310 #size-cells = <0>;
311 interrupt-map = </*Status*/ 0 &UIC2 11 4
312 /*Wake*/ 1 &UIC2 15 4>;
313 reg = <ef600f00 70>;
314 local-mac-address = [000000000000]; /* Filled in by U-Boot */
315 mal-device = <&MAL0>;
316 mal-tx-channel = <1>;
317 mal-rx-channel = <8>;
318 cell-index = <1>;
319 max-frame-size = <2328>;
320 rx-fifo-size = <1000>;
321 tx-fifo-size = <800>;
322 phy-mode = "rgmii";
323 phy-map = <00000000>;
324 rgmii-device = <&RGMII0>;
325 rgmii-channel = <1>;
326 tah-device = <&TAH1>;
327 tah-channel = <1>;
328 has-inverted-stacr-oc;
329 has-new-stacr-staopc;
330 mdio-device = <&EMAC0>;
331 };
332
333 EMAC2: ethernet@ef601100 {
334 device_type = "network";
335 compatible = "ibm,emac-460gt", "ibm,emac4";
336 interrupt-parent = <&EMAC2>;
337 interrupts = <0 1>;
338 #interrupt-cells = <1>;
339 #address-cells = <0>;
340 #size-cells = <0>;
341 interrupt-map = </*Status*/ 0 &UIC2 12 4
342 /*Wake*/ 1 &UIC2 16 4>;
343 reg = <ef601100 70>;
344 local-mac-address = [000000000000]; /* Filled in by U-Boot */
345 mal-device = <&MAL0>;
346 mal-tx-channel = <2>;
347 mal-rx-channel = <10>;
348 cell-index = <2>;
349 max-frame-size = <2328>;
350 rx-fifo-size = <1000>;
351 tx-fifo-size = <800>;
352 phy-mode = "rgmii";
353 phy-map = <00000000>;
354 rgmii-device = <&RGMII1>;
355 rgmii-channel = <0>;
356 has-inverted-stacr-oc;
357 has-new-stacr-staopc;
358 mdio-device = <&EMAC0>;
359 };
360
361 EMAC3: ethernet@ef601200 {
362 device_type = "network";
363 compatible = "ibm,emac-460gt", "ibm,emac4";
364 interrupt-parent = <&EMAC3>;
365 interrupts = <0 1>;
366 #interrupt-cells = <1>;
367 #address-cells = <0>;
368 #size-cells = <0>;
369 interrupt-map = </*Status*/ 0 &UIC2 13 4
370 /*Wake*/ 1 &UIC2 17 4>;
371 reg = <ef601200 70>;
372 local-mac-address = [000000000000]; /* Filled in by U-Boot */
373 mal-device = <&MAL0>;
374 mal-tx-channel = <3>;
375 mal-rx-channel = <18>;
376 cell-index = <3>;
377 max-frame-size = <2328>;
378 rx-fifo-size = <1000>;
379 tx-fifo-size = <800>;
380 phy-mode = "rgmii";
381 phy-map = <00000000>;
382 rgmii-device = <&RGMII1>;
383 rgmii-channel = <1>;
384 has-inverted-stacr-oc;
385 has-new-stacr-staopc;
386 mdio-device = <&EMAC0>;
387 };
388 };
389
390 PCIX0: pci@c0ec00000 {
391 device_type = "pci";
392 #interrupt-cells = <1>;
393 #size-cells = <2>;
394 #address-cells = <3>;
395 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
396 primary;
397 large-inbound-windows;
398 enable-msi-hole;
399 reg = <c 0ec00000 8 /* Config space access */
400 0 0 0 /* no IACK cycles */
401 c 0ed00000 4 /* Special cycles */
402 c 0ec80000 100 /* Internal registers */
403 c 0ec80100 fc>; /* Internal messaging registers */
404
405 /* Outbound ranges, one memory and one IO,
406 * later cannot be changed
407 */
408 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
409 01000000 0 00000000 0000000c 08000000 0 00010000>;
410
411 /* Inbound 2GB range starting at 0 */
412 dma-ranges = <42000000 0 0 0 0 0 80000000>;
413
414 /* This drives busses 0 to 0x3f */
415 bus-range = <0 3f>;
416
417 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
418 interrupt-map-mask = <0000 0 0 0>;
419 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
420 };
421
422 PCIE0: pciex@d00000000 {
423 device_type = "pci";
424 #interrupt-cells = <1>;
425 #size-cells = <2>;
426 #address-cells = <3>;
427 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
428 primary;
429 port = <0>; /* port number */
430 reg = <d 00000000 20000000 /* Config space access */
431 c 08010000 00001000>; /* Registers */
432 dcr-reg = <100 020>;
433 sdr-base = <300>;
434
435 /* Outbound ranges, one memory and one IO,
436 * later cannot be changed
437 */
438 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
439 01000000 0 00000000 0000000f 80000000 0 00010000>;
440
441 /* Inbound 2GB range starting at 0 */
442 dma-ranges = <42000000 0 0 0 0 0 80000000>;
443
444 /* This drives busses 40 to 0x7f */
445 bus-range = <40 7f>;
446
447 /* Legacy interrupts (note the weird polarity, the bridge seems
448 * to invert PCIe legacy interrupts).
449 * We are de-swizzling here because the numbers are actually for
450 * port of the root complex virtual P2P bridge. But I want
451 * to avoid putting a node for it in the tree, so the numbers
452 * below are basically de-swizzled numbers.
453 * The real slot is on idsel 0, so the swizzling is 1:1
454 */
455 interrupt-map-mask = <0000 0 0 7>;
456 interrupt-map = <
457 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
458 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
459 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
460 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
461 };
462
463 PCIE1: pciex@d20000000 {
464 device_type = "pci";
465 #interrupt-cells = <1>;
466 #size-cells = <2>;
467 #address-cells = <3>;
468 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
469 primary;
470 port = <1>; /* port number */
471 reg = <d 20000000 20000000 /* Config space access */
472 c 08011000 00001000>; /* Registers */
473 dcr-reg = <120 020>;
474 sdr-base = <340>;
475
476 /* Outbound ranges, one memory and one IO,
477 * later cannot be changed
478 */
479 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
480 01000000 0 00000000 0000000f 80010000 0 00010000>;
481
482 /* Inbound 2GB range starting at 0 */
483 dma-ranges = <42000000 0 0 0 0 0 80000000>;
484
485 /* This drives busses 80 to 0xbf */
486 bus-range = <80 bf>;
487
488 /* Legacy interrupts (note the weird polarity, the bridge seems
489 * to invert PCIe legacy interrupts).
490 * We are de-swizzling here because the numbers are actually for
491 * port of the root complex virtual P2P bridge. But I want
492 * to avoid putting a node for it in the tree, so the numbers
493 * below are basically de-swizzled numbers.
494 * The real slot is on idsel 0, so the swizzling is 1:1
495 */
496 interrupt-map-mask = <0000 0 0 7>;
497 interrupt-map = <
498 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
499 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
500 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
501 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
502 };
503 };
504 };
kernel source for telekom puls (alcatel/mediatek)