projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[POWERPC] 4xx: Add NOR FLASH entries to Canyonlands and Glacier dts
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / canyonlands.dts
1 /*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11 / {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "amcc,canyonlands";
15 compatible = "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 serial0 = &UART0;
22 serial1 = &UART1;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 model = "PowerPC,460EX";
32 reg = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>;
36 d-cache-line-size = <20>;
37 i-cache-size = <8000>;
38 d-cache-size = <8000>;
39 dcr-controller;
40 dcr-access-method = "native";
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0 0 0>; /* Filled in by U-Boot */
47 };
48
49 UIC0: interrupt-controller0 {
50 compatible = "ibm,uic-460ex","ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
53 dcr-reg = <0c0 009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
58
59 UIC1: interrupt-controller1 {
60 compatible = "ibm,uic-460ex","ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
63 dcr-reg = <0d0 009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */
68 interrupt-parent = <&UIC0>;
69 };
70
71 UIC2: interrupt-controller2 {
72 compatible = "ibm,uic-460ex","ibm,uic";
73 interrupt-controller;
74 cell-index = <2>;
75 dcr-reg = <0e0 009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
78 #interrupt-cells = <2>;
79 interrupts = <a 4 b 4>; /* cascade */
80 interrupt-parent = <&UIC0>;
81 };
82
83 UIC3: interrupt-controller3 {
84 compatible = "ibm,uic-460ex","ibm,uic";
85 interrupt-controller;
86 cell-index = <3>;
87 dcr-reg = <0f0 009>;
88 #address-cells = <0>;
89 #size-cells = <0>;
90 #interrupt-cells = <2>;
91 interrupts = <10 4 11 4>; /* cascade */
92 interrupt-parent = <&UIC0>;
93 };
94
95 SDR0: sdr {
96 compatible = "ibm,sdr-460ex";
97 dcr-reg = <00e 002>;
98 };
99
100 CPR0: cpr {
101 compatible = "ibm,cpr-460ex";
102 dcr-reg = <00c 002>;
103 };
104
105 plb {
106 compatible = "ibm,plb-460ex", "ibm,plb4";
107 #address-cells = <2>;
108 #size-cells = <1>;
109 ranges;
110 clock-frequency = <0>; /* Filled in by U-Boot */
111
112 SDRAM0: sdram {
113 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
114 dcr-reg = <010 2>;
115 };
116
117 MAL0: mcmal {
118 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
119 dcr-reg = <180 62>;
120 num-tx-chans = <2>;
121 num-rx-chans = <10>;
122 #address-cells = <0>;
123 #size-cells = <0>;
124 interrupt-parent = <&UIC2>;
125 interrupts = < /*TXEOB*/ 6 4
126 /*RXEOB*/ 7 4
127 /*SERR*/ 3 4
128 /*TXDE*/ 4 4
129 /*RXDE*/ 5 4>;
130 };
131
132 POB0: opb {
133 compatible = "ibm,opb-460ex", "ibm,opb";
134 #address-cells = <1>;
135 #size-cells = <1>;
136 ranges = <b0000000 4 b0000000 50000000>;
137 clock-frequency = <0>; /* Filled in by U-Boot */
138
139 EBC0: ebc {
140 compatible = "ibm,ebc-460ex", "ibm,ebc";
141 dcr-reg = <012 2>;
142 #address-cells = <2>;
143 #size-cells = <1>;
144 clock-frequency = <0>; /* Filled in by U-Boot */
145 /* ranges property is supplied by U-Boot */
146 interrupts = <6 4>;
147 interrupt-parent = <&UIC1>;
148
149 nor_flash@0,0 {
150 compatible = "amd,s29gl512n", "cfi-flash";
151 bank-width = <2>;
152 reg = <0 000000 4000000>;
153 #address-cells = <1>;
154 #size-cells = <1>;
155 partition@0 {
156 label = "kernel";
157 reg = <0 1e0000>;
158 };
159 partition@1e0000 {
160 label = "dtb";
161 reg = <1e0000 20000>;
162 };
163 partition@200000 {
164 label = "ramdisk";
165 reg = <200000 1400000>;
166 };
167 partition@1600000 {
168 label = "jffs2";
169 reg = <1600000 400000>;
170 };
171 partition@1a00000 {
172 label = "user";
173 reg = <1a00000 2560000>;
174 };
175 partition@3f60000 {
176 label = "env";
177 reg = <3f60000 40000>;
178 };
179 partition@3fa0000 {
180 label = "u-boot";
181 reg = <3fa0000 60000>;
182 };
183 };
184 };
185
186 UART0: serial@ef600300 {
187 device_type = "serial";
188 compatible = "ns16550";
189 reg = <ef600300 8>;
190 virtual-reg = <ef600300>;
191 clock-frequency = <0>; /* Filled in by U-Boot */
192 current-speed = <0>; /* Filled in by U-Boot */
193 interrupt-parent = <&UIC1>;
194 interrupts = <1 4>;
195 };
196
197 UART1: serial@ef600400 {
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <ef600400 8>;
201 virtual-reg = <ef600400>;
202 clock-frequency = <0>; /* Filled in by U-Boot */
203 current-speed = <0>; /* Filled in by U-Boot */
204 interrupt-parent = <&UIC0>;
205 interrupts = <1 4>;
206 };
207
208 UART2: serial@ef600500 {
209 device_type = "serial";
210 compatible = "ns16550";
211 reg = <ef600500 8>;
212 virtual-reg = <ef600500>;
213 clock-frequency = <0>; /* Filled in by U-Boot */
214 current-speed = <0>; /* Filled in by U-Boot */
215 interrupt-parent = <&UIC1>;
216 interrupts = <1d 4>;
217 };
218
219 UART3: serial@ef600600 {
220 device_type = "serial";
221 compatible = "ns16550";
222 reg = <ef600600 8>;
223 virtual-reg = <ef600600>;
224 clock-frequency = <0>; /* Filled in by U-Boot */
225 current-speed = <0>; /* Filled in by U-Boot */
226 interrupt-parent = <&UIC1>;
227 interrupts = <1e 4>;
228 };
229
230 IIC0: i2c@ef600700 {
231 compatible = "ibm,iic-460ex", "ibm,iic";
232 reg = <ef600700 14>;
233 interrupt-parent = <&UIC0>;
234 interrupts = <2 4>;
235 };
236
237 IIC1: i2c@ef600800 {
238 compatible = "ibm,iic-460ex", "ibm,iic";
239 reg = <ef600800 14>;
240 interrupt-parent = <&UIC0>;
241 interrupts = <3 4>;
242 };
243
244 ZMII0: emac-zmii@ef600d00 {
245 compatible = "ibm,zmii-460ex", "ibm,zmii";
246 reg = <ef600d00 c>;
247 };
248
249 RGMII0: emac-rgmii@ef601500 {
250 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
251 reg = <ef601500 8>;
252 has-mdio;
253 };
254
255 TAH0: emac-tah@ef601350 {
256 compatible = "ibm,tah-460ex", "ibm,tah";
257 reg = <ef601350 30>;
258 };
259
260 TAH1: emac-tah@ef601450 {
261 compatible = "ibm,tah-460ex", "ibm,tah";
262 reg = <ef601450 30>;
263 };
264
265 EMAC0: ethernet@ef600e00 {
266 device_type = "network";
267 compatible = "ibm,emac-460ex", "ibm,emac4";
268 interrupt-parent = <&EMAC0>;
269 interrupts = <0 1>;
270 #interrupt-cells = <1>;
271 #address-cells = <0>;
272 #size-cells = <0>;
273 interrupt-map = </*Status*/ 0 &UIC2 10 4
274 /*Wake*/ 1 &UIC2 14 4>;
275 reg = <ef600e00 70>;
276 local-mac-address = [000000000000]; /* Filled in by U-Boot */
277 mal-device = <&MAL0>;
278 mal-tx-channel = <0>;
279 mal-rx-channel = <0>;
280 cell-index = <0>;
281 max-frame-size = <2328>;
282 rx-fifo-size = <1000>;
283 tx-fifo-size = <800>;
284 phy-mode = "rgmii";
285 phy-map = <00000000>;
286 rgmii-device = <&RGMII0>;
287 rgmii-channel = <0>;
288 tah-device = <&TAH0>;
289 tah-channel = <0>;
290 has-inverted-stacr-oc;
291 has-new-stacr-staopc;
292 };
293
294 EMAC1: ethernet@ef600f00 {
295 device_type = "network";
296 compatible = "ibm,emac-460ex", "ibm,emac4";
297 interrupt-parent = <&EMAC1>;
298 interrupts = <0 1>;
299 #interrupt-cells = <1>;
300 #address-cells = <0>;
301 #size-cells = <0>;
302 interrupt-map = </*Status*/ 0 &UIC2 11 4
303 /*Wake*/ 1 &UIC2 15 4>;
304 reg = <ef600f00 70>;
305 local-mac-address = [000000000000]; /* Filled in by U-Boot */
306 mal-device = <&MAL0>;
307 mal-tx-channel = <1>;
308 mal-rx-channel = <8>;
309 cell-index = <1>;
310 max-frame-size = <2328>;
311 rx-fifo-size = <1000>;
312 tx-fifo-size = <800>;
313 phy-mode = "rgmii";
314 phy-map = <00000000>;
315 rgmii-device = <&RGMII0>;
316 rgmii-channel = <1>;
317 tah-device = <&TAH1>;
318 tah-channel = <1>;
319 has-inverted-stacr-oc;
320 has-new-stacr-staopc;
321 mdio-device = <&EMAC0>;
322 };
323 };
324
325 PCIX0: pci@c0ec00000 {
326 device_type = "pci";
327 #interrupt-cells = <1>;
328 #size-cells = <2>;
329 #address-cells = <3>;
330 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
331 primary;
332 large-inbound-windows;
333 enable-msi-hole;
334 reg = <c 0ec00000 8 /* Config space access */
335 0 0 0 /* no IACK cycles */
336 c 0ed00000 4 /* Special cycles */
337 c 0ec80000 100 /* Internal registers */
338 c 0ec80100 fc>; /* Internal messaging registers */
339
340 /* Outbound ranges, one memory and one IO,
341 * later cannot be changed
342 */
343 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
344 01000000 0 00000000 0000000c 08000000 0 00010000>;
345
346 /* Inbound 2GB range starting at 0 */
347 dma-ranges = <42000000 0 0 0 0 0 80000000>;
348
349 /* This drives busses 0 to 0x3f */
350 bus-range = <0 3f>;
351
352 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
353 interrupt-map-mask = <0000 0 0 0>;
354 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
355 };
356
357 PCIE0: pciex@d00000000 {
358 device_type = "pci";
359 #interrupt-cells = <1>;
360 #size-cells = <2>;
361 #address-cells = <3>;
362 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
363 primary;
364 port = <0>; /* port number */
365 reg = <d 00000000 20000000 /* Config space access */
366 c 08010000 00001000>; /* Registers */
367 dcr-reg = <100 020>;
368 sdr-base = <300>;
369
370 /* Outbound ranges, one memory and one IO,
371 * later cannot be changed
372 */
373 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
374 01000000 0 00000000 0000000f 80000000 0 00010000>;
375
376 /* Inbound 2GB range starting at 0 */
377 dma-ranges = <42000000 0 0 0 0 0 80000000>;
378
379 /* This drives busses 40 to 0x7f */
380 bus-range = <40 7f>;
381
382 /* Legacy interrupts (note the weird polarity, the bridge seems
383 * to invert PCIe legacy interrupts).
384 * We are de-swizzling here because the numbers are actually for
385 * port of the root complex virtual P2P bridge. But I want
386 * to avoid putting a node for it in the tree, so the numbers
387 * below are basically de-swizzled numbers.
388 * The real slot is on idsel 0, so the swizzling is 1:1
389 */
390 interrupt-map-mask = <0000 0 0 7>;
391 interrupt-map = <
392 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
393 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
394 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
395 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
396 };
397
398 PCIE1: pciex@d20000000 {
399 device_type = "pci";
400 #interrupt-cells = <1>;
401 #size-cells = <2>;
402 #address-cells = <3>;
403 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
404 primary;
405 port = <1>; /* port number */
406 reg = <d 20000000 20000000 /* Config space access */
407 c 08011000 00001000>; /* Registers */
408 dcr-reg = <120 020>;
409 sdr-base = <340>;
410
411 /* Outbound ranges, one memory and one IO,
412 * later cannot be changed
413 */
414 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
415 01000000 0 00000000 0000000f 80010000 0 00010000>;
416
417 /* Inbound 2GB range starting at 0 */
418 dma-ranges = <42000000 0 0 0 0 0 80000000>;
419
420 /* This drives busses 80 to 0xbf */
421 bus-range = <80 bf>;
422
423 /* Legacy interrupts (note the weird polarity, the bridge seems
424 * to invert PCIe legacy interrupts).
425 * We are de-swizzling here because the numbers are actually for
426 * port of the root complex virtual P2P bridge. But I want
427 * to avoid putting a node for it in the tree, so the numbers
428 * below are basically de-swizzled numbers.
429 * The real slot is on idsel 0, so the swizzling is 1:1
430 */
431 interrupt-map-mask = <0000 0 0 7>;
432 interrupt-map = <
433 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
434 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
435 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
436 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
437 };
438 };
439 };
kernel source for telekom puls (alcatel/mediatek)