arch/parisc/kernel/pci.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1997, 1998 Ralf Baechle
   7  * Copyright (C) 1999 SuSE GmbH
   8  * Copyright (C) 1999-2001 Hewlett-Packard Company
   9  * Copyright (C) 1999-2001 Grant Grundler
  10  */
  11 #include <linux/eisa.h>
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/slab.h>
  17 #include <linux/types.h>
  18
  19 #include <asm/io.h>
  20 #include <asm/system.h>
  21 #include <asm/superio.h>
  22
  23 #define DEBUG_RESOURCES 0
  24 #define DEBUG_CONFIG 0
  25
  26 #if DEBUG_CONFIG
  27 # define DBGC(x...)     printk(KERN_DEBUG x)
  28 #else
  29 # define DBGC(x...)
  30 #endif
  31
  32
  33 #if DEBUG_RESOURCES
  34 #define DBG_RES(x...)   printk(KERN_DEBUG x)
  35 #else
  36 #define DBG_RES(x...)
  37 #endif
  38
  39 /* To be used as: mdelay(pci_post_reset_delay);
  40  *
  41  * post_reset is the time the kernel should stall to prevent anyone from
  42  * accessing the PCI bus once #RESET is de-asserted.
  43  * PCI spec somewhere says 1 second but with multi-PCI bus systems,
  44  * this makes the boot time much longer than necessary.
  45  * 20ms seems to work for all the HP PCI implementations to date.
  46  *
  47  * #define pci_post_reset_delay 50
  48  */
  49
  50 struct pci_port_ops *pci_port __read_mostly;
  51 struct pci_bios_ops *pci_bios __read_mostly;
  52
  53 static int pci_hba_count __read_mostly;
  54
  55 /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data.  */
  56 #define PCI_HBA_MAX 32
  57 static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;
  58
  59
  60 /********************************************************************
  61 **
  62 ** I/O port space support
  63 **
  64 *********************************************************************/
  65
  66 /* EISA port numbers and PCI port numbers share the same interface.  Some
  67  * machines have both EISA and PCI adapters installed.  Rather than turn
  68  * pci_port into an array, we reserve bus 0 for EISA and call the EISA
  69  * routines if the access is to a port on bus 0.  We don't want to fix
  70  * EISA and ISA drivers which assume port space is <= 0xffff.
  71  */
  72
  73 #ifdef CONFIG_EISA
  74 #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
  75 #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
  76 #else
  77 #define EISA_IN(size)
  78 #define EISA_OUT(size)
  79 #endif
  80
  81 #define PCI_PORT_IN(type, size) \
  82 u##size in##type (int addr) \
  83 { \
  84         int b = PCI_PORT_HBA(addr); \
  85         EISA_IN(size); \
  86         if (!parisc_pci_hba[b]) return (u##size) -1; \
  87         return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
  88 } \
  89 EXPORT_SYMBOL(in##type);
  90
  91 PCI_PORT_IN(b,  8)
  92 PCI_PORT_IN(w, 16)
  93 PCI_PORT_IN(l, 32)
  94
  95
  96 #define PCI_PORT_OUT(type, size) \
  97 void out##type (u##size d, int addr) \
  98 { \
  99         int b = PCI_PORT_HBA(addr); \
 100         EISA_OUT(size); \
 101         if (!parisc_pci_hba[b]) return; \
 102         pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
 103 } \
 104 EXPORT_SYMBOL(out##type);
 105
 106 PCI_PORT_OUT(b,  8)
 107 PCI_PORT_OUT(w, 16)
 108 PCI_PORT_OUT(l, 32)
 109
 110
 111
 112 /*
 113  * BIOS32 replacement.
 114  */
 115 static int __init pcibios_init(void)
 116 {
 117         if (!pci_bios)
 118                 return -1;
 119
 120         if (pci_bios->init) {
 121                 pci_bios->init();
 122         } else {
 123                 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
 124         }
 125
 126         /* Set the CLS for PCI as early as possible. */
 127         pci_cache_line_size = pci_dfl_cache_line_size;
 128
 129         return 0;
 130 }
 131
 132
 133 /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
 134 void pcibios_fixup_bus(struct pci_bus *bus)
 135 {
 136         if (pci_bios->fixup_bus) {
 137                 pci_bios->fixup_bus(bus);
 138         } else {
 139                 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
 140         }
 141 }
 142
 143
 144 char *pcibios_setup(char *str)
 145 {
 146         return str;
 147 }
 148
 149 /*
 150  * Called by pci_set_master() - a driver interface.
 151  *
 152  * Legacy PDC guarantees to set:
 153  *      Map Memory BAR's into PA IO space.
 154  *      Map Expansion ROM BAR into one common PA IO space per bus.
 155  *      Map IO BAR's into PCI IO space.
 156  *      Command (see below)
 157  *      Cache Line Size
 158  *      Latency Timer
 159  *      Interrupt Line
 160  *      PPB: secondary latency timer, io/mmio base/limit,
 161  *              bus numbers, bridge control
 162  *
 163  */
 164 void pcibios_set_master(struct pci_dev *dev)
 165 {
 166         u8 lat;
 167
 168         /* If someone already mucked with this, don't touch it. */
 169         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 170         if (lat >= 16) return;
 171
 172         /*
 173         ** HP generally has fewer devices on the bus than other architectures.
 174         ** upper byte is PCI_LATENCY_TIMER.
 175         */
 176         pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
 177                               (0x80 << 8) | pci_cache_line_size);
 178 }
 179
 180
 181 void __init pcibios_init_bus(struct pci_bus *bus)
 182 {
 183         struct pci_dev *dev = bus->self;
 184         unsigned short bridge_ctl;
 185
 186         /* We deal only with pci controllers and pci-pci bridges. */
 187         if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 188                 return;
 189
 190         /* PCI-PCI bridge - set the cache line and default latency
 191            (32) for primary and secondary buses. */
 192         pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
 193
 194         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
 195         bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
 196         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
 197 }
 198
 199 /* called by drivers/pci/setup-bus.c:pci_setup_bridge().  */
 200 void __devinit pcibios_resource_to_bus(struct pci_dev *dev,
 201                 struct pci_bus_region *region, struct resource *res)
 202 {
 203 #ifdef CONFIG_64BIT
 204         struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
 205 #endif
 206
 207         if (res->flags & IORESOURCE_IO) {
 208                 /*
 209                 ** I/O space may see busnumbers here. Something
 210                 ** in the form of 0xbbxxxx where bb is the bus num
 211                 ** and xxxx is the I/O port space address.
 212                 ** Remaining address translation are done in the
 213                 ** PCI Host adapter specific code - ie dino_out8.
 214                 */
 215                 region->start = PCI_PORT_ADDR(res->start);
 216                 region->end   = PCI_PORT_ADDR(res->end);
 217         } else if (res->flags & IORESOURCE_MEM) {
 218                 /* Convert MMIO addr to PCI addr (undo global virtualization) */
 219                 region->start = PCI_BUS_ADDR(hba, res->start);
 220                 region->end   = PCI_BUS_ADDR(hba, res->end);
 221         }
 222
 223         DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n",
 224                 dev->bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM",
 225                 region->start, region->end);
 226 }
 227
 228 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 229                               struct pci_bus_region *region)
 230 {
 231 #ifdef CONFIG_64BIT
 232         struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
 233 #endif
 234
 235         if (res->flags & IORESOURCE_MEM) {
 236                 res->start = PCI_HOST_ADDR(hba, region->start);
 237                 res->end = PCI_HOST_ADDR(hba, region->end);
 238         }
 239
 240         if (res->flags & IORESOURCE_IO) {
 241                 res->start = region->start;
 242                 res->end = region->end;
 243         }
 244 }
 245
 246 #ifdef CONFIG_HOTPLUG
 247 EXPORT_SYMBOL(pcibios_resource_to_bus);
 248 EXPORT_SYMBOL(pcibios_bus_to_resource);
 249 #endif
 250
 251 /*
 252  * pcibios align resources() is called every time generic PCI code
 253  * wants to generate a new address. The process of looking for
 254  * an available address, each candidate is first "aligned" and
 255  * then checked if the resource is available until a match is found.
 256  *
 257  * Since we are just checking candidates, don't use any fields other
 258  * than res->start.
 259  */
 260 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 261                                 resource_size_t size, resource_size_t alignment)
 262 {
 263         resource_size_t mask, align, start = res->start;
 264
 265         DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
 266                 pci_name(((struct pci_dev *) data)),
 267                 res->parent, res->start, res->end,
 268                 (int) res->flags, size, alignment);
 269
 270         /* If it's not IO, then it's gotta be MEM */
 271         align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 272
 273         /* Align to largest of MIN or input size */
 274         mask = max(alignment, align) - 1;
 275         start += mask;
 276         start &= ~mask;
 277
 278         return start;
 279 }
 280
 281
 282 /*
 283  * A driver is enabling the device.  We make sure that all the appropriate
 284  * bits are set to allow the device to operate as the driver is expecting.
 285  * We enable the port IO and memory IO bits if the device has any BARs of
 286  * that type, and we enable the PERR and SERR bits unconditionally.
 287  * Drivers that do not need parity (eg graphics and possibly networking)
 288  * can clear these bits if they want.
 289  */
 290 int pcibios_enable_device(struct pci_dev *dev, int mask)
 291 {
 292         int err;
 293         u16 cmd, old_cmd;
 294
 295         err = pci_enable_resources(dev, mask);
 296         if (err < 0)
 297                 return err;
 298
 299         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 300         old_cmd = cmd;
 301
 302         cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
 303
 304 #if 0
 305         /* If bridge/bus controller has FBB enabled, child must too. */
 306         if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
 307                 cmd |= PCI_COMMAND_FAST_BACK;
 308 #endif
 309
 310         if (cmd != old_cmd) {
 311                 dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
 312                         old_cmd, cmd);
 313                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 314         }
 315         return 0;
 316 }
 317
 318
 319 /* PA-RISC specific */
 320 void pcibios_register_hba(struct pci_hba_data *hba)
 321 {
 322         if (pci_hba_count >= PCI_HBA_MAX) {
 323                 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
 324                 return;
 325         }
 326
 327         parisc_pci_hba[pci_hba_count] = hba;
 328         hba->hba_num = pci_hba_count++;
 329 }
 330
 331 subsys_initcall(pcibios_init);