arch/parisc/kernel/irq.c

   1 /*
   2  * Code to handle x86 style IRQs plus some generic interrupt stuff.
   3  *
   4  * Copyright (C) 1992 Linus Torvalds
   5  * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
   6  * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
   7  * Copyright (C) 1999-2000 Grant Grundler
   8  * Copyright (c) 2005 Matthew Wilcox
   9  *
  10  *    This program is free software; you can redistribute it and/or modify
  11  *    it under the terms of the GNU General Public License as published by
  12  *    the Free Software Foundation; either version 2, or (at your option)
  13  *    any later version.
  14  *
  15  *    This program is distributed in the hope that it will be useful,
  16  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *    GNU General Public License for more details.
  19  *
  20  *    You should have received a copy of the GNU General Public License
  21  *    along with this program; if not, write to the Free Software
  22  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24 #include <linux/bitops.h>
  25 #include <linux/config.h>
  26 #include <linux/errno.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/kernel_stat.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/types.h>
  33 #include <asm/io.h>
  34
  35 #include <asm/smp.h>
  36
  37 #undef PARISC_IRQ_CR16_COUNTS
  38
  39 extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
  40 extern irqreturn_t ipi_interrupt(int, void *, struct pt_regs *);
  41
  42 #define EIEM_MASK(irq)       (1UL<<(CPU_IRQ_MAX - irq))
  43
  44 /* Bits in EIEM correlate with cpu_irq_action[].
  45 ** Numbered *Big Endian*! (ie bit 0 is MSB)
  46 */
  47 static volatile unsigned long cpu_eiem = 0;
  48
  49 static void cpu_disable_irq(unsigned int irq)
  50 {
  51         unsigned long eirr_bit = EIEM_MASK(irq);
  52
  53         cpu_eiem &= ~eirr_bit;
  54         /* Do nothing on the other CPUs.  If they get this interrupt,
  55          * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
  56          * handle it, and the set_eiem() at the bottom will ensure it
  57          * then gets disabled */
  58 }
  59
  60 static void cpu_enable_irq(unsigned int irq)
  61 {
  62         unsigned long eirr_bit = EIEM_MASK(irq);
  63
  64         cpu_eiem |= eirr_bit;
  65
  66         /* FIXME: while our interrupts aren't nested, we cannot reset
  67          * the eiem mask if we're already in an interrupt.  Once we
  68          * implement nested interrupts, this can go away
  69          */
  70         if (!in_interrupt())
  71                 set_eiem(cpu_eiem);
  72
  73         /* This is just a simple NOP IPI.  But what it does is cause
  74          * all the other CPUs to do a set_eiem(cpu_eiem) at the end
  75          * of the interrupt handler */
  76         smp_send_all_nop();
  77 }
  78
  79 static unsigned int cpu_startup_irq(unsigned int irq)
  80 {
  81         cpu_enable_irq(irq);
  82         return 0;
  83 }
  84
  85 void no_ack_irq(unsigned int irq) { }
  86 void no_end_irq(unsigned int irq) { }
  87
  88 #ifdef CONFIG_SMP
  89 int cpu_check_affinity(unsigned int irq, cpumask_t *dest)
  90 {
  91         int cpu_dest;
  92
  93         /* timer and ipi have to always be received on all CPUs */
  94         if (irq == TIMER_IRQ || irq == IPI_IRQ) {
  95                 /* Bad linux design decision.  The mask has already
  96                  * been set; we must reset it */
  97                 irq_desc[irq].affinity = CPU_MASK_ALL;
  98                 return -EINVAL;
  99         }
 100
 101         /* whatever mask they set, we just allow one CPU */
 102         cpu_dest = first_cpu(*dest);
 103         *dest = cpumask_of_cpu(cpu_dest);
 104
 105         return 0;
 106 }
 107
 108 static void cpu_set_affinity_irq(unsigned int irq, cpumask_t dest)
 109 {
 110         if (cpu_check_affinity(irq, &dest))
 111                 return;
 112
 113         irq_desc[irq].affinity = dest;
 114 }
 115 #endif
 116
 117 static struct hw_interrupt_type cpu_interrupt_type = {
 118         .typename       = "CPU",
 119         .startup        = cpu_startup_irq,
 120         .shutdown       = cpu_disable_irq,
 121         .enable         = cpu_enable_irq,
 122         .disable        = cpu_disable_irq,
 123         .ack            = no_ack_irq,
 124         .end            = no_end_irq,
 125 #ifdef CONFIG_SMP
 126         .set_affinity   = cpu_set_affinity_irq,
 127 #endif
 128         /* XXX: Needs to be written.  We managed without it so far, but
 129          * we really ought to write it.
 130          */
 131         .retrigger      = NULL,
 132 };
 133
 134 int show_interrupts(struct seq_file *p, void *v)
 135 {
 136         int i = *(loff_t *) v, j;
 137         unsigned long flags;
 138
 139         if (i == 0) {
 140                 seq_puts(p, "    ");
 141                 for_each_online_cpu(j)
 142                         seq_printf(p, "       CPU%d", j);
 143
 144 #ifdef PARISC_IRQ_CR16_COUNTS
 145                 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
 146 #endif
 147                 seq_putc(p, '\n');
 148         }
 149
 150         if (i < NR_IRQS) {
 151                 struct irqaction *action;
 152
 153                 spin_lock_irqsave(&irq_desc[i].lock, flags);
 154                 action = irq_desc[i].action;
 155                 if (!action)
 156                         goto skip;
 157                 seq_printf(p, "%3d: ", i);
 158 #ifdef CONFIG_SMP
 159                 for_each_online_cpu(j)
 160                         seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
 161 #else
 162                 seq_printf(p, "%10u ", kstat_irqs(i));
 163 #endif
 164
 165                 seq_printf(p, " %14s", irq_desc[i].chip->typename);
 166 #ifndef PARISC_IRQ_CR16_COUNTS
 167                 seq_printf(p, "  %s", action->name);
 168
 169                 while ((action = action->next))
 170                         seq_printf(p, ", %s", action->name);
 171 #else
 172                 for ( ;action; action = action->next) {
 173                         unsigned int k, avg, min, max;
 174
 175                         min = max = action->cr16_hist[0];
 176
 177                         for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
 178                                 int hist = action->cr16_hist[k];
 179
 180                                 if (hist) {
 181                                         avg += hist;
 182                                 } else
 183                                         break;
 184
 185                                 if (hist > max) max = hist;
 186                                 if (hist < min) min = hist;
 187                         }
 188
 189                         avg /= k;
 190                         seq_printf(p, " %s[%d/%d/%d]", action->name,
 191                                         min,avg,max);
 192                 }
 193 #endif
 194
 195                 seq_putc(p, '\n');
 196  skip:
 197                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 198         }
 199
 200         return 0;
 201 }
 202
 203
 204
 205 /*
 206 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
 207 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
 208 **
 209 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
 210 ** Then use that to get the Transaction address and data.
 211 */
 212
 213 int cpu_claim_irq(unsigned int irq, struct hw_interrupt_type *type, void *data)
 214 {
 215         if (irq_desc[irq].action)
 216                 return -EBUSY;
 217         if (irq_desc[irq].chip != &cpu_interrupt_type)
 218                 return -EBUSY;
 219
 220         if (type) {
 221                 irq_desc[irq].chip = type;
 222                 irq_desc[irq].chip_data = data;
 223                 cpu_interrupt_type.enable(irq);
 224         }
 225         return 0;
 226 }
 227
 228 int txn_claim_irq(int irq)
 229 {
 230         return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
 231 }
 232
 233 /*
 234  * The bits_wide parameter accommodates the limitations of the HW/SW which
 235  * use these bits:
 236  * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
 237  * V-class (EPIC):          6 bits
 238  * N/L/A-class (iosapic):   8 bits
 239  * PCI 2.2 MSI:            16 bits
 240  * Some PCI devices:       32 bits (Symbios SCSI/ATM/HyperFabric)
 241  *
 242  * On the service provider side:
 243  * o PA 1.1 (and PA2.0 narrow mode)     5-bits (width of EIR register)
 244  * o PA 2.0 wide mode                   6-bits (per processor)
 245  * o IA64                               8-bits (0-256 total)
 246  *
 247  * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
 248  * by the processor...and the N/L-class I/O subsystem supports more bits than
 249  * PA2.0 has. The first case is the problem.
 250  */
 251 int txn_alloc_irq(unsigned int bits_wide)
 252 {
 253         int irq;
 254
 255         /* never return irq 0 cause that's the interval timer */
 256         for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
 257                 if (cpu_claim_irq(irq, NULL, NULL) < 0)
 258                         continue;
 259                 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
 260                         continue;
 261                 return irq;
 262         }
 263
 264         /* unlikely, but be prepared */
 265         return -1;
 266 }
 267
 268
 269 unsigned long txn_affinity_addr(unsigned int irq, int cpu)
 270 {
 271 #ifdef CONFIG_SMP
 272         irq_desc[irq].affinity = cpumask_of_cpu(cpu);
 273 #endif
 274
 275         return cpu_data[cpu].txn_addr;
 276 }
 277
 278
 279 unsigned long txn_alloc_addr(unsigned int virt_irq)
 280 {
 281         static int next_cpu = -1;
 282
 283         next_cpu++; /* assign to "next" CPU we want this bugger on */
 284
 285         /* validate entry */
 286         while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr ||
 287                 !cpu_online(next_cpu)))
 288                 next_cpu++;
 289
 290         if (next_cpu >= NR_CPUS)
 291                 next_cpu = 0;   /* nothing else, assign monarch */
 292
 293         return txn_affinity_addr(virt_irq, next_cpu);
 294 }
 295
 296
 297 unsigned int txn_alloc_data(unsigned int virt_irq)
 298 {
 299         return virt_irq - CPU_IRQ_BASE;
 300 }
 301
 302 /* ONLY called from entry.S:intr_extint() */
 303 void do_cpu_irq_mask(struct pt_regs *regs)
 304 {
 305         unsigned long eirr_val;
 306
 307         irq_enter();
 308
 309         /*
 310          * Don't allow TIMER or IPI nested interrupts.
 311          * Allowing any single interrupt to nest can lead to that CPU
 312          * handling interrupts with all enabled interrupts unmasked.
 313          */
 314         set_eiem(0UL);
 315
 316         /* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
 317          * 2) We loop here on EIRR contents in order to avoid
 318          *    nested interrupts or having to take another interrupt
 319          *    when we could have just handled it right away.
 320          */
 321         for (;;) {
 322                 unsigned long bit = (1UL << (BITS_PER_LONG - 1));
 323                 unsigned int irq;
 324                 eirr_val = mfctl(23) & cpu_eiem;
 325                 if (!eirr_val)
 326                         break;
 327
 328                 mtctl(eirr_val, 23); /* reset bits we are going to process */
 329
 330                 /* Work our way from MSb to LSb...same order we alloc EIRs */
 331                 for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {
 332 #ifdef CONFIG_SMP
 333                         cpumask_t dest = irq_desc[irq].affinity;
 334 #endif
 335                         if (!(bit & eirr_val))
 336                                 continue;
 337
 338                         /* clear bit in mask - can exit loop sooner */
 339                         eirr_val &= ~bit;
 340
 341 #ifdef CONFIG_SMP
 342                         /* FIXME: because generic set affinity mucks
 343                          * with the affinity before sending it to us
 344                          * we can get the situation where the affinity is
 345                          * wrong for our CPU type interrupts */
 346                         if (irq != TIMER_IRQ && irq != IPI_IRQ &&
 347                             !cpu_isset(smp_processor_id(), dest)) {
 348                                 int cpu = first_cpu(dest);
 349
 350                                 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
 351                                        irq, smp_processor_id(), cpu);
 352                                 gsc_writel(irq + CPU_IRQ_BASE,
 353                                            cpu_data[cpu].hpa);
 354                                 continue;
 355                         }
 356 #endif
 357
 358                         __do_IRQ(irq, regs);
 359                 }
 360         }
 361
 362         set_eiem(cpu_eiem);     /* restore original mask */
 363         irq_exit();
 364 }
 365
 366
 367 static struct irqaction timer_action = {
 368         .handler = timer_interrupt,
 369         .name = "timer",
 370         .flags = SA_INTERRUPT,
 371 };
 372
 373 #ifdef CONFIG_SMP
 374 static struct irqaction ipi_action = {
 375         .handler = ipi_interrupt,
 376         .name = "IPI",
 377         .flags = SA_INTERRUPT,
 378 };
 379 #endif
 380
 381 static void claim_cpu_irqs(void)
 382 {
 383         int i;
 384         for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
 385                 irq_desc[i].chip = &cpu_interrupt_type;
 386         }
 387
 388         irq_desc[TIMER_IRQ].action = &timer_action;
 389         irq_desc[TIMER_IRQ].status |= IRQ_PER_CPU;
 390 #ifdef CONFIG_SMP
 391         irq_desc[IPI_IRQ].action = &ipi_action;
 392         irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
 393 #endif
 394 }
 395
 396 void __init init_IRQ(void)
 397 {
 398         local_irq_disable();    /* PARANOID - should already be disabled */
 399         mtctl(~0UL, 23);        /* EIRR : clear all pending external intr */
 400         claim_cpu_irqs();
 401 #ifdef CONFIG_SMP
 402         if (!cpu_eiem)
 403                 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
 404 #else
 405         cpu_eiem = EIEM_MASK(TIMER_IRQ);
 406 #endif
 407         set_eiem(cpu_eiem);     /* EIEM : enable all external intr */
 408
 409 }
 410
 411 void ack_bad_irq(unsigned int irq)
 412 {
 413         printk("unexpected IRQ %d\n", irq);
 414 }