mn10300: move setup_jiffies_interrupt() to cevt-mn10300.c
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mn10300 / unit-asb2364 / include / unit / timex.h
1 /* timex.h: MN2WS0038 architecture timer specifications
2 *
3 * Copyright (C) 2002, 2010 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11 #ifndef _ASM_UNIT_TIMEX_H
12 #define _ASM_UNIT_TIMEX_H
13
14 #include <asm/timer-regs.h>
15 #include <unit/clock.h>
16 #include <asm/param.h>
17
18 /*
19 * jiffies counter specifications
20 */
21
22 #define TMJCBR_MAX 0xffffff /* 24bit */
23 #define TMJCIRQ TMTIRQ
24
25 #ifndef __ASSEMBLY__
26
27 #define MN10300_SRC_IOBCLK MN10300_IOBCLK
28
29 #ifndef HZ
30 # error HZ undeclared.
31 #endif /* !HZ */
32
33 #define MN10300_JCCLK (MN10300_SRC_IOBCLK)
34 #define MN10300_TSCCLK (MN10300_SRC_IOBCLK)
35
36 #define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ)
37 #define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ)
38
39 /* Check bit width of MTM interval value that sets base register */
40 #if (MN10300_JC_PER_HZ - 1) > TMJCBR_MAX
41 # error MTM tick timer interval value is overflow.
42 #endif
43
44 static inline void stop_jiffies_counter(void)
45 {
46 u16 tmp;
47 TMTMD = 0;
48 tmp = TMTMD;
49 }
50
51 static inline void reload_jiffies_counter(u32 cnt)
52 {
53 u32 tmp;
54
55 TMTBR = cnt;
56 tmp = TMTBR;
57
58 TMTMD = TMTMD_TMTLDE;
59 TMTMD = TMTMD_TMTCNE;
60 tmp = TMTMD;
61 }
62
63 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS) && \
64 !defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
65 /*
66 * If we aren't using broadcasting, each core needs its own event timer.
67 * Since CPU0 uses the tick timer which is 24-bits, we use timer 4 & 5
68 * cascaded to 32-bits for CPU1 (but only really use 24-bits to match
69 * CPU0).
70 */
71
72 #define TMJC1IRQ TM5IRQ
73
74 static inline void stop_jiffies_counter1(void)
75 {
76 u8 tmp;
77 TM4MD = 0;
78 TM5MD = 0;
79 tmp = TM4MD;
80 tmp = TM5MD;
81 }
82
83 static inline void reload_jiffies_counter1(u32 cnt)
84 {
85 u32 tmp;
86
87 TM45BR = cnt;
88 tmp = TM45BR;
89
90 TM4MD = TM4MD_INIT_COUNTER;
91 tmp = TM4MD;
92
93 TM5MD = TM5MD_SRC_TM4CASCADE | TM5MD_INIT_COUNTER;
94 TM5MD = TM5MD_SRC_TM4CASCADE | TM5MD_COUNT_ENABLE;
95 tmp = TM5MD;
96
97 TM4MD = TM4MD_COUNT_ENABLE;
98 tmp = TM4MD;
99 }
100 #endif /* CONFIG_SMP&GENERIC_CLOCKEVENTS&!GENERIC_CLOCKEVENTS_BROADCAST */
101
102 #endif /* !__ASSEMBLY__ */
103
104
105 /*
106 * timestamp counter specifications
107 */
108 #define TMTSCBR_MAX 0xffffffff
109
110 #ifndef __ASSEMBLY__
111
112 /* Use 32-bit timestamp counter */
113 #define TMTSCMD TMSMD
114 #define TMTSCBR TMSBR
115 #define TMTSCBC TMSBC
116 #define TMTSCICR TMSICR
117
118 static inline void startup_timestamp_counter(void)
119 {
120 u32 sync;
121
122 /* set up TMS(Timestamp) 32bit timer register to count real time
123 * - count down from 4Gig-1 to 0 and wrap at IOBCLK rate
124 */
125
126 TMTSCBR = TMTSCBR_MAX;
127 sync = TMTSCBR;
128
129 TMTSCICR = 0;
130 sync = TMTSCICR;
131
132 TMTSCMD = TMTMD_TMTLDE;
133 TMTSCMD = TMTMD_TMTCNE;
134 sync = TMTSCMD;
135 }
136
137 static inline void shutdown_timestamp_counter(void)
138 {
139 TMTSCMD = 0;
140 }
141
142 /*
143 * we use a cascaded pair of 16-bit down-counting timers to count I/O
144 * clock cycles for the purposes of time keeping
145 */
146 typedef unsigned long cycles_t;
147
148 static inline cycles_t read_timestamp_counter(void)
149 {
150 return (cycles_t)~TMTSCBC;
151 }
152
153 #endif /* !__ASSEMBLY__ */
154
155 #endif /* _ASM_UNIT_TIMEX_H */