arch/mips/sibyte/bcm1480/irq.c

   1 /*
   2  * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/smp.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/mm.h>
  25 #include <linux/kernel_stat.h>
  26
  27 #include <asm/errno.h>
  28 #include <asm/irq_regs.h>
  29 #include <asm/signal.h>
  30 #include <asm/system.h>
  31 #include <asm/io.h>
  32
  33 #include <asm/sibyte/bcm1480_regs.h>
  34 #include <asm/sibyte/bcm1480_int.h>
  35 #include <asm/sibyte/bcm1480_scd.h>
  36
  37 #include <asm/sibyte/sb1250_uart.h>
  38 #include <asm/sibyte/sb1250.h>
  39
  40 /*
  41  * These are the routines that handle all the low level interrupt stuff.
  42  * Actions handled here are: initialization of the interrupt map, requesting of
  43  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  44  * for interrupt lines
  45  */
  46
  47
  48 static void end_bcm1480_irq(unsigned int irq);
  49 static void enable_bcm1480_irq(unsigned int irq);
  50 static void disable_bcm1480_irq(unsigned int irq);
  51 static void ack_bcm1480_irq(unsigned int irq);
  52 #ifdef CONFIG_SMP
  53 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask);
  54 #endif
  55
  56 #ifdef CONFIG_PCI
  57 extern unsigned long ht_eoi_space;
  58 #endif
  59
  60 static struct irq_chip bcm1480_irq_type = {
  61         .name = "BCM1480-IMR",
  62         .ack = ack_bcm1480_irq,
  63         .mask = disable_bcm1480_irq,
  64         .mask_ack = ack_bcm1480_irq,
  65         .unmask = enable_bcm1480_irq,
  66         .end = end_bcm1480_irq,
  67 #ifdef CONFIG_SMP
  68         .set_affinity = bcm1480_set_affinity
  69 #endif
  70 };
  71
  72 /* Store the CPU id (not the logical number) */
  73 int bcm1480_irq_owner[BCM1480_NR_IRQS];
  74
  75 static DEFINE_RAW_SPINLOCK(bcm1480_imr_lock);
  76
  77 void bcm1480_mask_irq(int cpu, int irq)
  78 {
  79         unsigned long flags, hl_spacing;
  80         u64 cur_ints;
  81
  82         raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
  83         hl_spacing = 0;
  84         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
  85                 hl_spacing = BCM1480_IMR_HL_SPACING;
  86                 irq -= BCM1480_NR_IRQS_HALF;
  87         }
  88         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
  89         cur_ints |= (((u64) 1) << irq);
  90         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
  91         raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
  92 }
  93
  94 void bcm1480_unmask_irq(int cpu, int irq)
  95 {
  96         unsigned long flags, hl_spacing;
  97         u64 cur_ints;
  98
  99         raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
 100         hl_spacing = 0;
 101         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
 102                 hl_spacing = BCM1480_IMR_HL_SPACING;
 103                 irq -= BCM1480_NR_IRQS_HALF;
 104         }
 105         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 106         cur_ints &= ~(((u64) 1) << irq);
 107         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
 108         raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 109 }
 110
 111 #ifdef CONFIG_SMP
 112 static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
 113 {
 114         int i = 0, old_cpu, cpu, int_on, k;
 115         u64 cur_ints;
 116         unsigned long flags;
 117         unsigned int irq_dirty;
 118
 119         i = cpumask_first(mask);
 120
 121         /* Convert logical CPU to physical CPU */
 122         cpu = cpu_logical_map(i);
 123
 124         /* Protect against other affinity changers and IMR manipulation */
 125         raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
 126
 127         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 128         old_cpu = bcm1480_irq_owner[irq];
 129         irq_dirty = irq;
 130         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
 131                 irq_dirty -= BCM1480_NR_IRQS_HALF;
 132         }
 133
 134         for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
 135                 cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 136                 int_on = !(cur_ints & (((u64) 1) << irq_dirty));
 137                 if (int_on) {
 138                         /* If it was on, mask it */
 139                         cur_ints |= (((u64) 1) << irq_dirty);
 140                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 141                 }
 142                 bcm1480_irq_owner[irq] = cpu;
 143                 if (int_on) {
 144                         /* unmask for the new CPU */
 145                         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 146                         cur_ints &= ~(((u64) 1) << irq_dirty);
 147                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
 148                 }
 149         }
 150         raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 151
 152         return 0;
 153 }
 154 #endif
 155
 156
 157 /*****************************************************************************/
 158
 159 static void disable_bcm1480_irq(unsigned int irq)
 160 {
 161         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
 162 }
 163
 164 static void enable_bcm1480_irq(unsigned int irq)
 165 {
 166         bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 167 }
 168
 169
 170 static void ack_bcm1480_irq(unsigned int irq)
 171 {
 172         u64 pending;
 173         unsigned int irq_dirty;
 174         int k;
 175
 176         /*
 177          * If the interrupt was an HT interrupt, now is the time to
 178          * clear it.  NOTE: we assume the HT bridge was set up to
 179          * deliver the interrupts to all CPUs (which makes affinity
 180          * changing easier for us)
 181          */
 182         irq_dirty = irq;
 183         if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
 184                 irq_dirty -= BCM1480_NR_IRQS_HALF;
 185         }
 186         for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
 187                 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
 188                                                 R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
 189                 pending &= ((u64)1 << (irq_dirty));
 190                 if (pending) {
 191 #ifdef CONFIG_SMP
 192                         int i;
 193                         for (i=0; i<NR_CPUS; i++) {
 194                                 /*
 195                                  * Clear for all CPUs so an affinity switch
 196                                  * doesn't find an old status
 197                                  */
 198                                 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
 199                                                                 R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
 200                         }
 201 #else
 202                         __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
 203 #endif
 204
 205                         /*
 206                          * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 207                          * Pass 2, the LDT world may be edge-triggered, but
 208                          * this EOI shouldn't hurt.  If they are
 209                          * level-sensitive, the EOI is required.
 210                          */
 211 #ifdef CONFIG_PCI
 212                         if (ht_eoi_space)
 213                                 *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
 214 #endif
 215                 }
 216         }
 217         bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
 218 }
 219
 220
 221 static void end_bcm1480_irq(unsigned int irq)
 222 {
 223         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 224                 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
 225         }
 226 }
 227
 228
 229 void __init init_bcm1480_irqs(void)
 230 {
 231         int i;
 232
 233         for (i = 0; i < BCM1480_NR_IRQS; i++) {
 234                 set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
 235                 bcm1480_irq_owner[i] = 0;
 236         }
 237 }
 238
 239 /*
 240  *  init_IRQ is called early in the boot sequence from init/main.c.  It
 241  *  is responsible for setting up the interrupt mapper and installing the
 242  *  handler that will be responsible for dispatching interrupts to the
 243  *  "right" place.
 244  */
 245 /*
 246  * For now, map all interrupts to IP[2].  We could save
 247  * some cycles by parceling out system interrupts to different
 248  * IP lines, but keep it simple for bringup.  We'll also direct
 249  * all interrupts to a single CPU; we should probably route
 250  * PCI and LDT to one cpu and everything else to the other
 251  * to balance the load a bit.
 252  *
 253  * On the second cpu, everything is set to IP5, which is
 254  * ignored, EXCEPT the mailbox interrupt.  That one is
 255  * set to IP[2] so it is handled.  This is needed so we
 256  * can do cross-cpu function calls, as requred by SMP
 257  */
 258
 259 #define IMR_IP2_VAL     K_BCM1480_INT_MAP_I0
 260 #define IMR_IP3_VAL     K_BCM1480_INT_MAP_I1
 261 #define IMR_IP4_VAL     K_BCM1480_INT_MAP_I2
 262 #define IMR_IP5_VAL     K_BCM1480_INT_MAP_I3
 263 #define IMR_IP6_VAL     K_BCM1480_INT_MAP_I4
 264
 265 void __init arch_init_irq(void)
 266 {
 267         unsigned int i, cpu;
 268         u64 tmp;
 269         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 270                 STATUSF_IP1 | STATUSF_IP0;
 271
 272         /* Default everything to IP2 */
 273         /* Start with _high registers which has no bit 0 interrupt source */
 274         for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) {    /* was I0 */
 275                 for (cpu = 0; cpu < 4; cpu++) {
 276                         __raw_writeq(IMR_IP2_VAL,
 277                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
 278                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
 279                 }
 280         }
 281
 282         /* Now do _low registers */
 283         for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
 284                 for (cpu = 0; cpu < 4; cpu++) {
 285                         __raw_writeq(IMR_IP2_VAL,
 286                                      IOADDR(A_BCM1480_IMR_REGISTER(cpu,
 287                                                                    R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
 288                 }
 289         }
 290
 291         init_bcm1480_irqs();
 292
 293         /*
 294          * Map the high 16 bits of mailbox_0 registers to IP[3], for
 295          * inter-cpu messages
 296          */
 297         /* Was I1 */
 298         for (cpu = 0; cpu < 4; cpu++) {
 299                 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
 300                                                  (K_BCM1480_INT_MBOX_0_0 << 3)));
 301         }
 302
 303
 304         /* Clear the mailboxes.  The firmware may leave them dirty */
 305         for (cpu = 0; cpu < 4; cpu++) {
 306                 __raw_writeq(0xffffffffffffffffULL,
 307                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
 308                 __raw_writeq(0xffffffffffffffffULL,
 309                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
 310         }
 311
 312
 313         /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
 314         tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
 315         for (cpu = 0; cpu < 4; cpu++) {
 316                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
 317         }
 318         tmp = ~((u64) 0);
 319         for (cpu = 0; cpu < 4; cpu++) {
 320                 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
 321         }
 322
 323         /*
 324          * Note that the timer interrupts are also mapped, but this is
 325          * done in bcm1480_time_init().  Also, the profiling driver
 326          * does its own management of IP7.
 327          */
 328
 329         /* Enable necessary IPs, disable the rest */
 330         change_c0_status(ST0_IM, imask);
 331 }
 332
 333 extern void bcm1480_mailbox_interrupt(void);
 334
 335 static inline void dispatch_ip2(void)
 336 {
 337         unsigned long long mask_h, mask_l;
 338         unsigned int cpu = smp_processor_id();
 339         unsigned long base;
 340
 341         /*
 342          * Default...we've hit an IP[2] interrupt, which means we've got to
 343          * check the 1480 interrupt registers to figure out what to do.  Need
 344          * to detect which CPU we're on, now that smp_affinity is supported.
 345          */
 346         base = A_BCM1480_IMR_MAPPER(cpu);
 347         mask_h = __raw_readq(
 348                 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
 349         mask_l = __raw_readq(
 350                 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
 351
 352         if (mask_h) {
 353                 if (mask_h ^ 1)
 354                         do_IRQ(fls64(mask_h) - 1);
 355                 else if (mask_l)
 356                         do_IRQ(63 + fls64(mask_l));
 357         }
 358 }
 359
 360 asmlinkage void plat_irq_dispatch(void)
 361 {
 362         unsigned int cpu = smp_processor_id();
 363         unsigned int pending;
 364
 365 #ifdef CONFIG_SIBYTE_BCM1480_PROF
 366         /* Set compare to count to silence count/compare timer interrupts */
 367         write_c0_compare(read_c0_count());
 368 #endif
 369
 370         pending = read_c0_cause() & read_c0_status();
 371
 372 #ifdef CONFIG_SIBYTE_BCM1480_PROF
 373         if (pending & CAUSEF_IP7)       /* Cpu performance counter interrupt */
 374                 sbprof_cpu_intr();
 375         else
 376 #endif
 377
 378         if (pending & CAUSEF_IP4)
 379                 do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
 380 #ifdef CONFIG_SMP
 381         else if (pending & CAUSEF_IP3)
 382                 bcm1480_mailbox_interrupt();
 383 #endif
 384
 385         else if (pending & CAUSEF_IP2)
 386                 dispatch_ip2();
 387 }