arch/mips/pci/pci-alchemy.c

   1 /*
   2  * Alchemy PCI host mode support.
   3  *
   4  * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
   5  * Author: MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * Support for all devices (greater than 16) added by David Gathright.
   8  */
   9
  10 #include <linux/export.h>
  11 #include <linux/types.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/vmalloc.h>
  17
  18 #include <asm/mach-au1x00/au1000.h>
  19
  20 #ifdef CONFIG_DEBUG_PCI
  21 #define DBG(x...) printk(KERN_DEBUG x)
  22 #else
  23 #define DBG(x...) do {} while (0)
  24 #endif
  25
  26 #define PCI_ACCESS_READ         0
  27 #define PCI_ACCESS_WRITE        1
  28
  29 struct alchemy_pci_context {
  30         struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
  31         void __iomem *regs;                     /* ctrl base */
  32         /* tools for wired entry for config space access */
  33         unsigned long last_elo0;
  34         unsigned long last_elo1;
  35         int wired_entry;
  36         struct vm_struct *pci_cfg_vm;
  37
  38         unsigned long pm[12];
  39
  40         int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
  41         int (*board_pci_idsel)(unsigned int devsel, int assert);
  42 };
  43
  44 /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
  45  * in arch/mips/alchemy/common/setup.c
  46  */
  47 static struct resource alchemy_pci_def_memres = {
  48         .start  = ALCHEMY_PCI_MEMWIN_START,
  49         .end    = ALCHEMY_PCI_MEMWIN_END,
  50         .name   = "PCI memory space",
  51         .flags  = IORESOURCE_MEM
  52 };
  53
  54 static struct resource alchemy_pci_def_iores = {
  55         .start  = ALCHEMY_PCI_IOWIN_START,
  56         .end    = ALCHEMY_PCI_IOWIN_END,
  57         .name   = "PCI IO space",
  58         .flags  = IORESOURCE_IO
  59 };
  60
  61 static void mod_wired_entry(int entry, unsigned long entrylo0,
  62                 unsigned long entrylo1, unsigned long entryhi,
  63                 unsigned long pagemask)
  64 {
  65         unsigned long old_pagemask;
  66         unsigned long old_ctx;
  67
  68         /* Save old context and create impossible VPN2 value */
  69         old_ctx = read_c0_entryhi() & 0xff;
  70         old_pagemask = read_c0_pagemask();
  71         write_c0_index(entry);
  72         write_c0_pagemask(pagemask);
  73         write_c0_entryhi(entryhi);
  74         write_c0_entrylo0(entrylo0);
  75         write_c0_entrylo1(entrylo1);
  76         tlb_write_indexed();
  77         write_c0_entryhi(old_ctx);
  78         write_c0_pagemask(old_pagemask);
  79 }
  80
  81 static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx)
  82 {
  83         ctx->wired_entry = read_c0_wired();
  84         add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
  85         ctx->last_elo0 = ctx->last_elo1 = ~0;
  86 }
  87
  88 static int config_access(unsigned char access_type, struct pci_bus *bus,
  89                          unsigned int dev_fn, unsigned char where, u32 *data)
  90 {
  91         struct alchemy_pci_context *ctx = bus->sysdata;
  92         unsigned int device = PCI_SLOT(dev_fn);
  93         unsigned int function = PCI_FUNC(dev_fn);
  94         unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r;
  95         int error = PCIBIOS_SUCCESSFUL;
  96
  97         if (device > 19) {
  98                 *data = 0xffffffff;
  99                 return -1;
 100         }
 101
 102         /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
 103          * on resume, clearing our wired entry.  Unfortunately the ->resume()
 104          * callback is called way way way too late (and ->suspend() too early)
 105          * to have them destroy and recreate it.  Instead just test if c0_wired
 106          * is now lower than the index we retrieved before suspending and then
 107          * recreate the entry if necessary.  Of course this is totally bonkers
 108          * and breaks as soon as someone else adds another wired entry somewhere
 109          * else.  Anyone have any ideas how to handle this better?
 110          */
 111         if (unlikely(read_c0_wired() < ctx->wired_entry))
 112                 alchemy_pci_wired_entry(ctx);
 113
 114         local_irq_save(flags);
 115         r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
 116         r |= PCI_STATCMD_STATUS(0x2000);
 117         __raw_writel(r, ctx->regs + PCI_REG_STATCMD);
 118         wmb();
 119
 120         /* Allow board vendors to implement their own off-chip IDSEL.
 121          * If it doesn't succeed, may as well bail out at this point.
 122          */
 123         if (ctx->board_pci_idsel(device, 1) == 0) {
 124                 *data = 0xffffffff;
 125                 local_irq_restore(flags);
 126                 return -1;
 127         }
 128
 129         /* Setup the config window */
 130         if (bus->number == 0)
 131                 cfg_base = (1 << device) << 11;
 132         else
 133                 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
 134
 135         /* Setup the lower bits of the 36-bit address */
 136         offset = (function << 8) | (where & ~0x3);
 137         /* Pick up any address that falls below the page mask */
 138         offset |= cfg_base & ~PAGE_MASK;
 139
 140         /* Page boundary */
 141         cfg_base = cfg_base & PAGE_MASK;
 142
 143         /* To improve performance, if the current device is the same as
 144          * the last device accessed, we don't touch the TLB.
 145          */
 146         entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
 147         entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
 148         if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) {
 149                 mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1,
 150                                 (unsigned long)ctx->pci_cfg_vm->addr, PM_4K);
 151                 ctx->last_elo0 = entryLo0;
 152                 ctx->last_elo1 = entryLo1;
 153         }
 154
 155         if (access_type == PCI_ACCESS_WRITE)
 156                 __raw_writel(*data, ctx->pci_cfg_vm->addr + offset);
 157         else
 158                 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset);
 159         wmb();
 160
 161         DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n",
 162             access_type, bus->number, device, where, *data, offset);
 163
 164         /* check for errors, master abort */
 165         status = __raw_readl(ctx->regs + PCI_REG_STATCMD);
 166         if (status & (1 << 29)) {
 167                 *data = 0xffffffff;
 168                 error = -1;
 169                 DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
 170                     access_type, bus->number, device);
 171         } else if ((status >> 28) & 0xf) {
 172                 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
 173                     device, (status >> 28) & 0xf);
 174
 175                 /* clear errors */
 176                 __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD);
 177
 178                 *data = 0xffffffff;
 179                 error = -1;
 180         }
 181
 182         /* Take away the IDSEL. */
 183         (void)ctx->board_pci_idsel(device, 0);
 184
 185         local_irq_restore(flags);
 186         return error;
 187 }
 188
 189 static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 190                             int where,  u8 *val)
 191 {
 192         u32 data;
 193         int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 194
 195         if (where & 1)
 196                 data >>= 8;
 197         if (where & 2)
 198                 data >>= 16;
 199         *val = data & 0xff;
 200         return ret;
 201 }
 202
 203 static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 204                             int where, u16 *val)
 205 {
 206         u32 data;
 207         int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 208
 209         if (where & 2)
 210                 data >>= 16;
 211         *val = data & 0xffff;
 212         return ret;
 213 }
 214
 215 static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 216                              int where, u32 *val)
 217 {
 218         return config_access(PCI_ACCESS_READ, bus, devfn, where, val);
 219 }
 220
 221 static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
 222                              int where, u8 val)
 223 {
 224         u32 data = 0;
 225
 226         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 227                 return -1;
 228
 229         data = (data & ~(0xff << ((where & 3) << 3))) |
 230                (val << ((where & 3) << 3));
 231
 232         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 233                 return -1;
 234
 235         return PCIBIOS_SUCCESSFUL;
 236 }
 237
 238 static int write_config_word(struct pci_bus *bus, unsigned int devfn,
 239                              int where, u16 val)
 240 {
 241         u32 data = 0;
 242
 243         if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 244                 return -1;
 245
 246         data = (data & ~(0xffff << ((where & 3) << 3))) |
 247                (val << ((where & 3) << 3));
 248
 249         if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 250                 return -1;
 251
 252         return PCIBIOS_SUCCESSFUL;
 253 }
 254
 255 static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
 256                               int where, u32 val)
 257 {
 258         return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val);
 259 }
 260
 261 static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn,
 262                        int where, int size, u32 *val)
 263 {
 264         switch (size) {
 265         case 1: {
 266                         u8 _val;
 267                         int rc = read_config_byte(bus, devfn, where, &_val);
 268
 269                         *val = _val;
 270                         return rc;
 271                 }
 272         case 2: {
 273                         u16 _val;
 274                         int rc = read_config_word(bus, devfn, where, &_val);
 275
 276                         *val = _val;
 277                         return rc;
 278                 }
 279         default:
 280                 return read_config_dword(bus, devfn, where, val);
 281         }
 282 }
 283
 284 static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn,
 285                              int where, int size, u32 val)
 286 {
 287         switch (size) {
 288         case 1:
 289                 return write_config_byte(bus, devfn, where, (u8) val);
 290         case 2:
 291                 return write_config_word(bus, devfn, where, (u16) val);
 292         default:
 293                 return write_config_dword(bus, devfn, where, val);
 294         }
 295 }
 296
 297 static struct pci_ops alchemy_pci_ops = {
 298         .read   = alchemy_pci_read,
 299         .write  = alchemy_pci_write,
 300 };
 301
 302 static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
 303 {
 304         return 1;       /* success */
 305 }
 306
 307 static int __devinit alchemy_pci_probe(struct platform_device *pdev)
 308 {
 309         struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
 310         struct alchemy_pci_context *ctx;
 311         void __iomem *virt_io;
 312         unsigned long val;
 313         struct resource *r;
 314         int ret;
 315
 316         /* need at least PCI IRQ mapping table */
 317         if (!pd) {
 318                 dev_err(&pdev->dev, "need platform data for PCI setup\n");
 319                 ret = -ENODEV;
 320                 goto out;
 321         }
 322
 323         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 324         if (!ctx) {
 325                 dev_err(&pdev->dev, "no memory for pcictl context\n");
 326                 ret = -ENOMEM;
 327                 goto out;
 328         }
 329
 330         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 331         if (!r) {
 332                 dev_err(&pdev->dev, "no  pcictl ctrl regs resource\n");
 333                 ret = -ENODEV;
 334                 goto out1;
 335         }
 336
 337         if (!request_mem_region(r->start, resource_size(r), pdev->name)) {
 338                 dev_err(&pdev->dev, "cannot claim pci regs\n");
 339                 ret = -ENODEV;
 340                 goto out1;
 341         }
 342
 343         ctx->regs = ioremap_nocache(r->start, resource_size(r));
 344         if (!ctx->regs) {
 345                 dev_err(&pdev->dev, "cannot map pci regs\n");
 346                 ret = -ENODEV;
 347                 goto out2;
 348         }
 349
 350         /* map parts of the PCI IO area */
 351         /* REVISIT: if this changes with a newer variant (doubt it) make this
 352          * a platform resource.
 353          */
 354         virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000);
 355         if (!virt_io) {
 356                 dev_err(&pdev->dev, "cannot remap pci io space\n");
 357                 ret = -ENODEV;
 358                 goto out3;
 359         }
 360         ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
 361
 362 #ifdef CONFIG_DMA_NONCOHERENT
 363         /* Au1500 revisions older than AD have borked coherent PCI */
 364         if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
 365             (read_c0_prid() < 0x01030202)) {
 366                 val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
 367                 val |= PCI_CONFIG_NC;
 368                 __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
 369                 wmb();
 370                 dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n");
 371         }
 372 #endif
 373
 374         if (pd->board_map_irq)
 375                 ctx->board_map_irq = pd->board_map_irq;
 376
 377         if (pd->board_pci_idsel)
 378                 ctx->board_pci_idsel = pd->board_pci_idsel;
 379         else
 380                 ctx->board_pci_idsel = alchemy_pci_def_idsel;
 381
 382         /* fill in relevant pci_controller members */
 383         ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops;
 384         ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres;
 385         ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores;
 386
 387         /* we can't ioremap the entire pci config space because it's too large,
 388          * nor can we dynamically ioremap it because some drivers use the
 389          * PCI config routines from within atomic contex and that becomes a
 390          * problem in get_vm_area().  Instead we use one wired TLB entry to
 391          * handle all config accesses for all busses.
 392          */
 393         ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
 394         if (!ctx->pci_cfg_vm) {
 395                 dev_err(&pdev->dev, "unable to get vm area\n");
 396                 ret = -ENOMEM;
 397                 goto out4;
 398         }
 399         ctx->wired_entry = 8192;        /* impossibly high value */
 400
 401         set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
 402
 403         /* board may want to modify bits in the config register, do it now */
 404         val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
 405         val &= ~pd->pci_cfg_clr;
 406         val |= pd->pci_cfg_set;
 407         val &= ~PCI_CONFIG_PD;          /* clear disable bit */
 408         __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
 409         wmb();
 410
 411         platform_set_drvdata(pdev, ctx);
 412         register_pci_controller(&ctx->alchemy_pci_ctrl);
 413
 414         return 0;
 415
 416 out4:
 417         iounmap(virt_io);
 418 out3:
 419         iounmap(ctx->regs);
 420 out2:
 421         release_mem_region(r->start, resource_size(r));
 422 out1:
 423         kfree(ctx);
 424 out:
 425         return ret;
 426 }
 427
 428
 429 #ifdef CONFIG_PM
 430 /* save PCI controller register contents. */
 431 static int alchemy_pci_suspend(struct device *dev)
 432 {
 433         struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
 434
 435         ctx->pm[0]  = __raw_readl(ctx->regs + PCI_REG_CMEM);
 436         ctx->pm[1]  = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
 437         ctx->pm[2]  = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
 438         ctx->pm[3]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
 439         ctx->pm[4]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
 440         ctx->pm[5]  = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
 441         ctx->pm[6]  = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
 442         ctx->pm[7]  = __raw_readl(ctx->regs + PCI_REG_ID);
 443         ctx->pm[8]  = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
 444         ctx->pm[9]  = __raw_readl(ctx->regs + PCI_REG_PARAM);
 445         ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
 446         ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
 447
 448         return 0;
 449 }
 450
 451 static int alchemy_pci_resume(struct device *dev)
 452 {
 453         struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
 454
 455         __raw_writel(ctx->pm[0],  ctx->regs + PCI_REG_CMEM);
 456         __raw_writel(ctx->pm[2],  ctx->regs + PCI_REG_B2BMASK_CCH);
 457         __raw_writel(ctx->pm[3],  ctx->regs + PCI_REG_B2BBASE0_VID);
 458         __raw_writel(ctx->pm[4],  ctx->regs + PCI_REG_B2BBASE1_SID);
 459         __raw_writel(ctx->pm[5],  ctx->regs + PCI_REG_MWMASK_DEV);
 460         __raw_writel(ctx->pm[6],  ctx->regs + PCI_REG_MWBASE_REV_CCL);
 461         __raw_writel(ctx->pm[7],  ctx->regs + PCI_REG_ID);
 462         __raw_writel(ctx->pm[8],  ctx->regs + PCI_REG_CLASSREV);
 463         __raw_writel(ctx->pm[9],  ctx->regs + PCI_REG_PARAM);
 464         __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
 465         __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
 466         wmb();
 467         __raw_writel(ctx->pm[1],  ctx->regs + PCI_REG_CONFIG);
 468         wmb();
 469
 470         return 0;
 471 }
 472
 473 static const struct dev_pm_ops alchemy_pci_pmops = {
 474         .suspend        = alchemy_pci_suspend,
 475         .resume         = alchemy_pci_resume,
 476 };
 477
 478 #define ALCHEMY_PCICTL_PM       (&alchemy_pci_pmops)
 479
 480 #else
 481 #define ALCHEMY_PCICTL_PM       NULL
 482 #endif
 483
 484 static struct platform_driver alchemy_pcictl_driver = {
 485         .probe          = alchemy_pci_probe,
 486         .driver = {
 487                 .name   = "alchemy-pci",
 488                 .owner  = THIS_MODULE,
 489                 .pm     = ALCHEMY_PCICTL_PM,
 490         },
 491 };
 492
 493 static int __init alchemy_pci_init(void)
 494 {
 495         /* Au1500/Au1550 have PCI */
 496         switch (alchemy_get_cputype()) {
 497         case ALCHEMY_CPU_AU1500:
 498         case ALCHEMY_CPU_AU1550:
 499                 return platform_driver_register(&alchemy_pcictl_driver);
 500         }
 501         return 0;
 502 }
 503 arch_initcall(alchemy_pci_init);
 504
 505
 506 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 507 {
 508         struct alchemy_pci_context *ctx = dev->sysdata;
 509         if (ctx && ctx->board_map_irq)
 510                 return ctx->board_map_irq(dev, slot, pin);
 511         return -1;
 512 }
 513
 514 int pcibios_plat_dev_init(struct pci_dev *dev)
 515 {
 516         return 0;
 517 }