arch/mips/momentum/ocelot_c/irq.c

   1 /*
   2  * Copyright (C) 2000 RidgeRun, Inc.
   3  * Author: RidgeRun, Inc.
   4  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
   5  *
   6  * Copyright 2001 MontaVista Software Inc.
   7  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
   8  * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
   9  *
  10  *  This program is free software; you can redistribute  it and/or modify it
  11  *  under  the terms of  the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the  License, or (at your
  13  *  option) any later version.
  14  *
  15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  *  You should have received a copy of the  GNU General Public License along
  27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  28  *  675 Mass Ave, Cambridge, MA 02139, USA.
  29  *
  30  */
  31 #include <linux/errno.h>
  32 #include <linux/init.h>
  33 #include <linux/kernel_stat.h>
  34 #include <linux/module.h>
  35 #include <linux/signal.h>
  36 #include <linux/sched.h>
  37 #include <linux/types.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/ioport.h>
  40 #include <linux/timex.h>
  41 #include <linux/slab.h>
  42 #include <linux/random.h>
  43 #include <linux/bitops.h>
  44 #include <linux/mv643xx.h>
  45 #include <asm/bootinfo.h>
  46 #include <asm/io.h>
  47 #include <asm/irq_cpu.h>
  48 #include <asm/mipsregs.h>
  49 #include <asm/system.h>
  50
  51 extern void uart_irq_init(void);
  52 extern void cpci_irq_init(void);
  53
  54 static struct irqaction cascade_fpga = {
  55         no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
  56 };
  57
  58 static struct irqaction cascade_mv64340 = {
  59         no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
  60 };
  61
  62 extern void ll_uart_irq(void);
  63 extern void ll_cpci_irq(void);
  64
  65 asmlinkage void plat_irq_dispatch(void)
  66 {
  67         unsigned int pending = read_c0_cause() & read_c0_status();
  68
  69         if (pending & STATUSF_IP0)
  70                 do_IRQ(0);
  71         else if (pending & STATUSF_IP1)
  72                 do_IRQ(1);
  73         else if (pending & STATUSF_IP2)
  74                 do_IRQ(2);
  75         else if (pending & STATUSF_IP3)
  76                 ll_uart_irq();
  77         else if (pending & STATUSF_IP4)
  78                 do_IRQ(4);
  79         else if (pending & STATUSF_IP5)
  80                 ll_cpci_irq();
  81         else if (pending & STATUSF_IP6)
  82                 ll_mv64340_irq(regs);
  83         else if (pending & STATUSF_IP7)
  84                 do_IRQ(7);
  85         else
  86                 spurious_interrupt();
  87 }
  88
  89 void __init arch_init_irq(void)
  90 {
  91         /*
  92          * Clear all of the interrupts while we change the able around a bit.
  93          * int-handler is not on bootstrap
  94          */
  95         clear_c0_status(ST0_IM);
  96
  97         mips_cpu_irq_init(0);
  98
  99         /* set up the cascading interrupts */
 100         setup_irq(3, &cascade_fpga);
 101         setup_irq(5, &cascade_fpga);
 102         setup_irq(6, &cascade_mv64340);
 103
 104         mv64340_irq_init(16);
 105         uart_irq_init();
 106         cpci_irq_init();
 107 }