arch/mips/mips-boards/malta/malta_int.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
   4  * Copyright (C) 2001 Ralf Baechle
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  * Routines for generic manipulation of the interrupts found on the MIPS
  20  * Malta board.
  21  * The interrupt controller is located in the South Bridge a PIIX4 device
  22  * with two internal 82C95 interrupt controllers.
  23  */
  24 #include <linux/init.h>
  25 #include <linux/irq.h>
  26 #include <linux/sched.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/kernel_stat.h>
  30 #include <linux/random.h>
  31
  32 #include <asm/i8259.h>
  33 #include <asm/irq_cpu.h>
  34 #include <asm/io.h>
  35 #include <asm/irq_regs.h>
  36 #include <asm/mips-boards/malta.h>
  37 #include <asm/mips-boards/maltaint.h>
  38 #include <asm/mips-boards/piix4.h>
  39 #include <asm/gt64120.h>
  40 #include <asm/mips-boards/generic.h>
  41 #include <asm/mips-boards/msc01_pci.h>
  42 #include <asm/msc01_ic.h>
  43
  44 extern void mips_timer_interrupt(void);
  45
  46 static DEFINE_SPINLOCK(mips_irq_lock);
  47
  48 static inline int mips_pcibios_iack(void)
  49 {
  50         int irq;
  51         u32 dummy;
  52
  53         /*
  54          * Determine highest priority pending interrupt by performing
  55          * a PCI Interrupt Acknowledge cycle.
  56          */
  57         switch(mips_revision_corid) {
  58         case MIPS_REVISION_CORID_CORE_MSC:
  59         case MIPS_REVISION_CORID_CORE_FPGA2:
  60         case MIPS_REVISION_CORID_CORE_FPGA3:
  61         case MIPS_REVISION_CORID_CORE_24K:
  62         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
  63                 MSC_READ(MSC01_PCI_IACK, irq);
  64                 irq &= 0xff;
  65                 break;
  66         case MIPS_REVISION_CORID_QED_RM5261:
  67         case MIPS_REVISION_CORID_CORE_LV:
  68         case MIPS_REVISION_CORID_CORE_FPGA:
  69         case MIPS_REVISION_CORID_CORE_FPGAR2:
  70                 irq = GT_READ(GT_PCI0_IACK_OFS);
  71                 irq &= 0xff;
  72                 break;
  73         case MIPS_REVISION_CORID_BONITO64:
  74         case MIPS_REVISION_CORID_CORE_20K:
  75         case MIPS_REVISION_CORID_CORE_EMUL_BON:
  76                 /* The following will generate a PCI IACK cycle on the
  77                  * Bonito controller. It's a little bit kludgy, but it
  78                  * was the easiest way to implement it in hardware at
  79                  * the given time.
  80                  */
  81                 BONITO_PCIMAP_CFG = 0x20000;
  82
  83                 /* Flush Bonito register block */
  84                 dummy = BONITO_PCIMAP_CFG;
  85                 iob();    /* sync */
  86
  87                 irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
  88                 iob();    /* sync */
  89                 irq &= 0xff;
  90                 BONITO_PCIMAP_CFG = 0;
  91                 break;
  92         default:
  93                 printk("Unknown Core card, don't know the system controller.\n");
  94                 return -1;
  95         }
  96         return irq;
  97 }
  98
  99 static inline int get_int(void)
 100 {
 101         unsigned long flags;
 102         int irq;
 103         spin_lock_irqsave(&mips_irq_lock, flags);
 104
 105         irq = mips_pcibios_iack();
 106
 107         /*
 108          * The only way we can decide if an interrupt is spurious
 109          * is by checking the 8259 registers.  This needs a spinlock
 110          * on an SMP system,  so leave it up to the generic code...
 111          */
 112
 113         spin_unlock_irqrestore(&mips_irq_lock, flags);
 114
 115         return irq;
 116 }
 117
 118 static void malta_hw0_irqdispatch(void)
 119 {
 120         int irq;
 121
 122         irq = get_int();
 123         if (irq < 0) {
 124                 return;  /* interrupt has already been cleared */
 125         }
 126
 127         do_IRQ(MALTA_INT_BASE + irq);
 128 }
 129
 130 static void corehi_irqdispatch(void)
 131 {
 132         unsigned int intedge, intsteer, pcicmd, pcibadaddr;
 133         unsigned int pcimstat, intisr, inten, intpol;
 134         unsigned int intrcause,datalo,datahi;
 135         struct pt_regs *regs = get_irq_regs();
 136
 137         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
 138         printk("epc   : %08lx\nStatus: %08lx\n"
 139                "Cause : %08lx\nbadVaddr : %08lx\n",
 140                regs->cp0_epc, regs->cp0_status,
 141                regs->cp0_cause, regs->cp0_badvaddr);
 142
 143         /* Read all the registers and then print them as there is a
 144            problem with interspersed printk's upsetting the Bonito controller.
 145            Do it for the others too.
 146         */
 147
 148         switch(mips_revision_corid) {
 149         case MIPS_REVISION_CORID_CORE_MSC:
 150         case MIPS_REVISION_CORID_CORE_FPGA2:
 151         case MIPS_REVISION_CORID_CORE_FPGA3:
 152         case MIPS_REVISION_CORID_CORE_24K:
 153         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 154                 ll_msc_irq();
 155                 break;
 156         case MIPS_REVISION_CORID_QED_RM5261:
 157         case MIPS_REVISION_CORID_CORE_LV:
 158         case MIPS_REVISION_CORID_CORE_FPGA:
 159         case MIPS_REVISION_CORID_CORE_FPGAR2:
 160                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
 161                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
 162                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
 163                 printk("GT_INTRCAUSE = %08x\n", intrcause);
 164                 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
 165                 break;
 166         case MIPS_REVISION_CORID_BONITO64:
 167         case MIPS_REVISION_CORID_CORE_20K:
 168         case MIPS_REVISION_CORID_CORE_EMUL_BON:
 169                 pcibadaddr = BONITO_PCIBADADDR;
 170                 pcimstat = BONITO_PCIMSTAT;
 171                 intisr = BONITO_INTISR;
 172                 inten = BONITO_INTEN;
 173                 intpol = BONITO_INTPOL;
 174                 intedge = BONITO_INTEDGE;
 175                 intsteer = BONITO_INTSTEER;
 176                 pcicmd = BONITO_PCICMD;
 177                 printk("BONITO_INTISR = %08x\n", intisr);
 178                 printk("BONITO_INTEN = %08x\n", inten);
 179                 printk("BONITO_INTPOL = %08x\n", intpol);
 180                 printk("BONITO_INTEDGE = %08x\n", intedge);
 181                 printk("BONITO_INTSTEER = %08x\n", intsteer);
 182                 printk("BONITO_PCICMD = %08x\n", pcicmd);
 183                 printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
 184                 printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
 185                 break;
 186         }
 187
 188         /* We die here*/
 189         die("CoreHi interrupt", regs);
 190 }
 191
 192 static inline int clz(unsigned long x)
 193 {
 194         __asm__ (
 195         "       .set    push                                    \n"
 196         "       .set    mips32                                  \n"
 197         "       clz     %0, %1                                  \n"
 198         "       .set    pop                                     \n"
 199         : "=r" (x)
 200         : "r" (x));
 201
 202         return x;
 203 }
 204
 205 /*
 206  * Version of ffs that only looks at bits 12..15.
 207  */
 208 static inline unsigned int irq_ffs(unsigned int pending)
 209 {
 210 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 211         return -clz(pending) + 31 - CAUSEB_IP;
 212 #else
 213         unsigned int a0 = 7;
 214         unsigned int t0;
 215
 216         t0 = pending & 0xf000;
 217         t0 = t0 < 1;
 218         t0 = t0 << 2;
 219         a0 = a0 - t0;
 220         pending = pending << t0;
 221
 222         t0 = pending & 0xc000;
 223         t0 = t0 < 1;
 224         t0 = t0 << 1;
 225         a0 = a0 - t0;
 226         pending = pending << t0;
 227
 228         t0 = pending & 0x8000;
 229         t0 = t0 < 1;
 230         //t0 = t0 << 2;
 231         a0 = a0 - t0;
 232         //pending = pending << t0;
 233
 234         return a0;
 235 #endif
 236 }
 237
 238 /*
 239  * IRQs on the Malta board look basically (barring software IRQs which we
 240  * don't use at all and all external interrupt sources are combined together
 241  * on hardware interrupt 0 (MIPS IRQ 2)) like:
 242  *
 243  *      MIPS IRQ        Source
 244  *      --------        ------
 245  *             0        Software (ignored)
 246  *             1        Software (ignored)
 247  *             2        Combined hardware interrupt (hw0)
 248  *             3        Hardware (ignored)
 249  *             4        Hardware (ignored)
 250  *             5        Hardware (ignored)
 251  *             6        Hardware (ignored)
 252  *             7        R4k timer (what we use)
 253  *
 254  * We handle the IRQ according to _our_ priority which is:
 255  *
 256  * Highest ----     R4k Timer
 257  * Lowest  ----     Combined hardware interrupt
 258  *
 259  * then we just return, if multiple IRQs are pending then we will just take
 260  * another exception, big deal.
 261  */
 262
 263 asmlinkage void plat_irq_dispatch(void)
 264 {
 265         unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 266         int irq;
 267
 268         irq = irq_ffs(pending);
 269
 270         if (irq == MIPSCPU_INT_I8259A)
 271                 malta_hw0_irqdispatch();
 272         else if (irq > 0)
 273                 do_IRQ(MIPSCPU_INT_BASE + irq);
 274         else
 275                 spurious_interrupt();
 276 }
 277
 278 static struct irqaction i8259irq = {
 279         .handler = no_action,
 280         .name = "XT-PIC cascade"
 281 };
 282
 283 static struct irqaction corehi_irqaction = {
 284         .handler = no_action,
 285         .name = "CoreHi"
 286 };
 287
 288 msc_irqmap_t __initdata msc_irqmap[] = {
 289         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
 290         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 291 };
 292 int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
 293
 294 msc_irqmap_t __initdata msc_eicirqmap[] = {
 295         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
 296         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
 297         {MSC01E_INT_I8259A,             MSC01_IRQ_LEVEL, 0},
 298         {MSC01E_INT_SMI,                MSC01_IRQ_LEVEL, 0},
 299         {MSC01E_INT_COREHI,             MSC01_IRQ_LEVEL, 0},
 300         {MSC01E_INT_CORELO,             MSC01_IRQ_LEVEL, 0},
 301         {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
 302         {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 303         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
 304         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 305 };
 306 int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
 307
 308 void __init arch_init_irq(void)
 309 {
 310         init_i8259_irqs();
 311
 312         if (!cpu_has_veic)
 313                 mips_cpu_irq_init (MIPSCPU_INT_BASE);
 314
 315         switch(mips_revision_corid) {
 316         case MIPS_REVISION_CORID_CORE_MSC:
 317         case MIPS_REVISION_CORID_CORE_FPGA2:
 318         case MIPS_REVISION_CORID_CORE_FPGA3:
 319         case MIPS_REVISION_CORID_CORE_24K:
 320         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 321                 if (cpu_has_veic)
 322                         init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
 323                 else
 324                         init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
 325         }
 326
 327         if (cpu_has_veic) {
 328                 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
 329                 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
 330                 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
 331                 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
 332         }
 333         else if (cpu_has_vint) {
 334                 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
 335                 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
 336 #ifdef CONFIG_MIPS_MT_SMTC
 337                 setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq,
 338                         (0x100 << MIPSCPU_INT_I8259A));
 339                 setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI,
 340                         &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
 341 #else /* Not SMTC */
 342                 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 343                 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
 344 #endif /* CONFIG_MIPS_MT_SMTC */
 345         }
 346         else {
 347                 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 348                 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
 349         }
 350 }