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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / traps.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/kprobes.h>
29 #include <linux/notifier.h>
30 #include <linux/kdb.h>
31 #include <linux/irq.h>
32 #include <linux/perf_event.h>
33
34 #include <asm/bootinfo.h>
35 #include <asm/branch.h>
36 #include <asm/break.h>
37 #include <asm/cop2.h>
38 #include <asm/cpu.h>
39 #include <asm/dsp.h>
40 #include <asm/fpu.h>
41 #include <asm/fpu_emulator.h>
42 #include <asm/mipsregs.h>
43 #include <asm/mipsmtregs.h>
44 #include <asm/module.h>
45 #include <asm/pgtable.h>
46 #include <asm/ptrace.h>
47 #include <asm/sections.h>
48 #include <asm/system.h>
49 #include <asm/tlbdebug.h>
50 #include <asm/traps.h>
51 #include <asm/uaccess.h>
52 #include <asm/watch.h>
53 #include <asm/mmu_context.h>
54 #include <asm/types.h>
55 #include <asm/stacktrace.h>
56 #include <asm/uasm.h>
57
58 extern void check_wait(void);
59 extern asmlinkage void r4k_wait(void);
60 extern asmlinkage void rollback_handle_int(void);
61 extern asmlinkage void handle_int(void);
62 extern asmlinkage void handle_tlbm(void);
63 extern asmlinkage void handle_tlbl(void);
64 extern asmlinkage void handle_tlbs(void);
65 extern asmlinkage void handle_adel(void);
66 extern asmlinkage void handle_ades(void);
67 extern asmlinkage void handle_ibe(void);
68 extern asmlinkage void handle_dbe(void);
69 extern asmlinkage void handle_sys(void);
70 extern asmlinkage void handle_bp(void);
71 extern asmlinkage void handle_ri(void);
72 extern asmlinkage void handle_ri_rdhwr_vivt(void);
73 extern asmlinkage void handle_ri_rdhwr(void);
74 extern asmlinkage void handle_cpu(void);
75 extern asmlinkage void handle_ov(void);
76 extern asmlinkage void handle_tr(void);
77 extern asmlinkage void handle_fpe(void);
78 extern asmlinkage void handle_mdmx(void);
79 extern asmlinkage void handle_watch(void);
80 extern asmlinkage void handle_mt(void);
81 extern asmlinkage void handle_dsp(void);
82 extern asmlinkage void handle_mcheck(void);
83 extern asmlinkage void handle_reserved(void);
84
85 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
86 struct mips_fpu_struct *ctx, int has_fpu,
87 void *__user *fault_addr);
88
89 void (*board_be_init)(void);
90 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
91 void (*board_nmi_handler_setup)(void);
92 void (*board_ejtag_handler_setup)(void);
93 void (*board_bind_eic_interrupt)(int irq, int regset);
94
95
96 static void show_raw_backtrace(unsigned long reg29)
97 {
98 unsigned long *sp = (unsigned long *)(reg29 & ~3);
99 unsigned long addr;
100
101 printk("Call Trace:");
102 #ifdef CONFIG_KALLSYMS
103 printk("\n");
104 #endif
105 while (!kstack_end(sp)) {
106 unsigned long __user *p =
107 (unsigned long __user *)(unsigned long)sp++;
108 if (__get_user(addr, p)) {
109 printk(" (Bad stack address)");
110 break;
111 }
112 if (__kernel_text_address(addr))
113 print_ip_sym(addr);
114 }
115 printk("\n");
116 }
117
118 #ifdef CONFIG_KALLSYMS
119 int raw_show_trace;
120 static int __init set_raw_show_trace(char *str)
121 {
122 raw_show_trace = 1;
123 return 1;
124 }
125 __setup("raw_show_trace", set_raw_show_trace);
126 #endif
127
128 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
129 {
130 unsigned long sp = regs->regs[29];
131 unsigned long ra = regs->regs[31];
132 unsigned long pc = regs->cp0_epc;
133
134 if (raw_show_trace || !__kernel_text_address(pc)) {
135 show_raw_backtrace(sp);
136 return;
137 }
138 printk("Call Trace:\n");
139 do {
140 print_ip_sym(pc);
141 pc = unwind_stack(task, &sp, pc, &ra);
142 } while (pc);
143 printk("\n");
144 }
145
146 /*
147 * This routine abuses get_user()/put_user() to reference pointers
148 * with at least a bit of error checking ...
149 */
150 static void show_stacktrace(struct task_struct *task,
151 const struct pt_regs *regs)
152 {
153 const int field = 2 * sizeof(unsigned long);
154 long stackdata;
155 int i;
156 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
157
158 printk("Stack :");
159 i = 0;
160 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
161 if (i && ((i % (64 / field)) == 0))
162 printk("\n ");
163 if (i > 39) {
164 printk(" ...");
165 break;
166 }
167
168 if (__get_user(stackdata, sp++)) {
169 printk(" (Bad stack address)");
170 break;
171 }
172
173 printk(" %0*lx", field, stackdata);
174 i++;
175 }
176 printk("\n");
177 show_backtrace(task, regs);
178 }
179
180 void show_stack(struct task_struct *task, unsigned long *sp)
181 {
182 struct pt_regs regs;
183 if (sp) {
184 regs.regs[29] = (unsigned long)sp;
185 regs.regs[31] = 0;
186 regs.cp0_epc = 0;
187 } else {
188 if (task && task != current) {
189 regs.regs[29] = task->thread.reg29;
190 regs.regs[31] = 0;
191 regs.cp0_epc = task->thread.reg31;
192 #ifdef CONFIG_KGDB_KDB
193 } else if (atomic_read(&kgdb_active) != -1 &&
194 kdb_current_regs) {
195 memcpy(&regs, kdb_current_regs, sizeof(regs));
196 #endif /* CONFIG_KGDB_KDB */
197 } else {
198 prepare_frametrace(&regs);
199 }
200 }
201 show_stacktrace(task, &regs);
202 }
203
204 /*
205 * The architecture-independent dump_stack generator
206 */
207 void dump_stack(void)
208 {
209 struct pt_regs regs;
210
211 prepare_frametrace(&regs);
212 show_backtrace(current, &regs);
213 }
214
215 EXPORT_SYMBOL(dump_stack);
216
217 static void show_code(unsigned int __user *pc)
218 {
219 long i;
220 unsigned short __user *pc16 = NULL;
221
222 printk("\nCode:");
223
224 if ((unsigned long)pc & 1)
225 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
226 for(i = -3 ; i < 6 ; i++) {
227 unsigned int insn;
228 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
229 printk(" (Bad address in epc)\n");
230 break;
231 }
232 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
233 }
234 }
235
236 static void __show_regs(const struct pt_regs *regs)
237 {
238 const int field = 2 * sizeof(unsigned long);
239 unsigned int cause = regs->cp0_cause;
240 int i;
241
242 printk("Cpu %d\n", smp_processor_id());
243
244 /*
245 * Saved main processor registers
246 */
247 for (i = 0; i < 32; ) {
248 if ((i % 4) == 0)
249 printk("$%2d :", i);
250 if (i == 0)
251 printk(" %0*lx", field, 0UL);
252 else if (i == 26 || i == 27)
253 printk(" %*s", field, "");
254 else
255 printk(" %0*lx", field, regs->regs[i]);
256
257 i++;
258 if ((i % 4) == 0)
259 printk("\n");
260 }
261
262 #ifdef CONFIG_CPU_HAS_SMARTMIPS
263 printk("Acx : %0*lx\n", field, regs->acx);
264 #endif
265 printk("Hi : %0*lx\n", field, regs->hi);
266 printk("Lo : %0*lx\n", field, regs->lo);
267
268 /*
269 * Saved cp0 registers
270 */
271 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
272 (void *) regs->cp0_epc);
273 printk(" %s\n", print_tainted());
274 printk("ra : %0*lx %pS\n", field, regs->regs[31],
275 (void *) regs->regs[31]);
276
277 printk("Status: %08x ", (uint32_t) regs->cp0_status);
278
279 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
280 if (regs->cp0_status & ST0_KUO)
281 printk("KUo ");
282 if (regs->cp0_status & ST0_IEO)
283 printk("IEo ");
284 if (regs->cp0_status & ST0_KUP)
285 printk("KUp ");
286 if (regs->cp0_status & ST0_IEP)
287 printk("IEp ");
288 if (regs->cp0_status & ST0_KUC)
289 printk("KUc ");
290 if (regs->cp0_status & ST0_IEC)
291 printk("IEc ");
292 } else {
293 if (regs->cp0_status & ST0_KX)
294 printk("KX ");
295 if (regs->cp0_status & ST0_SX)
296 printk("SX ");
297 if (regs->cp0_status & ST0_UX)
298 printk("UX ");
299 switch (regs->cp0_status & ST0_KSU) {
300 case KSU_USER:
301 printk("USER ");
302 break;
303 case KSU_SUPERVISOR:
304 printk("SUPERVISOR ");
305 break;
306 case KSU_KERNEL:
307 printk("KERNEL ");
308 break;
309 default:
310 printk("BAD_MODE ");
311 break;
312 }
313 if (regs->cp0_status & ST0_ERL)
314 printk("ERL ");
315 if (regs->cp0_status & ST0_EXL)
316 printk("EXL ");
317 if (regs->cp0_status & ST0_IE)
318 printk("IE ");
319 }
320 printk("\n");
321
322 printk("Cause : %08x\n", cause);
323
324 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
325 if (1 <= cause && cause <= 5)
326 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
327
328 printk("PrId : %08x (%s)\n", read_c0_prid(),
329 cpu_name_string());
330 }
331
332 /*
333 * FIXME: really the generic show_regs should take a const pointer argument.
334 */
335 void show_regs(struct pt_regs *regs)
336 {
337 __show_regs((struct pt_regs *)regs);
338 }
339
340 void show_registers(struct pt_regs *regs)
341 {
342 const int field = 2 * sizeof(unsigned long);
343
344 __show_regs(regs);
345 print_modules();
346 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
347 current->comm, current->pid, current_thread_info(), current,
348 field, current_thread_info()->tp_value);
349 if (cpu_has_userlocal) {
350 unsigned long tls;
351
352 tls = read_c0_userlocal();
353 if (tls != current_thread_info()->tp_value)
354 printk("*HwTLS: %0*lx\n", field, tls);
355 }
356
357 show_stacktrace(current, regs);
358 show_code((unsigned int __user *) regs->cp0_epc);
359 printk("\n");
360 }
361
362 static int regs_to_trapnr(struct pt_regs *regs)
363 {
364 return (regs->cp0_cause >> 2) & 0x1f;
365 }
366
367 static DEFINE_SPINLOCK(die_lock);
368
369 void __noreturn die(const char *str, struct pt_regs *regs)
370 {
371 static int die_counter;
372 int sig = SIGSEGV;
373 #ifdef CONFIG_MIPS_MT_SMTC
374 unsigned long dvpret = dvpe();
375 #endif /* CONFIG_MIPS_MT_SMTC */
376
377 notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV);
378
379 console_verbose();
380 spin_lock_irq(&die_lock);
381 bust_spinlocks(1);
382 #ifdef CONFIG_MIPS_MT_SMTC
383 mips_mt_regdump(dvpret);
384 #endif /* CONFIG_MIPS_MT_SMTC */
385
386 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
387 sig = 0;
388
389 printk("%s[#%d]:\n", str, ++die_counter);
390 show_registers(regs);
391 add_taint(TAINT_DIE);
392 spin_unlock_irq(&die_lock);
393
394 if (in_interrupt())
395 panic("Fatal exception in interrupt");
396
397 if (panic_on_oops) {
398 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
399 ssleep(5);
400 panic("Fatal exception");
401 }
402
403 do_exit(sig);
404 }
405
406 extern struct exception_table_entry __start___dbe_table[];
407 extern struct exception_table_entry __stop___dbe_table[];
408
409 __asm__(
410 " .section __dbe_table, \"a\"\n"
411 " .previous \n");
412
413 /* Given an address, look for it in the exception tables. */
414 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
415 {
416 const struct exception_table_entry *e;
417
418 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
419 if (!e)
420 e = search_module_dbetables(addr);
421 return e;
422 }
423
424 asmlinkage void do_be(struct pt_regs *regs)
425 {
426 const int field = 2 * sizeof(unsigned long);
427 const struct exception_table_entry *fixup = NULL;
428 int data = regs->cp0_cause & 4;
429 int action = MIPS_BE_FATAL;
430
431 /* XXX For now. Fixme, this searches the wrong table ... */
432 if (data && !user_mode(regs))
433 fixup = search_dbe_tables(exception_epc(regs));
434
435 if (fixup)
436 action = MIPS_BE_FIXUP;
437
438 if (board_be_handler)
439 action = board_be_handler(regs, fixup != NULL);
440
441 switch (action) {
442 case MIPS_BE_DISCARD:
443 return;
444 case MIPS_BE_FIXUP:
445 if (fixup) {
446 regs->cp0_epc = fixup->nextinsn;
447 return;
448 }
449 break;
450 default:
451 break;
452 }
453
454 /*
455 * Assume it would be too dangerous to continue ...
456 */
457 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
458 data ? "Data" : "Instruction",
459 field, regs->cp0_epc, field, regs->regs[31]);
460 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
461 == NOTIFY_STOP)
462 return;
463
464 die_if_kernel("Oops", regs);
465 force_sig(SIGBUS, current);
466 }
467
468 /*
469 * ll/sc, rdhwr, sync emulation
470 */
471
472 #define OPCODE 0xfc000000
473 #define BASE 0x03e00000
474 #define RT 0x001f0000
475 #define OFFSET 0x0000ffff
476 #define LL 0xc0000000
477 #define SC 0xe0000000
478 #define SPEC0 0x00000000
479 #define SPEC3 0x7c000000
480 #define RD 0x0000f800
481 #define FUNC 0x0000003f
482 #define SYNC 0x0000000f
483 #define RDHWR 0x0000003b
484
485 /*
486 * The ll_bit is cleared by r*_switch.S
487 */
488
489 unsigned int ll_bit;
490 struct task_struct *ll_task;
491
492 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
493 {
494 unsigned long value, __user *vaddr;
495 long offset;
496
497 /*
498 * analyse the ll instruction that just caused a ri exception
499 * and put the referenced address to addr.
500 */
501
502 /* sign extend offset */
503 offset = opcode & OFFSET;
504 offset <<= 16;
505 offset >>= 16;
506
507 vaddr = (unsigned long __user *)
508 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
509
510 if ((unsigned long)vaddr & 3)
511 return SIGBUS;
512 if (get_user(value, vaddr))
513 return SIGSEGV;
514
515 preempt_disable();
516
517 if (ll_task == NULL || ll_task == current) {
518 ll_bit = 1;
519 } else {
520 ll_bit = 0;
521 }
522 ll_task = current;
523
524 preempt_enable();
525
526 regs->regs[(opcode & RT) >> 16] = value;
527
528 return 0;
529 }
530
531 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
532 {
533 unsigned long __user *vaddr;
534 unsigned long reg;
535 long offset;
536
537 /*
538 * analyse the sc instruction that just caused a ri exception
539 * and put the referenced address to addr.
540 */
541
542 /* sign extend offset */
543 offset = opcode & OFFSET;
544 offset <<= 16;
545 offset >>= 16;
546
547 vaddr = (unsigned long __user *)
548 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
549 reg = (opcode & RT) >> 16;
550
551 if ((unsigned long)vaddr & 3)
552 return SIGBUS;
553
554 preempt_disable();
555
556 if (ll_bit == 0 || ll_task != current) {
557 regs->regs[reg] = 0;
558 preempt_enable();
559 return 0;
560 }
561
562 preempt_enable();
563
564 if (put_user(regs->regs[reg], vaddr))
565 return SIGSEGV;
566
567 regs->regs[reg] = 1;
568
569 return 0;
570 }
571
572 /*
573 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
574 * opcodes are supposed to result in coprocessor unusable exceptions if
575 * executed on ll/sc-less processors. That's the theory. In practice a
576 * few processors such as NEC's VR4100 throw reserved instruction exceptions
577 * instead, so we're doing the emulation thing in both exception handlers.
578 */
579 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
580 {
581 if ((opcode & OPCODE) == LL) {
582 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
583 1, 0, regs, 0);
584 return simulate_ll(regs, opcode);
585 }
586 if ((opcode & OPCODE) == SC) {
587 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
588 1, 0, regs, 0);
589 return simulate_sc(regs, opcode);
590 }
591
592 return -1; /* Must be something else ... */
593 }
594
595 /*
596 * Simulate trapping 'rdhwr' instructions to provide user accessible
597 * registers not implemented in hardware.
598 */
599 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
600 {
601 struct thread_info *ti = task_thread_info(current);
602
603 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
604 int rd = (opcode & RD) >> 11;
605 int rt = (opcode & RT) >> 16;
606 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
607 1, 0, regs, 0);
608 switch (rd) {
609 case 0: /* CPU number */
610 regs->regs[rt] = smp_processor_id();
611 return 0;
612 case 1: /* SYNCI length */
613 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
614 current_cpu_data.icache.linesz);
615 return 0;
616 case 2: /* Read count register */
617 regs->regs[rt] = read_c0_count();
618 return 0;
619 case 3: /* Count register resolution */
620 switch (current_cpu_data.cputype) {
621 case CPU_20KC:
622 case CPU_25KF:
623 regs->regs[rt] = 1;
624 break;
625 default:
626 regs->regs[rt] = 2;
627 }
628 return 0;
629 case 29:
630 regs->regs[rt] = ti->tp_value;
631 return 0;
632 default:
633 return -1;
634 }
635 }
636
637 /* Not ours. */
638 return -1;
639 }
640
641 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
642 {
643 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
644 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
645 1, 0, regs, 0);
646 return 0;
647 }
648
649 return -1; /* Must be something else ... */
650 }
651
652 asmlinkage void do_ov(struct pt_regs *regs)
653 {
654 siginfo_t info;
655
656 die_if_kernel("Integer overflow", regs);
657
658 info.si_code = FPE_INTOVF;
659 info.si_signo = SIGFPE;
660 info.si_errno = 0;
661 info.si_addr = (void __user *) regs->cp0_epc;
662 force_sig_info(SIGFPE, &info, current);
663 }
664
665 static int process_fpemu_return(int sig, void __user *fault_addr)
666 {
667 if (sig == SIGSEGV || sig == SIGBUS) {
668 struct siginfo si = {0};
669 si.si_addr = fault_addr;
670 si.si_signo = sig;
671 if (sig == SIGSEGV) {
672 if (find_vma(current->mm, (unsigned long)fault_addr))
673 si.si_code = SEGV_ACCERR;
674 else
675 si.si_code = SEGV_MAPERR;
676 } else {
677 si.si_code = BUS_ADRERR;
678 }
679 force_sig_info(sig, &si, current);
680 return 1;
681 } else if (sig) {
682 force_sig(sig, current);
683 return 1;
684 } else {
685 return 0;
686 }
687 }
688
689 /*
690 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
691 */
692 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
693 {
694 siginfo_t info = {0};
695
696 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
697 == NOTIFY_STOP)
698 return;
699 die_if_kernel("FP exception in kernel code", regs);
700
701 if (fcr31 & FPU_CSR_UNI_X) {
702 int sig;
703 void __user *fault_addr = NULL;
704
705 /*
706 * Unimplemented operation exception. If we've got the full
707 * software emulator on-board, let's use it...
708 *
709 * Force FPU to dump state into task/thread context. We're
710 * moving a lot of data here for what is probably a single
711 * instruction, but the alternative is to pre-decode the FP
712 * register operands before invoking the emulator, which seems
713 * a bit extreme for what should be an infrequent event.
714 */
715 /* Ensure 'resume' not overwrite saved fp context again. */
716 lose_fpu(1);
717
718 /* Run the emulator */
719 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
720 &fault_addr);
721
722 /*
723 * We can't allow the emulated instruction to leave any of
724 * the cause bit set in $fcr31.
725 */
726 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
727
728 /* Restore the hardware register state */
729 own_fpu(1); /* Using the FPU again. */
730
731 /* If something went wrong, signal */
732 process_fpemu_return(sig, fault_addr);
733
734 return;
735 } else if (fcr31 & FPU_CSR_INV_X)
736 info.si_code = FPE_FLTINV;
737 else if (fcr31 & FPU_CSR_DIV_X)
738 info.si_code = FPE_FLTDIV;
739 else if (fcr31 & FPU_CSR_OVF_X)
740 info.si_code = FPE_FLTOVF;
741 else if (fcr31 & FPU_CSR_UDF_X)
742 info.si_code = FPE_FLTUND;
743 else if (fcr31 & FPU_CSR_INE_X)
744 info.si_code = FPE_FLTRES;
745 else
746 info.si_code = __SI_FAULT;
747 info.si_signo = SIGFPE;
748 info.si_errno = 0;
749 info.si_addr = (void __user *) regs->cp0_epc;
750 force_sig_info(SIGFPE, &info, current);
751 }
752
753 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
754 const char *str)
755 {
756 siginfo_t info;
757 char b[40];
758
759 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
760 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
761 return;
762 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
763
764 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
765 return;
766
767 /*
768 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
769 * insns, even for trap and break codes that indicate arithmetic
770 * failures. Weird ...
771 * But should we continue the brokenness??? --macro
772 */
773 switch (code) {
774 case BRK_OVERFLOW:
775 case BRK_DIVZERO:
776 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
777 die_if_kernel(b, regs);
778 if (code == BRK_DIVZERO)
779 info.si_code = FPE_INTDIV;
780 else
781 info.si_code = FPE_INTOVF;
782 info.si_signo = SIGFPE;
783 info.si_errno = 0;
784 info.si_addr = (void __user *) regs->cp0_epc;
785 force_sig_info(SIGFPE, &info, current);
786 break;
787 case BRK_BUG:
788 die_if_kernel("Kernel bug detected", regs);
789 force_sig(SIGTRAP, current);
790 break;
791 case BRK_MEMU:
792 /*
793 * Address errors may be deliberately induced by the FPU
794 * emulator to retake control of the CPU after executing the
795 * instruction in the delay slot of an emulated branch.
796 *
797 * Terminate if exception was recognized as a delay slot return
798 * otherwise handle as normal.
799 */
800 if (do_dsemulret(regs))
801 return;
802
803 die_if_kernel("Math emu break/trap", regs);
804 force_sig(SIGTRAP, current);
805 break;
806 default:
807 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
808 die_if_kernel(b, regs);
809 force_sig(SIGTRAP, current);
810 }
811 }
812
813 asmlinkage void do_bp(struct pt_regs *regs)
814 {
815 unsigned int opcode, bcode;
816
817 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
818 goto out_sigsegv;
819
820 /*
821 * There is the ancient bug in the MIPS assemblers that the break
822 * code starts left to bit 16 instead to bit 6 in the opcode.
823 * Gas is bug-compatible, but not always, grrr...
824 * We handle both cases with a simple heuristics. --macro
825 */
826 bcode = ((opcode >> 6) & ((1 << 20) - 1));
827 if (bcode >= (1 << 10))
828 bcode >>= 10;
829
830 /*
831 * notify the kprobe handlers, if instruction is likely to
832 * pertain to them.
833 */
834 switch (bcode) {
835 case BRK_KPROBE_BP:
836 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
837 return;
838 else
839 break;
840 case BRK_KPROBE_SSTEPBP:
841 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
842 return;
843 else
844 break;
845 default:
846 break;
847 }
848
849 do_trap_or_bp(regs, bcode, "Break");
850 return;
851
852 out_sigsegv:
853 force_sig(SIGSEGV, current);
854 }
855
856 asmlinkage void do_tr(struct pt_regs *regs)
857 {
858 unsigned int opcode, tcode = 0;
859
860 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
861 goto out_sigsegv;
862
863 /* Immediate versions don't provide a code. */
864 if (!(opcode & OPCODE))
865 tcode = ((opcode >> 6) & ((1 << 10) - 1));
866
867 do_trap_or_bp(regs, tcode, "Trap");
868 return;
869
870 out_sigsegv:
871 force_sig(SIGSEGV, current);
872 }
873
874 asmlinkage void do_ri(struct pt_regs *regs)
875 {
876 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
877 unsigned long old_epc = regs->cp0_epc;
878 unsigned int opcode = 0;
879 int status = -1;
880
881 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
882 == NOTIFY_STOP)
883 return;
884
885 die_if_kernel("Reserved instruction in kernel code", regs);
886
887 if (unlikely(compute_return_epc(regs) < 0))
888 return;
889
890 if (unlikely(get_user(opcode, epc) < 0))
891 status = SIGSEGV;
892
893 if (!cpu_has_llsc && status < 0)
894 status = simulate_llsc(regs, opcode);
895
896 if (status < 0)
897 status = simulate_rdhwr(regs, opcode);
898
899 if (status < 0)
900 status = simulate_sync(regs, opcode);
901
902 if (status < 0)
903 status = SIGILL;
904
905 if (unlikely(status > 0)) {
906 regs->cp0_epc = old_epc; /* Undo skip-over. */
907 force_sig(status, current);
908 }
909 }
910
911 /*
912 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
913 * emulated more than some threshold number of instructions, force migration to
914 * a "CPU" that has FP support.
915 */
916 static void mt_ase_fp_affinity(void)
917 {
918 #ifdef CONFIG_MIPS_MT_FPAFF
919 if (mt_fpemul_threshold > 0 &&
920 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
921 /*
922 * If there's no FPU present, or if the application has already
923 * restricted the allowed set to exclude any CPUs with FPUs,
924 * we'll skip the procedure.
925 */
926 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
927 cpumask_t tmask;
928
929 current->thread.user_cpus_allowed
930 = current->cpus_allowed;
931 cpus_and(tmask, current->cpus_allowed,
932 mt_fpu_cpumask);
933 set_cpus_allowed_ptr(current, &tmask);
934 set_thread_flag(TIF_FPUBOUND);
935 }
936 }
937 #endif /* CONFIG_MIPS_MT_FPAFF */
938 }
939
940 /*
941 * No lock; only written during early bootup by CPU 0.
942 */
943 static RAW_NOTIFIER_HEAD(cu2_chain);
944
945 int __ref register_cu2_notifier(struct notifier_block *nb)
946 {
947 return raw_notifier_chain_register(&cu2_chain, nb);
948 }
949
950 int cu2_notifier_call_chain(unsigned long val, void *v)
951 {
952 return raw_notifier_call_chain(&cu2_chain, val, v);
953 }
954
955 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
956 void *data)
957 {
958 struct pt_regs *regs = data;
959
960 switch (action) {
961 default:
962 die_if_kernel("Unhandled kernel unaligned access or invalid "
963 "instruction", regs);
964 /* Fall through */
965
966 case CU2_EXCEPTION:
967 force_sig(SIGILL, current);
968 }
969
970 return NOTIFY_OK;
971 }
972
973 asmlinkage void do_cpu(struct pt_regs *regs)
974 {
975 unsigned int __user *epc;
976 unsigned long old_epc;
977 unsigned int opcode;
978 unsigned int cpid;
979 int status;
980 unsigned long __maybe_unused flags;
981
982 die_if_kernel("do_cpu invoked from kernel context!", regs);
983
984 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
985
986 switch (cpid) {
987 case 0:
988 epc = (unsigned int __user *)exception_epc(regs);
989 old_epc = regs->cp0_epc;
990 opcode = 0;
991 status = -1;
992
993 if (unlikely(compute_return_epc(regs) < 0))
994 return;
995
996 if (unlikely(get_user(opcode, epc) < 0))
997 status = SIGSEGV;
998
999 if (!cpu_has_llsc && status < 0)
1000 status = simulate_llsc(regs, opcode);
1001
1002 if (status < 0)
1003 status = simulate_rdhwr(regs, opcode);
1004
1005 if (status < 0)
1006 status = SIGILL;
1007
1008 if (unlikely(status > 0)) {
1009 regs->cp0_epc = old_epc; /* Undo skip-over. */
1010 force_sig(status, current);
1011 }
1012
1013 return;
1014
1015 case 1:
1016 if (used_math()) /* Using the FPU again. */
1017 own_fpu(1);
1018 else { /* First time FPU user. */
1019 init_fpu();
1020 set_used_math();
1021 }
1022
1023 if (!raw_cpu_has_fpu) {
1024 int sig;
1025 void __user *fault_addr = NULL;
1026 sig = fpu_emulator_cop1Handler(regs,
1027 &current->thread.fpu,
1028 0, &fault_addr);
1029 if (!process_fpemu_return(sig, fault_addr))
1030 mt_ase_fp_affinity();
1031 }
1032
1033 return;
1034
1035 case 2:
1036 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1037 return;
1038
1039 case 3:
1040 break;
1041 }
1042
1043 force_sig(SIGILL, current);
1044 }
1045
1046 asmlinkage void do_mdmx(struct pt_regs *regs)
1047 {
1048 force_sig(SIGILL, current);
1049 }
1050
1051 /*
1052 * Called with interrupts disabled.
1053 */
1054 asmlinkage void do_watch(struct pt_regs *regs)
1055 {
1056 u32 cause;
1057
1058 /*
1059 * Clear WP (bit 22) bit of cause register so we don't loop
1060 * forever.
1061 */
1062 cause = read_c0_cause();
1063 cause &= ~(1 << 22);
1064 write_c0_cause(cause);
1065
1066 /*
1067 * If the current thread has the watch registers loaded, save
1068 * their values and send SIGTRAP. Otherwise another thread
1069 * left the registers set, clear them and continue.
1070 */
1071 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1072 mips_read_watch_registers();
1073 local_irq_enable();
1074 force_sig(SIGTRAP, current);
1075 } else {
1076 mips_clear_watch_registers();
1077 local_irq_enable();
1078 }
1079 }
1080
1081 asmlinkage void do_mcheck(struct pt_regs *regs)
1082 {
1083 const int field = 2 * sizeof(unsigned long);
1084 int multi_match = regs->cp0_status & ST0_TS;
1085
1086 show_regs(regs);
1087
1088 if (multi_match) {
1089 printk("Index : %0x\n", read_c0_index());
1090 printk("Pagemask: %0x\n", read_c0_pagemask());
1091 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1092 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1093 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1094 printk("\n");
1095 dump_tlb_all();
1096 }
1097
1098 show_code((unsigned int __user *) regs->cp0_epc);
1099
1100 /*
1101 * Some chips may have other causes of machine check (e.g. SB1
1102 * graduation timer)
1103 */
1104 panic("Caught Machine Check exception - %scaused by multiple "
1105 "matching entries in the TLB.",
1106 (multi_match) ? "" : "not ");
1107 }
1108
1109 asmlinkage void do_mt(struct pt_regs *regs)
1110 {
1111 int subcode;
1112
1113 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1114 >> VPECONTROL_EXCPT_SHIFT;
1115 switch (subcode) {
1116 case 0:
1117 printk(KERN_DEBUG "Thread Underflow\n");
1118 break;
1119 case 1:
1120 printk(KERN_DEBUG "Thread Overflow\n");
1121 break;
1122 case 2:
1123 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1124 break;
1125 case 3:
1126 printk(KERN_DEBUG "Gating Storage Exception\n");
1127 break;
1128 case 4:
1129 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1130 break;
1131 case 5:
1132 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
1133 break;
1134 default:
1135 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1136 subcode);
1137 break;
1138 }
1139 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1140
1141 force_sig(SIGILL, current);
1142 }
1143
1144
1145 asmlinkage void do_dsp(struct pt_regs *regs)
1146 {
1147 if (cpu_has_dsp)
1148 panic("Unexpected DSP exception\n");
1149
1150 force_sig(SIGILL, current);
1151 }
1152
1153 asmlinkage void do_reserved(struct pt_regs *regs)
1154 {
1155 /*
1156 * Game over - no way to handle this if it ever occurs. Most probably
1157 * caused by a new unknown cpu type or after another deadly
1158 * hard/software error.
1159 */
1160 show_regs(regs);
1161 panic("Caught reserved exception %ld - should not happen.",
1162 (regs->cp0_cause & 0x7f) >> 2);
1163 }
1164
1165 static int __initdata l1parity = 1;
1166 static int __init nol1parity(char *s)
1167 {
1168 l1parity = 0;
1169 return 1;
1170 }
1171 __setup("nol1par", nol1parity);
1172 static int __initdata l2parity = 1;
1173 static int __init nol2parity(char *s)
1174 {
1175 l2parity = 0;
1176 return 1;
1177 }
1178 __setup("nol2par", nol2parity);
1179
1180 /*
1181 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1182 * it different ways.
1183 */
1184 static inline void parity_protection_init(void)
1185 {
1186 switch (current_cpu_type()) {
1187 case CPU_24K:
1188 case CPU_34K:
1189 case CPU_74K:
1190 case CPU_1004K:
1191 {
1192 #define ERRCTL_PE 0x80000000
1193 #define ERRCTL_L2P 0x00800000
1194 unsigned long errctl;
1195 unsigned int l1parity_present, l2parity_present;
1196
1197 errctl = read_c0_ecc();
1198 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1199
1200 /* probe L1 parity support */
1201 write_c0_ecc(errctl | ERRCTL_PE);
1202 back_to_back_c0_hazard();
1203 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1204
1205 /* probe L2 parity support */
1206 write_c0_ecc(errctl|ERRCTL_L2P);
1207 back_to_back_c0_hazard();
1208 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1209
1210 if (l1parity_present && l2parity_present) {
1211 if (l1parity)
1212 errctl |= ERRCTL_PE;
1213 if (l1parity ^ l2parity)
1214 errctl |= ERRCTL_L2P;
1215 } else if (l1parity_present) {
1216 if (l1parity)
1217 errctl |= ERRCTL_PE;
1218 } else if (l2parity_present) {
1219 if (l2parity)
1220 errctl |= ERRCTL_L2P;
1221 } else {
1222 /* No parity available */
1223 }
1224
1225 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1226
1227 write_c0_ecc(errctl);
1228 back_to_back_c0_hazard();
1229 errctl = read_c0_ecc();
1230 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1231
1232 if (l1parity_present)
1233 printk(KERN_INFO "Cache parity protection %sabled\n",
1234 (errctl & ERRCTL_PE) ? "en" : "dis");
1235
1236 if (l2parity_present) {
1237 if (l1parity_present && l1parity)
1238 errctl ^= ERRCTL_L2P;
1239 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1240 (errctl & ERRCTL_L2P) ? "en" : "dis");
1241 }
1242 }
1243 break;
1244
1245 case CPU_5KC:
1246 write_c0_ecc(0x80000000);
1247 back_to_back_c0_hazard();
1248 /* Set the PE bit (bit 31) in the c0_errctl register. */
1249 printk(KERN_INFO "Cache parity protection %sabled\n",
1250 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1251 break;
1252 case CPU_20KC:
1253 case CPU_25KF:
1254 /* Clear the DE bit (bit 16) in the c0_status register. */
1255 printk(KERN_INFO "Enable cache parity protection for "
1256 "MIPS 20KC/25KF CPUs.\n");
1257 clear_c0_status(ST0_DE);
1258 break;
1259 default:
1260 break;
1261 }
1262 }
1263
1264 asmlinkage void cache_parity_error(void)
1265 {
1266 const int field = 2 * sizeof(unsigned long);
1267 unsigned int reg_val;
1268
1269 /* For the moment, report the problem and hang. */
1270 printk("Cache error exception:\n");
1271 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1272 reg_val = read_c0_cacheerr();
1273 printk("c0_cacheerr == %08x\n", reg_val);
1274
1275 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1276 reg_val & (1<<30) ? "secondary" : "primary",
1277 reg_val & (1<<31) ? "data" : "insn");
1278 printk("Error bits: %s%s%s%s%s%s%s\n",
1279 reg_val & (1<<29) ? "ED " : "",
1280 reg_val & (1<<28) ? "ET " : "",
1281 reg_val & (1<<26) ? "EE " : "",
1282 reg_val & (1<<25) ? "EB " : "",
1283 reg_val & (1<<24) ? "EI " : "",
1284 reg_val & (1<<23) ? "E1 " : "",
1285 reg_val & (1<<22) ? "E0 " : "");
1286 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1287
1288 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1289 if (reg_val & (1<<22))
1290 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1291
1292 if (reg_val & (1<<23))
1293 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1294 #endif
1295
1296 panic("Can't handle the cache error!");
1297 }
1298
1299 /*
1300 * SDBBP EJTAG debug exception handler.
1301 * We skip the instruction and return to the next instruction.
1302 */
1303 void ejtag_exception_handler(struct pt_regs *regs)
1304 {
1305 const int field = 2 * sizeof(unsigned long);
1306 unsigned long depc, old_epc;
1307 unsigned int debug;
1308
1309 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1310 depc = read_c0_depc();
1311 debug = read_c0_debug();
1312 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1313 if (debug & 0x80000000) {
1314 /*
1315 * In branch delay slot.
1316 * We cheat a little bit here and use EPC to calculate the
1317 * debug return address (DEPC). EPC is restored after the
1318 * calculation.
1319 */
1320 old_epc = regs->cp0_epc;
1321 regs->cp0_epc = depc;
1322 __compute_return_epc(regs);
1323 depc = regs->cp0_epc;
1324 regs->cp0_epc = old_epc;
1325 } else
1326 depc += 4;
1327 write_c0_depc(depc);
1328
1329 #if 0
1330 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1331 write_c0_debug(debug | 0x100);
1332 #endif
1333 }
1334
1335 /*
1336 * NMI exception handler.
1337 */
1338 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1339 {
1340 bust_spinlocks(1);
1341 printk("NMI taken!!!!\n");
1342 die("NMI", regs);
1343 }
1344
1345 #define VECTORSPACING 0x100 /* for EI/VI mode */
1346
1347 unsigned long ebase;
1348 unsigned long exception_handlers[32];
1349 unsigned long vi_handlers[64];
1350
1351 void __init *set_except_vector(int n, void *addr)
1352 {
1353 unsigned long handler = (unsigned long) addr;
1354 unsigned long old_handler = exception_handlers[n];
1355
1356 exception_handlers[n] = handler;
1357 if (n == 0 && cpu_has_divec) {
1358 unsigned long jump_mask = ~((1 << 28) - 1);
1359 u32 *buf = (u32 *)(ebase + 0x200);
1360 unsigned int k0 = 26;
1361 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1362 uasm_i_j(&buf, handler & ~jump_mask);
1363 uasm_i_nop(&buf);
1364 } else {
1365 UASM_i_LA(&buf, k0, handler);
1366 uasm_i_jr(&buf, k0);
1367 uasm_i_nop(&buf);
1368 }
1369 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1370 }
1371 return (void *)old_handler;
1372 }
1373
1374 static asmlinkage void do_default_vi(void)
1375 {
1376 show_regs(get_irq_regs());
1377 panic("Caught unexpected vectored interrupt.");
1378 }
1379
1380 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1381 {
1382 unsigned long handler;
1383 unsigned long old_handler = vi_handlers[n];
1384 int srssets = current_cpu_data.srsets;
1385 u32 *w;
1386 unsigned char *b;
1387
1388 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1389
1390 if (addr == NULL) {
1391 handler = (unsigned long) do_default_vi;
1392 srs = 0;
1393 } else
1394 handler = (unsigned long) addr;
1395 vi_handlers[n] = (unsigned long) addr;
1396
1397 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1398
1399 if (srs >= srssets)
1400 panic("Shadow register set %d not supported", srs);
1401
1402 if (cpu_has_veic) {
1403 if (board_bind_eic_interrupt)
1404 board_bind_eic_interrupt(n, srs);
1405 } else if (cpu_has_vint) {
1406 /* SRSMap is only defined if shadow sets are implemented */
1407 if (srssets > 1)
1408 change_c0_srsmap(0xf << n*4, srs << n*4);
1409 }
1410
1411 if (srs == 0) {
1412 /*
1413 * If no shadow set is selected then use the default handler
1414 * that does normal register saving and a standard interrupt exit
1415 */
1416
1417 extern char except_vec_vi, except_vec_vi_lui;
1418 extern char except_vec_vi_ori, except_vec_vi_end;
1419 extern char rollback_except_vec_vi;
1420 char *vec_start = (cpu_wait == r4k_wait) ?
1421 &rollback_except_vec_vi : &except_vec_vi;
1422 #ifdef CONFIG_MIPS_MT_SMTC
1423 /*
1424 * We need to provide the SMTC vectored interrupt handler
1425 * not only with the address of the handler, but with the
1426 * Status.IM bit to be masked before going there.
1427 */
1428 extern char except_vec_vi_mori;
1429 const int mori_offset = &except_vec_vi_mori - vec_start;
1430 #endif /* CONFIG_MIPS_MT_SMTC */
1431 const int handler_len = &except_vec_vi_end - vec_start;
1432 const int lui_offset = &except_vec_vi_lui - vec_start;
1433 const int ori_offset = &except_vec_vi_ori - vec_start;
1434
1435 if (handler_len > VECTORSPACING) {
1436 /*
1437 * Sigh... panicing won't help as the console
1438 * is probably not configured :(
1439 */
1440 panic("VECTORSPACING too small");
1441 }
1442
1443 memcpy(b, vec_start, handler_len);
1444 #ifdef CONFIG_MIPS_MT_SMTC
1445 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1446
1447 w = (u32 *)(b + mori_offset);
1448 *w = (*w & 0xffff0000) | (0x100 << n);
1449 #endif /* CONFIG_MIPS_MT_SMTC */
1450 w = (u32 *)(b + lui_offset);
1451 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1452 w = (u32 *)(b + ori_offset);
1453 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1454 local_flush_icache_range((unsigned long)b,
1455 (unsigned long)(b+handler_len));
1456 }
1457 else {
1458 /*
1459 * In other cases jump directly to the interrupt handler
1460 *
1461 * It is the handlers responsibility to save registers if required
1462 * (eg hi/lo) and return from the exception using "eret"
1463 */
1464 w = (u32 *)b;
1465 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1466 *w = 0;
1467 local_flush_icache_range((unsigned long)b,
1468 (unsigned long)(b+8));
1469 }
1470
1471 return (void *)old_handler;
1472 }
1473
1474 void *set_vi_handler(int n, vi_handler_t addr)
1475 {
1476 return set_vi_srs_handler(n, addr, 0);
1477 }
1478
1479 extern void cpu_cache_init(void);
1480 extern void tlb_init(void);
1481 extern void flush_tlb_handlers(void);
1482
1483 /*
1484 * Timer interrupt
1485 */
1486 int cp0_compare_irq;
1487 int cp0_compare_irq_shift;
1488
1489 /*
1490 * Performance counter IRQ or -1 if shared with timer
1491 */
1492 int cp0_perfcount_irq;
1493 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1494
1495 static int __cpuinitdata noulri;
1496
1497 static int __init ulri_disable(char *s)
1498 {
1499 pr_info("Disabling ulri\n");
1500 noulri = 1;
1501
1502 return 1;
1503 }
1504 __setup("noulri", ulri_disable);
1505
1506 void __cpuinit per_cpu_trap_init(void)
1507 {
1508 unsigned int cpu = smp_processor_id();
1509 unsigned int status_set = ST0_CU0;
1510 unsigned int hwrena = cpu_hwrena_impl_bits;
1511 #ifdef CONFIG_MIPS_MT_SMTC
1512 int secondaryTC = 0;
1513 int bootTC = (cpu == 0);
1514
1515 /*
1516 * Only do per_cpu_trap_init() for first TC of Each VPE.
1517 * Note that this hack assumes that the SMTC init code
1518 * assigns TCs consecutively and in ascending order.
1519 */
1520
1521 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1522 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1523 secondaryTC = 1;
1524 #endif /* CONFIG_MIPS_MT_SMTC */
1525
1526 /*
1527 * Disable coprocessors and select 32-bit or 64-bit addressing
1528 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1529 * flag that some firmware may have left set and the TS bit (for
1530 * IP27). Set XX for ISA IV code to work.
1531 */
1532 #ifdef CONFIG_64BIT
1533 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1534 #endif
1535 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1536 status_set |= ST0_XX;
1537 if (cpu_has_dsp)
1538 status_set |= ST0_MX;
1539
1540 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1541 status_set);
1542
1543 if (cpu_has_mips_r2)
1544 hwrena |= 0x0000000f;
1545
1546 if (!noulri && cpu_has_userlocal)
1547 hwrena |= (1 << 29);
1548
1549 if (hwrena)
1550 write_c0_hwrena(hwrena);
1551
1552 #ifdef CONFIG_MIPS_MT_SMTC
1553 if (!secondaryTC) {
1554 #endif /* CONFIG_MIPS_MT_SMTC */
1555
1556 if (cpu_has_veic || cpu_has_vint) {
1557 unsigned long sr = set_c0_status(ST0_BEV);
1558 write_c0_ebase(ebase);
1559 write_c0_status(sr);
1560 /* Setting vector spacing enables EI/VI mode */
1561 change_c0_intctl(0x3e0, VECTORSPACING);
1562 }
1563 if (cpu_has_divec) {
1564 if (cpu_has_mipsmt) {
1565 unsigned int vpflags = dvpe();
1566 set_c0_cause(CAUSEF_IV);
1567 evpe(vpflags);
1568 } else
1569 set_c0_cause(CAUSEF_IV);
1570 }
1571
1572 /*
1573 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1574 *
1575 * o read IntCtl.IPTI to determine the timer interrupt
1576 * o read IntCtl.IPPCI to determine the performance counter interrupt
1577 */
1578 if (cpu_has_mips_r2) {
1579 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1580 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1581 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1582 if (cp0_perfcount_irq == cp0_compare_irq)
1583 cp0_perfcount_irq = -1;
1584 } else {
1585 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1586 cp0_compare_irq_shift = cp0_compare_irq;
1587 cp0_perfcount_irq = -1;
1588 }
1589
1590 #ifdef CONFIG_MIPS_MT_SMTC
1591 }
1592 #endif /* CONFIG_MIPS_MT_SMTC */
1593
1594 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1595
1596 atomic_inc(&init_mm.mm_count);
1597 current->active_mm = &init_mm;
1598 BUG_ON(current->mm);
1599 enter_lazy_tlb(&init_mm, current);
1600
1601 #ifdef CONFIG_MIPS_MT_SMTC
1602 if (bootTC) {
1603 #endif /* CONFIG_MIPS_MT_SMTC */
1604 cpu_cache_init();
1605 tlb_init();
1606 #ifdef CONFIG_MIPS_MT_SMTC
1607 } else if (!secondaryTC) {
1608 /*
1609 * First TC in non-boot VPE must do subset of tlb_init()
1610 * for MMU countrol registers.
1611 */
1612 write_c0_pagemask(PM_DEFAULT_MASK);
1613 write_c0_wired(0);
1614 }
1615 #endif /* CONFIG_MIPS_MT_SMTC */
1616 TLBMISS_HANDLER_SETUP();
1617 }
1618
1619 /* Install CPU exception handler */
1620 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1621 {
1622 memcpy((void *)(ebase + offset), addr, size);
1623 local_flush_icache_range(ebase + offset, ebase + offset + size);
1624 }
1625
1626 static char panic_null_cerr[] __cpuinitdata =
1627 "Trying to set NULL cache error exception handler";
1628
1629 /*
1630 * Install uncached CPU exception handler.
1631 * This is suitable only for the cache error exception which is the only
1632 * exception handler that is being run uncached.
1633 */
1634 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1635 unsigned long size)
1636 {
1637 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1638
1639 if (!addr)
1640 panic(panic_null_cerr);
1641
1642 memcpy((void *)(uncached_ebase + offset), addr, size);
1643 }
1644
1645 static int __initdata rdhwr_noopt;
1646 static int __init set_rdhwr_noopt(char *str)
1647 {
1648 rdhwr_noopt = 1;
1649 return 1;
1650 }
1651
1652 __setup("rdhwr_noopt", set_rdhwr_noopt);
1653
1654 void __init trap_init(void)
1655 {
1656 extern char except_vec3_generic, except_vec3_r4000;
1657 extern char except_vec4;
1658 unsigned long i;
1659 int rollback;
1660
1661 check_wait();
1662 rollback = (cpu_wait == r4k_wait);
1663
1664 #if defined(CONFIG_KGDB)
1665 if (kgdb_early_setup)
1666 return; /* Already done */
1667 #endif
1668
1669 if (cpu_has_veic || cpu_has_vint) {
1670 unsigned long size = 0x200 + VECTORSPACING*64;
1671 ebase = (unsigned long)
1672 __alloc_bootmem(size, 1 << fls(size), 0);
1673 } else {
1674 ebase = CKSEG0;
1675 if (cpu_has_mips_r2)
1676 ebase += (read_c0_ebase() & 0x3ffff000);
1677 }
1678
1679 per_cpu_trap_init();
1680
1681 /*
1682 * Copy the generic exception handlers to their final destination.
1683 * This will be overriden later as suitable for a particular
1684 * configuration.
1685 */
1686 set_handler(0x180, &except_vec3_generic, 0x80);
1687
1688 /*
1689 * Setup default vectors
1690 */
1691 for (i = 0; i <= 31; i++)
1692 set_except_vector(i, handle_reserved);
1693
1694 /*
1695 * Copy the EJTAG debug exception vector handler code to it's final
1696 * destination.
1697 */
1698 if (cpu_has_ejtag && board_ejtag_handler_setup)
1699 board_ejtag_handler_setup();
1700
1701 /*
1702 * Only some CPUs have the watch exceptions.
1703 */
1704 if (cpu_has_watch)
1705 set_except_vector(23, handle_watch);
1706
1707 /*
1708 * Initialise interrupt handlers
1709 */
1710 if (cpu_has_veic || cpu_has_vint) {
1711 int nvec = cpu_has_veic ? 64 : 8;
1712 for (i = 0; i < nvec; i++)
1713 set_vi_handler(i, NULL);
1714 }
1715 else if (cpu_has_divec)
1716 set_handler(0x200, &except_vec4, 0x8);
1717
1718 /*
1719 * Some CPUs can enable/disable for cache parity detection, but does
1720 * it different ways.
1721 */
1722 parity_protection_init();
1723
1724 /*
1725 * The Data Bus Errors / Instruction Bus Errors are signaled
1726 * by external hardware. Therefore these two exceptions
1727 * may have board specific handlers.
1728 */
1729 if (board_be_init)
1730 board_be_init();
1731
1732 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1733 set_except_vector(1, handle_tlbm);
1734 set_except_vector(2, handle_tlbl);
1735 set_except_vector(3, handle_tlbs);
1736
1737 set_except_vector(4, handle_adel);
1738 set_except_vector(5, handle_ades);
1739
1740 set_except_vector(6, handle_ibe);
1741 set_except_vector(7, handle_dbe);
1742
1743 set_except_vector(8, handle_sys);
1744 set_except_vector(9, handle_bp);
1745 set_except_vector(10, rdhwr_noopt ? handle_ri :
1746 (cpu_has_vtag_icache ?
1747 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1748 set_except_vector(11, handle_cpu);
1749 set_except_vector(12, handle_ov);
1750 set_except_vector(13, handle_tr);
1751
1752 if (current_cpu_type() == CPU_R6000 ||
1753 current_cpu_type() == CPU_R6000A) {
1754 /*
1755 * The R6000 is the only R-series CPU that features a machine
1756 * check exception (similar to the R4000 cache error) and
1757 * unaligned ldc1/sdc1 exception. The handlers have not been
1758 * written yet. Well, anyway there is no R6000 machine on the
1759 * current list of targets for Linux/MIPS.
1760 * (Duh, crap, there is someone with a triple R6k machine)
1761 */
1762 //set_except_vector(14, handle_mc);
1763 //set_except_vector(15, handle_ndc);
1764 }
1765
1766
1767 if (board_nmi_handler_setup)
1768 board_nmi_handler_setup();
1769
1770 if (cpu_has_fpu && !cpu_has_nofpuex)
1771 set_except_vector(15, handle_fpe);
1772
1773 set_except_vector(22, handle_mdmx);
1774
1775 if (cpu_has_mcheck)
1776 set_except_vector(24, handle_mcheck);
1777
1778 if (cpu_has_mipsmt)
1779 set_except_vector(25, handle_mt);
1780
1781 set_except_vector(26, handle_dsp);
1782
1783 if (cpu_has_vce)
1784 /* Special exception: R4[04]00 uses also the divec space. */
1785 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1786 else if (cpu_has_4kex)
1787 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1788 else
1789 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1790
1791 local_flush_icache_range(ebase, ebase + 0x400);
1792 flush_tlb_handlers();
1793
1794 sort_extable(__start___dbe_table, __stop___dbe_table);
1795
1796 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1797 }
kernel source for telekom puls (alcatel/mediatek)