arch/mips/include/asm/mmu_context.h

   1 /*
   2  * Switch a MMU context.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_MMU_CONTEXT_H
  12 #define _ASM_MMU_CONTEXT_H
  13
  14 #include <linux/errno.h>
  15 #include <linux/sched.h>
  16 #include <linux/smp.h>
  17 #include <linux/slab.h>
  18 #include <asm/cacheflush.h>
  19 #include <asm/hazards.h>
  20 #include <asm/tlbflush.h>
  21 #ifdef CONFIG_MIPS_MT_SMTC
  22 #include <asm/mipsmtregs.h>
  23 #include <asm/smtc.h>
  24 #endif /* SMTC */
  25 #include <asm-generic/mm_hooks.h>
  26
  27 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  28
  29 #define TLBMISS_HANDLER_SETUP_PGD(pgd)                                  \
  30 do {                                                                    \
  31         void (*tlbmiss_handler_setup_pgd)(unsigned long);               \
  32         extern u32 tlbmiss_handler_setup_pgd_array[16];                 \
  33                                                                         \
  34         tlbmiss_handler_setup_pgd =                                     \
  35                 (__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \
  36         tlbmiss_handler_setup_pgd((unsigned long)(pgd));                \
  37 } while (0)
  38
  39 #define TLBMISS_HANDLER_SETUP()                                         \
  40         do {                                                            \
  41                 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);              \
  42                 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
  43         } while (0)
  44
  45 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
  46
  47 /*
  48  * For the fast tlb miss handlers, we keep a per cpu array of pointers
  49  * to the current pgd for each processor. Also, the proc. id is stuffed
  50  * into the context register.
  51  */
  52 extern unsigned long pgd_current[];
  53
  54 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
  55         pgd_current[smp_processor_id()] = (unsigned long)(pgd)
  56
  57 #ifdef CONFIG_32BIT
  58 #define TLBMISS_HANDLER_SETUP()                                         \
  59         write_c0_context((unsigned long) smp_processor_id() << 25);     \
  60         back_to_back_c0_hazard();                                       \
  61         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
  62 #endif
  63 #ifdef CONFIG_64BIT
  64 #define TLBMISS_HANDLER_SETUP()                                         \
  65         write_c0_context((unsigned long) smp_processor_id() << 26);     \
  66         back_to_back_c0_hazard();                                       \
  67         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
  68 #endif
  69 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
  70 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
  71
  72 #define ASID_INC        0x40
  73 #define ASID_MASK       0xfc0
  74
  75 #elif defined(CONFIG_CPU_R8000)
  76
  77 #define ASID_INC        0x10
  78 #define ASID_MASK       0xff0
  79
  80 #elif defined(CONFIG_MIPS_MT_SMTC)
  81
  82 #define ASID_INC        0x1
  83 extern unsigned long smtc_asid_mask;
  84 #define ASID_MASK       (smtc_asid_mask)
  85 #define HW_ASID_MASK    0xff
  86 /* End SMTC/34K debug hack */
  87 #else /* FIXME: not correct for R6000 */
  88
  89 #define ASID_INC        0x1
  90 #define ASID_MASK       0xff
  91
  92 #endif
  93
  94 #define cpu_context(cpu, mm)    ((mm)->context.asid[cpu])
  95 #define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) & ASID_MASK)
  96 #define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
  97
  98 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  99 {
 100 }
 101
 102 /*
 103  *  All unused by hardware upper bits will be considered
 104  *  as a software asid extension.
 105  */
 106 #define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
 107 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
 108
 109 #ifndef CONFIG_MIPS_MT_SMTC
 110 /* Normal, classic MIPS get_new_mmu_context */
 111 static inline void
 112 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
 113 {
 114         unsigned long asid = asid_cache(cpu);
 115
 116         if (! ((asid += ASID_INC) & ASID_MASK) ) {
 117                 if (cpu_has_vtag_icache)
 118                         flush_icache_all();
 119                 local_flush_tlb_all();  /* start new asid cycle */
 120                 if (!asid)              /* fix version if needed */
 121                         asid = ASID_FIRST_VERSION;
 122         }
 123         cpu_context(cpu, mm) = asid_cache(cpu) = asid;
 124 }
 125
 126 #else /* CONFIG_MIPS_MT_SMTC */
 127
 128 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
 129
 130 #endif /* CONFIG_MIPS_MT_SMTC */
 131
 132 /*
 133  * Initialize the context related info for a new mm_struct
 134  * instance.
 135  */
 136 static inline int
 137 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 138 {
 139         int i;
 140
 141         for_each_possible_cpu(i)
 142                 cpu_context(i, mm) = 0;
 143
 144         return 0;
 145 }
 146
 147 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 148                              struct task_struct *tsk)
 149 {
 150         unsigned int cpu = smp_processor_id();
 151         unsigned long flags;
 152 #ifdef CONFIG_MIPS_MT_SMTC
 153         unsigned long oldasid;
 154         unsigned long mtflags;
 155         int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
 156         local_irq_save(flags);
 157         mtflags = dvpe();
 158 #else /* Not SMTC */
 159         local_irq_save(flags);
 160 #endif /* CONFIG_MIPS_MT_SMTC */
 161
 162         /* Check if our ASID is of an older version and thus invalid */
 163         if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
 164                 get_new_mmu_context(next, cpu);
 165 #ifdef CONFIG_MIPS_MT_SMTC
 166         /*
 167          * If the EntryHi ASID being replaced happens to be
 168          * the value flagged at ASID recycling time as having
 169          * an extended life, clear the bit showing it being
 170          * in use by this "CPU", and if that's the last bit,
 171          * free up the ASID value for use and flush any old
 172          * instances of it from the TLB.
 173          */
 174         oldasid = (read_c0_entryhi() & ASID_MASK);
 175         if(smtc_live_asid[mytlb][oldasid]) {
 176                 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
 177                 if(smtc_live_asid[mytlb][oldasid] == 0)
 178                         smtc_flush_tlb_asid(oldasid);
 179         }
 180         /*
 181          * Tread softly on EntryHi, and so long as we support
 182          * having ASID_MASK smaller than the hardware maximum,
 183          * make sure no "soft" bits become "hard"...
 184          */
 185         write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
 186                          cpu_asid(cpu, next));
 187         ehb(); /* Make sure it propagates to TCStatus */
 188         evpe(mtflags);
 189 #else
 190         write_c0_entryhi(cpu_asid(cpu, next));
 191 #endif /* CONFIG_MIPS_MT_SMTC */
 192         TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 193
 194         /*
 195          * Mark current->active_mm as not "active" anymore.
 196          * We don't want to mislead possible IPI tlb flush routines.
 197          */
 198         cpumask_clear_cpu(cpu, mm_cpumask(prev));
 199         cpumask_set_cpu(cpu, mm_cpumask(next));
 200
 201         local_irq_restore(flags);
 202 }
 203
 204 /*
 205  * Destroy context related info for an mm_struct that is about
 206  * to be put to rest.
 207  */
 208 static inline void destroy_context(struct mm_struct *mm)
 209 {
 210 }
 211
 212 #define deactivate_mm(tsk, mm)  do { } while (0)
 213
 214 /*
 215  * After we have set current->mm to a new value, this activates
 216  * the context for the new mm so we see the new mappings.
 217  */
 218 static inline void
 219 activate_mm(struct mm_struct *prev, struct mm_struct *next)
 220 {
 221         unsigned long flags;
 222         unsigned int cpu = smp_processor_id();
 223
 224 #ifdef CONFIG_MIPS_MT_SMTC
 225         unsigned long oldasid;
 226         unsigned long mtflags;
 227         int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
 228 #endif /* CONFIG_MIPS_MT_SMTC */
 229
 230         local_irq_save(flags);
 231
 232         /* Unconditionally get a new ASID.  */
 233         get_new_mmu_context(next, cpu);
 234
 235 #ifdef CONFIG_MIPS_MT_SMTC
 236         /* See comments for similar code above */
 237         mtflags = dvpe();
 238         oldasid = read_c0_entryhi() & ASID_MASK;
 239         if(smtc_live_asid[mytlb][oldasid]) {
 240                 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
 241                 if(smtc_live_asid[mytlb][oldasid] == 0)
 242                          smtc_flush_tlb_asid(oldasid);
 243         }
 244         /* See comments for similar code above */
 245         write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
 246                          cpu_asid(cpu, next));
 247         ehb(); /* Make sure it propagates to TCStatus */
 248         evpe(mtflags);
 249 #else
 250         write_c0_entryhi(cpu_asid(cpu, next));
 251 #endif /* CONFIG_MIPS_MT_SMTC */
 252         TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 253
 254         /* mark mmu ownership change */
 255         cpumask_clear_cpu(cpu, mm_cpumask(prev));
 256         cpumask_set_cpu(cpu, mm_cpumask(next));
 257
 258         local_irq_restore(flags);
 259 }
 260
 261 /*
 262  * If mm is currently active_mm, we can't really drop it.  Instead,
 263  * we will get a new one for it.
 264  */
 265 static inline void
 266 drop_mmu_context(struct mm_struct *mm, unsigned cpu)
 267 {
 268         unsigned long flags;
 269 #ifdef CONFIG_MIPS_MT_SMTC
 270         unsigned long oldasid;
 271         /* Can't use spinlock because called from TLB flush within DVPE */
 272         unsigned int prevvpe;
 273         int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
 274 #endif /* CONFIG_MIPS_MT_SMTC */
 275
 276         local_irq_save(flags);
 277
 278         if (cpumask_test_cpu(cpu, mm_cpumask(mm)))  {
 279                 get_new_mmu_context(mm, cpu);
 280 #ifdef CONFIG_MIPS_MT_SMTC
 281                 /* See comments for similar code above */
 282                 prevvpe = dvpe();
 283                 oldasid = (read_c0_entryhi() & ASID_MASK);
 284                 if (smtc_live_asid[mytlb][oldasid]) {
 285                         smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
 286                         if(smtc_live_asid[mytlb][oldasid] == 0)
 287                                 smtc_flush_tlb_asid(oldasid);
 288                 }
 289                 /* See comments for similar code above */
 290                 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
 291                                 | cpu_asid(cpu, mm));
 292                 ehb(); /* Make sure it propagates to TCStatus */
 293                 evpe(prevvpe);
 294 #else /* not CONFIG_MIPS_MT_SMTC */
 295                 write_c0_entryhi(cpu_asid(cpu, mm));
 296 #endif /* CONFIG_MIPS_MT_SMTC */
 297         } else {
 298                 /* will get a new context next time */
 299 #ifndef CONFIG_MIPS_MT_SMTC
 300                 cpu_context(cpu, mm) = 0;
 301 #else /* SMTC */
 302                 int i;
 303
 304                 /* SMTC shares the TLB (and ASIDs) across VPEs */
 305                 for_each_online_cpu(i) {
 306                     if((smtc_status & SMTC_TLB_SHARED)
 307                     || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
 308                         cpu_context(i, mm) = 0;
 309                 }
 310 #endif /* CONFIG_MIPS_MT_SMTC */
 311         }
 312         local_irq_restore(flags);
 313 }
 314
 315 #endif /* _ASM_MMU_CONTEXT_H */