arch/mips/alchemy/devboards/pb1500.c

   1 /*
   2  * Pb1500 board support.
   3  *
   4  * Copyright (C) 2009 Manuel Lauss
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/gpio.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/platform_device.h>
  27 #include <asm/mach-au1x00/au1000.h>
  28 #include <asm/mach-db1x00/bcsr.h>
  29 #include <prom.h>
  30 #include "platform.h"
  31
  32 const char *get_system_type(void)
  33 {
  34         return "PB1500";
  35 }
  36
  37 void __init board_setup(void)
  38 {
  39         u32 pin_func;
  40         u32 sys_freqctrl, sys_clksrc;
  41
  42         bcsr_init(DB1000_BCSR_PHYS_ADDR,
  43                   DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
  44
  45         sys_clksrc = sys_freqctrl = pin_func = 0;
  46         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  47         au_writel(8, SYS_AUXPLL);
  48         alchemy_gpio1_input_enable();
  49         udelay(100);
  50
  51         /* GPIO201 is input for PCMCIA card detect */
  52         /* GPIO203 is input for PCMCIA interrupt request */
  53         alchemy_gpio_direction_input(201);
  54         alchemy_gpio_direction_input(203);
  55
  56 #if IS_ENABLED(CONFIG_USB_OHCI_HCD)
  57
  58         /* Zero and disable FREQ2 */
  59         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  60         sys_freqctrl &= ~0xFFF00000;
  61         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  62
  63         /* zero and disable USBH/USBD clocks */
  64         sys_clksrc = au_readl(SYS_CLKSRC);
  65         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  66                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  67         au_writel(sys_clksrc, SYS_CLKSRC);
  68
  69         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  70         sys_freqctrl &= ~0xFFF00000;
  71
  72         sys_clksrc = au_readl(SYS_CLKSRC);
  73         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  74                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  75
  76         /* FREQ2 = aux/2 = 48 MHz */
  77         sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
  78         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  79
  80         /*
  81          * Route 48MHz FREQ2 into USB Host and/or Device
  82          */
  83         sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
  84         au_writel(sys_clksrc, SYS_CLKSRC);
  85
  86         pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
  87         /* 2nd USB port is USB host */
  88         pin_func |= SYS_PF_USB;
  89         au_writel(pin_func, SYS_PINFUNC);
  90 #endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
  91
  92 #ifdef CONFIG_PCI
  93         {
  94                 void __iomem *base =
  95                                 (void __iomem *)KSEG1ADDR(AU1500_PCI_PHYS_ADDR);
  96                 /* Setup PCI bus controller */
  97                 __raw_writel(0x00003fff, base + PCI_REG_CMEM);
  98                 __raw_writel(0xf0000000, base + PCI_REG_MWMASK_DEV);
  99                 __raw_writel(0, base + PCI_REG_MWBASE_REV_CCL);
 100                 __raw_writel(0x02a00356, base + PCI_REG_STATCMD);
 101                 __raw_writel(0x00003c04, base + PCI_REG_PARAM);
 102                 __raw_writel(0x00000008, base + PCI_REG_MBAR);
 103                 wmb();
 104         }
 105 #endif
 106
 107         /* Enable sys bus clock divider when IDLE state or no bus activity. */
 108         au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 109
 110         /* Enable the RTC if not already enabled */
 111         if (!(au_readl(0xac000028) & 0x20)) {
 112                 printk(KERN_INFO "enabling clock ...\n");
 113                 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
 114         }
 115         /* Put the clock in BCD mode */
 116         if (au_readl(0xac00002c) & 0x4) { /* reg B */
 117                 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
 118                 au_sync();
 119         }
 120 }
 121
 122 /******************************************************************************/
 123
 124 static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 125 {
 126         if ((slot < 12) || (slot > 13) || pin == 0)
 127                 return -1;
 128         if (slot == 12)
 129                 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
 130         if (slot == 13) {
 131                 switch (pin) {
 132                 case 1: return AU1500_PCI_INTA;
 133                 case 2: return AU1500_PCI_INTB;
 134                 case 3: return AU1500_PCI_INTC;
 135                 case 4: return AU1500_PCI_INTD;
 136                 }
 137         }
 138         return -1;
 139 }
 140
 141 static struct resource alchemy_pci_host_res[] = {
 142         [0] = {
 143                 .start  = AU1500_PCI_PHYS_ADDR,
 144                 .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
 145                 .flags  = IORESOURCE_MEM,
 146         },
 147 };
 148
 149 static struct alchemy_pci_platdata pb1500_pci_pd = {
 150         .board_map_irq  = pb1500_map_pci_irq,
 151         .pci_cfg_set    = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
 152                           PCI_CONFIG_CH |
 153 #if defined(__MIPSEB__)
 154                           PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
 155 #else
 156                           0,
 157 #endif
 158 };
 159
 160 static struct platform_device pb1500_pci_host = {
 161         .dev.platform_data = &pb1500_pci_pd,
 162         .name           = "alchemy-pci",
 163         .id             = 0,
 164         .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
 165         .resource       = alchemy_pci_host_res,
 166 };
 167
 168 static int __init pb1500_dev_init(void)
 169 {
 170         int swapped;
 171
 172         irq_set_irq_type(AU1500_GPIO9_INT,   IRQF_TRIGGER_LOW);   /* CD0# */
 173         irq_set_irq_type(AU1500_GPIO10_INT,  IRQF_TRIGGER_LOW);  /* CARD0 */
 174         irq_set_irq_type(AU1500_GPIO11_INT,  IRQF_TRIGGER_LOW);  /* STSCHG0# */
 175         irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
 176         irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
 177         irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
 178         irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
 179         irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
 180
 181         /* PCMCIA. single socket, identical to Pb1100 */
 182         db1x_register_pcmcia_socket(
 183                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 184                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 185                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 186                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 187                 AU1000_PCMCIA_IO_PHYS_ADDR,
 188                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 189                 AU1500_GPIO11_INT, AU1500_GPIO9_INT,     /* card / insert */
 190                 /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
 191
 192         swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
 193         db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
 194         platform_device_register(&pb1500_pci_host);
 195
 196         return 0;
 197 }
 198 arch_initcall(pb1500_dev_init);