4 * Exposes all configurable internal clock sources to the clk framework.
7 * - Root source, usually 12MHz supplied by an external crystal
8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
11 * - 6 clock dividers with:
12 * * selectable source [one of the PLLs],
13 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14 * or [1 .. 256 in steps of 1] (Au1300),
15 * * can be enabled individually.
17 * - up to 6 "internal" (fixed) consumers which:
18 * * take either AUXPLL or one of the above 6 dividers as input,
19 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20 * * can be disabled separately.
23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24 * depends on board design and should be set by bootloader, read-only.
25 * - peripheral clock: half the rate of sysbus clock, source for a lot
26 * of peripheral blocks, read-only.
27 * - memory clock: clk rate to main memory chips, depends on board
28 * design and is read-only,
29 * - lrclk: the static bus clock signal for synchronous operation.
30 * depends on board design, must be set by bootloader,
31 * but may be required to correctly configure devices attached to
32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33 * later models it's called RCLK.
36 #include <linux/init.h>
38 #include <linux/clk-provider.h>
39 #include <linux/clkdev.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/types.h>
43 #include <asm/mach-au1x00/au1000.h>
45 /* Base clock: 12MHz is the default in all databooks, and I haven't
46 * found any board yet which uses a different rate.
48 #define ALCHEMY_ROOTCLK_RATE 12000000
51 * the internal sources which can be driven by the PLLs and dividers.
52 * Names taken from the databooks, refer to them for more information,
53 * especially which ones are share a clock line.
55 static const char * const alchemy_au1300_intclknames
[] = {
56 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
60 static const char * const alchemy_au1200_intclknames
[] = {
61 "lcd_intclk", NULL
, NULL
, NULL
, "EXTCLK0", "EXTCLK1"
64 static const char * const alchemy_au1550_intclknames
[] = {
65 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
69 static const char * const alchemy_au1100_intclknames
[] = {
70 "usb_clk", "lcd_intclk", NULL
, "i2s_clk", "EXTCLK0", "EXTCLK1"
73 static const char * const alchemy_au1500_intclknames
[] = {
74 NULL
, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
77 static const char * const alchemy_au1000_intclknames
[] = {
78 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
82 /* aliases for a few on-chip sources which are either shared
83 * or have gone through name changes.
85 static struct clk_aliastable
{
89 } alchemy_clk_aliases
[] __initdata
= {
90 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
91 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
92 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
93 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
94 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
95 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550
},
96 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550
},
97 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200
},
98 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200
},
99 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
100 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
101 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
102 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
107 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
109 /* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
110 static spinlock_t alchemy_clk_fg0_lock
;
111 static spinlock_t alchemy_clk_fg1_lock
;
112 static spinlock_t alchemy_clk_csrc_lock
;
114 /* CPU Core clock *****************************************************/
116 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw
*hw
,
117 unsigned long parent_rate
)
122 * On early Au1000, sys_cpupll was write-only. Since these
123 * silicon versions of Au1000 are not sold, we don't bend
124 * over backwards trying to determine the frequency.
126 if (unlikely(au1xxx_cpu_has_pll_wo()))
129 t
= alchemy_rdsys(AU1000_SYS_CPUPLL
) & 0x7f;
136 static struct clk_ops alchemy_clkops_cpu
= {
137 .recalc_rate
= alchemy_clk_cpu_recalc
,
140 static struct clk __init
*alchemy_clk_setup_cpu(const char *parent_name
,
143 struct clk_init_data id
;
146 h
= kzalloc(sizeof(*h
), GFP_KERNEL
);
148 return ERR_PTR(-ENOMEM
);
150 id
.name
= ALCHEMY_CPU_CLK
;
151 id
.parent_names
= &parent_name
;
153 id
.flags
= CLK_IS_BASIC
;
154 id
.ops
= &alchemy_clkops_cpu
;
157 return clk_register(NULL
, h
);
160 /* AUXPLLs ************************************************************/
162 struct alchemy_auxpll_clk
{
164 unsigned long reg
; /* au1300 has also AUXPLL2 */
165 int maxmult
; /* max multiplier */
167 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
169 static unsigned long alchemy_clk_aux_recalc(struct clk_hw
*hw
,
170 unsigned long parent_rate
)
172 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
174 return (alchemy_rdsys(a
->reg
) & 0xff) * parent_rate
;
177 static int alchemy_clk_aux_setr(struct clk_hw
*hw
,
179 unsigned long parent_rate
)
181 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
182 unsigned long d
= rate
;
189 /* minimum is 84MHz, max is 756-1032 depending on variant */
190 if (((d
< 7) && (d
!= 0)) || (d
> a
->maxmult
))
193 alchemy_wrsys(d
, a
->reg
);
197 static long alchemy_clk_aux_roundr(struct clk_hw
*hw
,
199 unsigned long *parent_rate
)
201 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
204 if (!rate
|| !*parent_rate
)
207 mult
= rate
/ (*parent_rate
);
209 if (mult
&& (mult
< 7))
211 if (mult
> a
->maxmult
)
214 return (*parent_rate
) * mult
;
217 static struct clk_ops alchemy_clkops_aux
= {
218 .recalc_rate
= alchemy_clk_aux_recalc
,
219 .set_rate
= alchemy_clk_aux_setr
,
220 .round_rate
= alchemy_clk_aux_roundr
,
223 static struct clk __init
*alchemy_clk_setup_aux(const char *parent_name
,
224 char *name
, int maxmult
,
227 struct clk_init_data id
;
229 struct alchemy_auxpll_clk
*a
;
231 a
= kzalloc(sizeof(*a
), GFP_KERNEL
);
233 return ERR_PTR(-ENOMEM
);
236 id
.parent_names
= &parent_name
;
238 id
.flags
= CLK_GET_RATE_NOCACHE
;
239 id
.ops
= &alchemy_clkops_aux
;
242 a
->maxmult
= maxmult
;
245 c
= clk_register(NULL
, &a
->hw
);
247 clk_register_clkdev(c
, name
, NULL
);
254 /* sysbus_clk *********************************************************/
256 static struct clk __init
*alchemy_clk_setup_sysbus(const char *pn
)
258 unsigned long v
= (alchemy_rdsys(AU1000_SYS_POWERCTRL
) & 3) + 2;
261 c
= clk_register_fixed_factor(NULL
, ALCHEMY_SYSBUS_CLK
,
264 clk_register_clkdev(c
, ALCHEMY_SYSBUS_CLK
, NULL
);
268 /* Peripheral Clock ***************************************************/
270 static struct clk __init
*alchemy_clk_setup_periph(const char *pn
)
272 /* Peripheral clock runs at half the rate of sysbus clk */
275 c
= clk_register_fixed_factor(NULL
, ALCHEMY_PERIPH_CLK
,
278 clk_register_clkdev(c
, ALCHEMY_PERIPH_CLK
, NULL
);
282 /* mem clock **********************************************************/
284 static struct clk __init
*alchemy_clk_setup_mem(const char *pn
, int ct
)
286 void __iomem
*addr
= IOMEM(AU1000_MEM_PHYS_ADDR
);
292 case ALCHEMY_CPU_AU1550
:
293 case ALCHEMY_CPU_AU1200
:
294 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
295 div
= (v
& (1 << 15)) ? 1 : 2;
297 case ALCHEMY_CPU_AU1300
:
298 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
299 div
= (v
& (1 << 31)) ? 1 : 2;
301 case ALCHEMY_CPU_AU1000
:
302 case ALCHEMY_CPU_AU1500
:
303 case ALCHEMY_CPU_AU1100
:
309 c
= clk_register_fixed_factor(NULL
, ALCHEMY_MEM_CLK
, pn
,
312 clk_register_clkdev(c
, ALCHEMY_MEM_CLK
, NULL
);
316 /* lrclk: external synchronous static bus clock ***********************/
318 static struct clk __init
*alchemy_clk_setup_lrclk(const char *pn
)
320 /* MEM_STCFG0[15:13] = divisor.
321 * L/RCLK = periph_clk / (divisor + 1)
322 * On Au1000, Au1500, Au1100 it's called LCLK,
323 * on later models it's called RCLK, but it's the same thing.
326 unsigned long v
= alchemy_rdsmem(AU1000_MEM_STCFG0
) >> 13;
329 c
= clk_register_fixed_factor(NULL
, ALCHEMY_LR_CLK
,
332 clk_register_clkdev(c
, ALCHEMY_LR_CLK
, NULL
);
336 /* Clock dividers and muxes *******************************************/
338 /* data for fgen and csrc mux-dividers */
339 struct alchemy_fgcs_clk
{
341 spinlock_t
*reglock
; /* register lock */
342 unsigned long reg
; /* SYS_FREQCTRL0/1 */
343 int shift
; /* offset in register */
344 int parent
; /* parent before disable [Au1300] */
345 int isen
; /* is it enabled? */
346 int *dt
; /* dividertable for csrc */
348 #define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
350 static long alchemy_calc_div(unsigned long rate
, unsigned long prate
,
351 int scale
, int maxdiv
, unsigned long *rv
)
356 if ((prate
/ div1
) > rate
)
359 if (scale
== 2) { /* only div-by-multiple-of-2 possible */
361 div1
++; /* stay <=prate */
364 div2
= (div1
/ scale
) - 1; /* value to write to register */
371 div1
= ((div2
+ 1) * scale
);
375 static long alchemy_clk_fgcs_detr(struct clk_hw
*hw
, unsigned long rate
,
376 unsigned long *best_parent_rate
,
377 struct clk_hw
**best_parent_clk
,
378 int scale
, int maxdiv
)
380 struct clk
*pc
, *bpc
, *free
;
381 long tdv
, tpr
, pr
, nr
, br
, bpr
, diff
, lastdiff
;
390 /* look at the rates each enabled parent supplies and select
391 * the one that gets closest to but not over the requested rate.
393 for (j
= 0; j
< 7; j
++) {
394 pc
= clk_get_parent_by_index(hw
->clk
, j
);
398 /* if this parent is currently unused, remember it.
399 * XXX: we would actually want clk_has_active_children()
400 * but this is a good-enough approximation for now.
402 if (!__clk_is_prepared(pc
)) {
407 pr
= clk_get_rate(pc
);
411 /* what can hardware actually provide */
412 tdv
= alchemy_calc_div(rate
, pr
, scale
, maxdiv
, NULL
);
418 if (diff
< lastdiff
) {
428 /* if we couldn't get the exact rate we wanted from the enabled
429 * parents, maybe we can tell an available disabled/inactive one
430 * to give us a rate we can divide down to the requested rate.
432 if (lastdiff
&& free
) {
433 for (j
= (maxdiv
== 4) ? 1 : scale
; j
<= maxdiv
; j
+= scale
) {
437 pr
= clk_round_rate(free
, tpr
);
439 tdv
= alchemy_calc_div(rate
, pr
, scale
, maxdiv
, NULL
);
444 if (diff
< lastdiff
) {
455 *best_parent_rate
= bpr
;
456 *best_parent_clk
= __clk_get_hw(bpc
);
460 static int alchemy_clk_fgv1_en(struct clk_hw
*hw
)
462 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
463 unsigned long v
, flags
;
465 spin_lock_irqsave(c
->reglock
, flags
);
466 v
= alchemy_rdsys(c
->reg
);
467 v
|= (1 << 1) << c
->shift
;
468 alchemy_wrsys(v
, c
->reg
);
469 spin_unlock_irqrestore(c
->reglock
, flags
);
474 static int alchemy_clk_fgv1_isen(struct clk_hw
*hw
)
476 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
477 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 1);
482 static void alchemy_clk_fgv1_dis(struct clk_hw
*hw
)
484 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
485 unsigned long v
, flags
;
487 spin_lock_irqsave(c
->reglock
, flags
);
488 v
= alchemy_rdsys(c
->reg
);
489 v
&= ~((1 << 1) << c
->shift
);
490 alchemy_wrsys(v
, c
->reg
);
491 spin_unlock_irqrestore(c
->reglock
, flags
);
494 static int alchemy_clk_fgv1_setp(struct clk_hw
*hw
, u8 index
)
496 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
497 unsigned long v
, flags
;
499 spin_lock_irqsave(c
->reglock
, flags
);
500 v
= alchemy_rdsys(c
->reg
);
502 v
|= (1 << c
->shift
);
504 v
&= ~(1 << c
->shift
);
505 alchemy_wrsys(v
, c
->reg
);
506 spin_unlock_irqrestore(c
->reglock
, flags
);
511 static u8
alchemy_clk_fgv1_getp(struct clk_hw
*hw
)
513 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
515 return (alchemy_rdsys(c
->reg
) >> c
->shift
) & 1;
518 static int alchemy_clk_fgv1_setr(struct clk_hw
*hw
, unsigned long rate
,
519 unsigned long parent_rate
)
521 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
522 unsigned long div
, v
, flags
, ret
;
523 int sh
= c
->shift
+ 2;
525 if (!rate
|| !parent_rate
|| rate
> (parent_rate
/ 2))
527 ret
= alchemy_calc_div(rate
, parent_rate
, 2, 512, &div
);
528 spin_lock_irqsave(c
->reglock
, flags
);
529 v
= alchemy_rdsys(c
->reg
);
532 alchemy_wrsys(v
, c
->reg
);
533 spin_unlock_irqrestore(c
->reglock
, flags
);
538 static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw
*hw
,
539 unsigned long parent_rate
)
541 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
542 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 2);
544 v
= ((v
& 0xff) + 1) * 2;
545 return parent_rate
/ v
;
548 static long alchemy_clk_fgv1_detr(struct clk_hw
*hw
, unsigned long rate
,
549 unsigned long *best_parent_rate
,
550 struct clk_hw
**best_parent_clk
)
552 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
553 best_parent_clk
, 2, 512);
556 /* Au1000, Au1100, Au15x0, Au12x0 */
557 static struct clk_ops alchemy_clkops_fgenv1
= {
558 .recalc_rate
= alchemy_clk_fgv1_recalc
,
559 .determine_rate
= alchemy_clk_fgv1_detr
,
560 .set_rate
= alchemy_clk_fgv1_setr
,
561 .set_parent
= alchemy_clk_fgv1_setp
,
562 .get_parent
= alchemy_clk_fgv1_getp
,
563 .enable
= alchemy_clk_fgv1_en
,
564 .disable
= alchemy_clk_fgv1_dis
,
565 .is_enabled
= alchemy_clk_fgv1_isen
,
568 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk
*c
)
570 unsigned long v
= alchemy_rdsys(c
->reg
);
572 v
&= ~(3 << c
->shift
);
573 v
|= (c
->parent
& 3) << c
->shift
;
574 alchemy_wrsys(v
, c
->reg
);
578 static int alchemy_clk_fgv2_en(struct clk_hw
*hw
)
580 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
583 /* enable by setting the previous parent clock */
584 spin_lock_irqsave(c
->reglock
, flags
);
585 __alchemy_clk_fgv2_en(c
);
586 spin_unlock_irqrestore(c
->reglock
, flags
);
591 static int alchemy_clk_fgv2_isen(struct clk_hw
*hw
)
593 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
595 return ((alchemy_rdsys(c
->reg
) >> c
->shift
) & 3) != 0;
598 static void alchemy_clk_fgv2_dis(struct clk_hw
*hw
)
600 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
601 unsigned long v
, flags
;
603 spin_lock_irqsave(c
->reglock
, flags
);
604 v
= alchemy_rdsys(c
->reg
);
605 v
&= ~(3 << c
->shift
); /* set input mux to "disabled" state */
606 alchemy_wrsys(v
, c
->reg
);
608 spin_unlock_irqrestore(c
->reglock
, flags
);
611 static int alchemy_clk_fgv2_setp(struct clk_hw
*hw
, u8 index
)
613 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
616 spin_lock_irqsave(c
->reglock
, flags
);
617 c
->parent
= index
+ 1; /* value to write to register */
619 __alchemy_clk_fgv2_en(c
);
620 spin_unlock_irqrestore(c
->reglock
, flags
);
625 static u8
alchemy_clk_fgv2_getp(struct clk_hw
*hw
)
627 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
628 unsigned long flags
, v
;
630 spin_lock_irqsave(c
->reglock
, flags
);
632 spin_unlock_irqrestore(c
->reglock
, flags
);
636 /* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
637 * dividers behave exactly as on previous models (dividers are multiples
638 * of 2); with the bit set, dividers are multiples of 1, halving their
639 * range, but making them also much more flexible.
641 static int alchemy_clk_fgv2_setr(struct clk_hw
*hw
, unsigned long rate
,
642 unsigned long parent_rate
)
644 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
645 int sh
= c
->shift
+ 2;
646 unsigned long div
, v
, flags
, ret
;
648 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
651 v
= alchemy_rdsys(c
->reg
) & (1 << 30); /* test "scale" bit */
652 ret
= alchemy_calc_div(rate
, parent_rate
, v
? 1 : 2,
653 v
? 256 : 512, &div
);
655 spin_lock_irqsave(c
->reglock
, flags
);
656 v
= alchemy_rdsys(c
->reg
);
658 v
|= (div
& 0xff) << sh
;
659 alchemy_wrsys(v
, c
->reg
);
660 spin_unlock_irqrestore(c
->reglock
, flags
);
665 static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw
*hw
,
666 unsigned long parent_rate
)
668 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
669 int sh
= c
->shift
+ 2;
672 v
= alchemy_rdsys(c
->reg
);
673 t
= parent_rate
/ (((v
>> sh
) & 0xff) + 1);
674 if ((v
& (1 << 30)) == 0) /* test scale bit */
680 static long alchemy_clk_fgv2_detr(struct clk_hw
*hw
, unsigned long rate
,
681 unsigned long *best_parent_rate
,
682 struct clk_hw
**best_parent_clk
)
684 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
687 if (alchemy_rdsys(c
->reg
) & (1 << 30)) {
695 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
696 best_parent_clk
, scale
, maxdiv
);
699 /* Au1300 larger input mux, no separate disable bit, flexible divider */
700 static struct clk_ops alchemy_clkops_fgenv2
= {
701 .recalc_rate
= alchemy_clk_fgv2_recalc
,
702 .determine_rate
= alchemy_clk_fgv2_detr
,
703 .set_rate
= alchemy_clk_fgv2_setr
,
704 .set_parent
= alchemy_clk_fgv2_setp
,
705 .get_parent
= alchemy_clk_fgv2_getp
,
706 .enable
= alchemy_clk_fgv2_en
,
707 .disable
= alchemy_clk_fgv2_dis
,
708 .is_enabled
= alchemy_clk_fgv2_isen
,
711 static const char * const alchemy_clk_fgv1_parents
[] = {
712 ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
715 static const char * const alchemy_clk_fgv2_parents
[] = {
716 ALCHEMY_AUXPLL2_CLK
, ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
719 static const char * const alchemy_clk_fgen_names
[] = {
720 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
721 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
};
723 static int __init
alchemy_clk_init_fgens(int ctype
)
726 struct clk_init_data id
;
727 struct alchemy_fgcs_clk
*a
;
732 case ALCHEMY_CPU_AU1000
...ALCHEMY_CPU_AU1200
:
733 id
.ops
= &alchemy_clkops_fgenv1
;
734 id
.parent_names
= (const char **)alchemy_clk_fgv1_parents
;
737 case ALCHEMY_CPU_AU1300
:
738 id
.ops
= &alchemy_clkops_fgenv2
;
739 id
.parent_names
= (const char **)alchemy_clk_fgv2_parents
;
745 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
747 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
751 spin_lock_init(&alchemy_clk_fg0_lock
);
752 spin_lock_init(&alchemy_clk_fg1_lock
);
754 for (i
= 0; i
< 6; i
++) {
755 id
.name
= alchemy_clk_fgen_names
[i
];
756 a
->shift
= 10 * (i
< 3 ? i
: i
- 3);
758 a
->reg
= AU1000_SYS_FREQCTRL1
;
759 a
->reglock
= &alchemy_clk_fg1_lock
;
761 a
->reg
= AU1000_SYS_FREQCTRL0
;
762 a
->reglock
= &alchemy_clk_fg0_lock
;
765 /* default to first parent if bootloader has set
766 * the mux to disabled state.
768 if (ctype
== ALCHEMY_CPU_AU1300
) {
769 v
= alchemy_rdsys(a
->reg
);
770 a
->parent
= (v
>> a
->shift
) & 3;
779 c
= clk_register(NULL
, &a
->hw
);
783 clk_register_clkdev(c
, id
.name
, NULL
);
790 /* internal sources muxes *********************************************/
792 static int alchemy_clk_csrc_isen(struct clk_hw
*hw
)
794 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
795 unsigned long v
= alchemy_rdsys(c
->reg
);
797 return (((v
>> c
->shift
) >> 2) & 7) != 0;
800 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk
*c
)
802 unsigned long v
= alchemy_rdsys(c
->reg
);
804 v
&= ~((7 << 2) << c
->shift
);
805 v
|= ((c
->parent
& 7) << 2) << c
->shift
;
806 alchemy_wrsys(v
, c
->reg
);
810 static int alchemy_clk_csrc_en(struct clk_hw
*hw
)
812 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
815 /* enable by setting the previous parent clock */
816 spin_lock_irqsave(c
->reglock
, flags
);
817 __alchemy_clk_csrc_en(c
);
818 spin_unlock_irqrestore(c
->reglock
, flags
);
823 static void alchemy_clk_csrc_dis(struct clk_hw
*hw
)
825 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
826 unsigned long v
, flags
;
828 spin_lock_irqsave(c
->reglock
, flags
);
829 v
= alchemy_rdsys(c
->reg
);
830 v
&= ~((3 << 2) << c
->shift
); /* mux to "disabled" state */
831 alchemy_wrsys(v
, c
->reg
);
833 spin_unlock_irqrestore(c
->reglock
, flags
);
836 static int alchemy_clk_csrc_setp(struct clk_hw
*hw
, u8 index
)
838 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
841 spin_lock_irqsave(c
->reglock
, flags
);
842 c
->parent
= index
+ 1; /* value to write to register */
844 __alchemy_clk_csrc_en(c
);
845 spin_unlock_irqrestore(c
->reglock
, flags
);
850 static u8
alchemy_clk_csrc_getp(struct clk_hw
*hw
)
852 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
854 return c
->parent
- 1;
857 static unsigned long alchemy_clk_csrc_recalc(struct clk_hw
*hw
,
858 unsigned long parent_rate
)
860 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
861 unsigned long v
= (alchemy_rdsys(c
->reg
) >> c
->shift
) & 3;
863 return parent_rate
/ c
->dt
[v
];
866 static int alchemy_clk_csrc_setr(struct clk_hw
*hw
, unsigned long rate
,
867 unsigned long parent_rate
)
869 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
870 unsigned long d
, v
, flags
;
873 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
876 d
= (parent_rate
+ (rate
/ 2)) / rate
;
879 if ((d
== 3) && (c
->dt
[2] != 3))
882 for (i
= 0; i
< 4; i
++)
887 return -EINVAL
; /* oops */
889 spin_lock_irqsave(c
->reglock
, flags
);
890 v
= alchemy_rdsys(c
->reg
);
891 v
&= ~(3 << c
->shift
);
892 v
|= (i
& 3) << c
->shift
;
893 alchemy_wrsys(v
, c
->reg
);
894 spin_unlock_irqrestore(c
->reglock
, flags
);
899 static long alchemy_clk_csrc_detr(struct clk_hw
*hw
, unsigned long rate
,
900 unsigned long *best_parent_rate
,
901 struct clk_hw
**best_parent_clk
)
903 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
904 int scale
= c
->dt
[2] == 3 ? 1 : 2; /* au1300 check */
906 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
907 best_parent_clk
, scale
, 4);
910 static struct clk_ops alchemy_clkops_csrc
= {
911 .recalc_rate
= alchemy_clk_csrc_recalc
,
912 .determine_rate
= alchemy_clk_csrc_detr
,
913 .set_rate
= alchemy_clk_csrc_setr
,
914 .set_parent
= alchemy_clk_csrc_setp
,
915 .get_parent
= alchemy_clk_csrc_getp
,
916 .enable
= alchemy_clk_csrc_en
,
917 .disable
= alchemy_clk_csrc_dis
,
918 .is_enabled
= alchemy_clk_csrc_isen
,
921 static const char * const alchemy_clk_csrc_parents
[] = {
922 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK
,
923 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
924 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
928 static int alchemy_csrc_dt1
[] = { 1, 4, 1, 2 }; /* rest */
929 static int alchemy_csrc_dt2
[] = { 1, 4, 3, 2 }; /* Au1300 */
931 static int __init
alchemy_clk_setup_imux(int ctype
)
933 struct alchemy_fgcs_clk
*a
;
934 const char * const *names
;
935 struct clk_init_data id
;
940 id
.ops
= &alchemy_clkops_csrc
;
941 id
.parent_names
= (const char **)alchemy_clk_csrc_parents
;
943 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
945 dt
= alchemy_csrc_dt1
;
947 case ALCHEMY_CPU_AU1000
:
948 names
= alchemy_au1000_intclknames
;
950 case ALCHEMY_CPU_AU1500
:
951 names
= alchemy_au1500_intclknames
;
953 case ALCHEMY_CPU_AU1100
:
954 names
= alchemy_au1100_intclknames
;
956 case ALCHEMY_CPU_AU1550
:
957 names
= alchemy_au1550_intclknames
;
959 case ALCHEMY_CPU_AU1200
:
960 names
= alchemy_au1200_intclknames
;
962 case ALCHEMY_CPU_AU1300
:
963 dt
= alchemy_csrc_dt2
;
964 names
= alchemy_au1300_intclknames
;
970 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
974 spin_lock_init(&alchemy_clk_csrc_lock
);
977 for (i
= 0; i
< 6; i
++) {
983 a
->reg
= AU1000_SYS_CLKSRC
;
984 a
->reglock
= &alchemy_clk_csrc_lock
;
987 /* default to first parent clock if mux is initially
988 * set to disabled state.
990 v
= alchemy_rdsys(a
->reg
);
991 a
->parent
= ((v
>> a
->shift
) >> 2) & 7;
999 c
= clk_register(NULL
, &a
->hw
);
1003 clk_register_clkdev(c
, id
.name
, NULL
);
1012 /**********************************************************************/
1021 static int __init
alchemy_clk_init(void)
1023 int ctype
= alchemy_get_cputype(), ret
, i
;
1024 struct clk_aliastable
*t
= alchemy_clk_aliases
;
1027 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1028 c
= clk_register_fixed_rate(NULL
, ALCHEMY_ROOT_CLK
, NULL
,
1030 ALCHEMY_ROOTCLK_RATE
);
1033 /* CPU core clock */
1034 c
= alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK
, ctype
);
1037 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1038 i
= (ctype
== ALCHEMY_CPU_AU1300
) ? 84 : 63;
1039 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
, ALCHEMY_AUXPLL_CLK
,
1040 i
, AU1000_SYS_AUXPLL
);
1043 if (ctype
== ALCHEMY_CPU_AU1300
) {
1044 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
,
1045 ALCHEMY_AUXPLL2_CLK
, i
,
1046 AU1300_SYS_AUXPLL2
);
1050 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1051 c
= alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK
);
1054 /* peripheral clock: runs at half rate of sysbus clk */
1055 c
= alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK
);
1058 /* SDR/DDR memory clock */
1059 c
= alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK
, ctype
);
1062 /* L/RCLK: external static bus clock for synchronous mode */
1063 c
= alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK
);
1066 /* Frequency dividers 0-5 */
1067 ret
= alchemy_clk_init_fgens(ctype
);
1073 /* diving muxes for internal sources */
1074 ret
= alchemy_clk_setup_imux(ctype
);
1080 /* set up aliases drivers might look for */
1082 if (t
->cputype
== ctype
)
1083 clk_add_alias(t
->alias
, NULL
, t
->base
, NULL
);
1087 pr_info("Alchemy clocktree installed\n");
1093 postcore_initcall(alchemy_clk_init
);