4 * Exposes all configurable internal clock sources to the clk framework.
7 * - Root source, usually 12MHz supplied by an external crystal
8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
11 * - 6 clock dividers with:
12 * * selectable source [one of the PLLs],
13 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14 * or [1 .. 256 in steps of 1] (Au1300),
15 * * can be enabled individually.
17 * - up to 6 "internal" (fixed) consumers which:
18 * * take either AUXPLL or one of the above 6 dividers as input,
19 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20 * * can be disabled separately.
23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24 * depends on board design and should be set by bootloader, read-only.
25 * - peripheral clock: half the rate of sysbus clock, source for a lot
26 * of peripheral blocks, read-only.
27 * - memory clock: clk rate to main memory chips, depends on board
28 * design and is read-only,
29 * - lrclk: the static bus clock signal for synchronous operation.
30 * depends on board design, must be set by bootloader,
31 * but may be required to correctly configure devices attached to
32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33 * later models it's called RCLK.
36 #include <linux/init.h>
38 #include <linux/clk-provider.h>
39 #include <linux/clkdev.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/types.h>
43 #include <asm/mach-au1x00/au1000.h>
45 /* Base clock: 12MHz is the default in all databooks, and I haven't
46 * found any board yet which uses a different rate.
48 #define ALCHEMY_ROOTCLK_RATE 12000000
51 * the internal sources which can be driven by the PLLs and dividers.
52 * Names taken from the databooks, refer to them for more information,
53 * especially which ones are share a clock line.
55 static const char * const alchemy_au1300_intclknames
[] = {
56 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
60 static const char * const alchemy_au1200_intclknames
[] = {
61 "lcd_intclk", NULL
, NULL
, NULL
, "EXTCLK0", "EXTCLK1"
64 static const char * const alchemy_au1550_intclknames
[] = {
65 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
69 static const char * const alchemy_au1100_intclknames
[] = {
70 "usb_clk", "lcd_intclk", NULL
, "i2s_clk", "EXTCLK0", "EXTCLK1"
73 static const char * const alchemy_au1500_intclknames
[] = {
74 NULL
, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
77 static const char * const alchemy_au1000_intclknames
[] = {
78 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
82 /* aliases for a few on-chip sources which are either shared
83 * or have gone through name changes.
85 static struct clk_aliastable
{
89 } alchemy_clk_aliases
[] __initdata
= {
90 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
91 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
92 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
93 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
94 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
95 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550
},
96 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550
},
97 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200
},
98 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200
},
99 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
100 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
101 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
102 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
107 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
109 /* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
110 static spinlock_t alchemy_clk_fg0_lock
;
111 static spinlock_t alchemy_clk_fg1_lock
;
112 static spinlock_t alchemy_clk_csrc_lock
;
114 /* CPU Core clock *****************************************************/
116 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw
*hw
,
117 unsigned long parent_rate
)
122 * On early Au1000, sys_cpupll was write-only. Since these
123 * silicon versions of Au1000 are not sold, we don't bend
124 * over backwards trying to determine the frequency.
126 if (unlikely(au1xxx_cpu_has_pll_wo()))
129 t
= alchemy_rdsys(AU1000_SYS_CPUPLL
) & 0x7f;
130 if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300
)
138 void __init
alchemy_set_lpj(void)
140 preset_lpj
= alchemy_clk_cpu_recalc(NULL
, ALCHEMY_ROOTCLK_RATE
);
141 preset_lpj
/= 2 * HZ
;
144 static struct clk_ops alchemy_clkops_cpu
= {
145 .recalc_rate
= alchemy_clk_cpu_recalc
,
148 static struct clk __init
*alchemy_clk_setup_cpu(const char *parent_name
,
151 struct clk_init_data id
;
154 h
= kzalloc(sizeof(*h
), GFP_KERNEL
);
156 return ERR_PTR(-ENOMEM
);
158 id
.name
= ALCHEMY_CPU_CLK
;
159 id
.parent_names
= &parent_name
;
161 id
.flags
= CLK_IS_BASIC
;
162 id
.ops
= &alchemy_clkops_cpu
;
165 return clk_register(NULL
, h
);
168 /* AUXPLLs ************************************************************/
170 struct alchemy_auxpll_clk
{
172 unsigned long reg
; /* au1300 has also AUXPLL2 */
173 int maxmult
; /* max multiplier */
175 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
177 static unsigned long alchemy_clk_aux_recalc(struct clk_hw
*hw
,
178 unsigned long parent_rate
)
180 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
182 return (alchemy_rdsys(a
->reg
) & 0xff) * parent_rate
;
185 static int alchemy_clk_aux_setr(struct clk_hw
*hw
,
187 unsigned long parent_rate
)
189 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
190 unsigned long d
= rate
;
197 /* minimum is 84MHz, max is 756-1032 depending on variant */
198 if (((d
< 7) && (d
!= 0)) || (d
> a
->maxmult
))
201 alchemy_wrsys(d
, a
->reg
);
205 static long alchemy_clk_aux_roundr(struct clk_hw
*hw
,
207 unsigned long *parent_rate
)
209 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
212 if (!rate
|| !*parent_rate
)
215 mult
= rate
/ (*parent_rate
);
217 if (mult
&& (mult
< 7))
219 if (mult
> a
->maxmult
)
222 return (*parent_rate
) * mult
;
225 static struct clk_ops alchemy_clkops_aux
= {
226 .recalc_rate
= alchemy_clk_aux_recalc
,
227 .set_rate
= alchemy_clk_aux_setr
,
228 .round_rate
= alchemy_clk_aux_roundr
,
231 static struct clk __init
*alchemy_clk_setup_aux(const char *parent_name
,
232 char *name
, int maxmult
,
235 struct clk_init_data id
;
237 struct alchemy_auxpll_clk
*a
;
239 a
= kzalloc(sizeof(*a
), GFP_KERNEL
);
241 return ERR_PTR(-ENOMEM
);
244 id
.parent_names
= &parent_name
;
246 id
.flags
= CLK_GET_RATE_NOCACHE
;
247 id
.ops
= &alchemy_clkops_aux
;
250 a
->maxmult
= maxmult
;
253 c
= clk_register(NULL
, &a
->hw
);
255 clk_register_clkdev(c
, name
, NULL
);
262 /* sysbus_clk *********************************************************/
264 static struct clk __init
*alchemy_clk_setup_sysbus(const char *pn
)
266 unsigned long v
= (alchemy_rdsys(AU1000_SYS_POWERCTRL
) & 3) + 2;
269 c
= clk_register_fixed_factor(NULL
, ALCHEMY_SYSBUS_CLK
,
272 clk_register_clkdev(c
, ALCHEMY_SYSBUS_CLK
, NULL
);
276 /* Peripheral Clock ***************************************************/
278 static struct clk __init
*alchemy_clk_setup_periph(const char *pn
)
280 /* Peripheral clock runs at half the rate of sysbus clk */
283 c
= clk_register_fixed_factor(NULL
, ALCHEMY_PERIPH_CLK
,
286 clk_register_clkdev(c
, ALCHEMY_PERIPH_CLK
, NULL
);
290 /* mem clock **********************************************************/
292 static struct clk __init
*alchemy_clk_setup_mem(const char *pn
, int ct
)
294 void __iomem
*addr
= IOMEM(AU1000_MEM_PHYS_ADDR
);
300 case ALCHEMY_CPU_AU1550
:
301 case ALCHEMY_CPU_AU1200
:
302 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
303 div
= (v
& (1 << 15)) ? 1 : 2;
305 case ALCHEMY_CPU_AU1300
:
306 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
307 div
= (v
& (1 << 31)) ? 1 : 2;
309 case ALCHEMY_CPU_AU1000
:
310 case ALCHEMY_CPU_AU1500
:
311 case ALCHEMY_CPU_AU1100
:
317 c
= clk_register_fixed_factor(NULL
, ALCHEMY_MEM_CLK
, pn
,
320 clk_register_clkdev(c
, ALCHEMY_MEM_CLK
, NULL
);
324 /* lrclk: external synchronous static bus clock ***********************/
326 static struct clk __init
*alchemy_clk_setup_lrclk(const char *pn
, int t
)
328 /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
329 * otherwise lrclk=pclk/4.
330 * All other variants: MEM_STCFG0[15:13] = divisor.
331 * L/RCLK = periph_clk / (divisor + 1)
332 * On Au1000, Au1500, Au1100 it's called LCLK,
333 * on later models it's called RCLK, but it's the same thing.
336 unsigned long v
= alchemy_rdsmem(AU1000_MEM_STCFG0
);
339 case ALCHEMY_CPU_AU1000
:
340 case ALCHEMY_CPU_AU1500
:
341 v
= 4 + ((v
>> 11) & 1);
343 default: /* all other models */
344 v
= ((v
>> 13) & 7) + 1;
346 c
= clk_register_fixed_factor(NULL
, ALCHEMY_LR_CLK
,
349 clk_register_clkdev(c
, ALCHEMY_LR_CLK
, NULL
);
353 /* Clock dividers and muxes *******************************************/
355 /* data for fgen and csrc mux-dividers */
356 struct alchemy_fgcs_clk
{
358 spinlock_t
*reglock
; /* register lock */
359 unsigned long reg
; /* SYS_FREQCTRL0/1 */
360 int shift
; /* offset in register */
361 int parent
; /* parent before disable [Au1300] */
362 int isen
; /* is it enabled? */
363 int *dt
; /* dividertable for csrc */
365 #define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
367 static long alchemy_calc_div(unsigned long rate
, unsigned long prate
,
368 int scale
, int maxdiv
, unsigned long *rv
)
373 if ((prate
/ div1
) > rate
)
376 if (scale
== 2) { /* only div-by-multiple-of-2 possible */
378 div1
++; /* stay <=prate */
381 div2
= (div1
/ scale
) - 1; /* value to write to register */
388 div1
= ((div2
+ 1) * scale
);
392 static int alchemy_clk_fgcs_detr(struct clk_hw
*hw
,
393 struct clk_rate_request
*req
,
394 int scale
, int maxdiv
)
396 struct clk
*pc
, *bpc
, *free
;
397 long tdv
, tpr
, pr
, nr
, br
, bpr
, diff
, lastdiff
;
406 /* look at the rates each enabled parent supplies and select
407 * the one that gets closest to but not over the requested rate.
409 for (j
= 0; j
< 7; j
++) {
410 pc
= clk_get_parent_by_index(hw
->clk
, j
);
414 /* if this parent is currently unused, remember it.
415 * XXX: we would actually want clk_has_active_children()
416 * but this is a good-enough approximation for now.
418 if (!__clk_is_prepared(pc
)) {
423 pr
= clk_get_rate(pc
);
427 /* what can hardware actually provide */
428 tdv
= alchemy_calc_div(req
->rate
, pr
, scale
, maxdiv
, NULL
);
430 diff
= req
->rate
- nr
;
434 if (diff
< lastdiff
) {
444 /* if we couldn't get the exact rate we wanted from the enabled
445 * parents, maybe we can tell an available disabled/inactive one
446 * to give us a rate we can divide down to the requested rate.
448 if (lastdiff
&& free
) {
449 for (j
= (maxdiv
== 4) ? 1 : scale
; j
<= maxdiv
; j
+= scale
) {
453 pr
= clk_round_rate(free
, tpr
);
455 tdv
= alchemy_calc_div(req
->rate
, pr
, scale
, maxdiv
,
458 diff
= req
->rate
- nr
;
461 if (diff
< lastdiff
) {
472 req
->best_parent_rate
= bpr
;
473 req
->best_parent_hw
= __clk_get_hw(bpc
);
478 static int alchemy_clk_fgv1_en(struct clk_hw
*hw
)
480 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
481 unsigned long v
, flags
;
483 spin_lock_irqsave(c
->reglock
, flags
);
484 v
= alchemy_rdsys(c
->reg
);
485 v
|= (1 << 1) << c
->shift
;
486 alchemy_wrsys(v
, c
->reg
);
487 spin_unlock_irqrestore(c
->reglock
, flags
);
492 static int alchemy_clk_fgv1_isen(struct clk_hw
*hw
)
494 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
495 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 1);
500 static void alchemy_clk_fgv1_dis(struct clk_hw
*hw
)
502 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
503 unsigned long v
, flags
;
505 spin_lock_irqsave(c
->reglock
, flags
);
506 v
= alchemy_rdsys(c
->reg
);
507 v
&= ~((1 << 1) << c
->shift
);
508 alchemy_wrsys(v
, c
->reg
);
509 spin_unlock_irqrestore(c
->reglock
, flags
);
512 static int alchemy_clk_fgv1_setp(struct clk_hw
*hw
, u8 index
)
514 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
515 unsigned long v
, flags
;
517 spin_lock_irqsave(c
->reglock
, flags
);
518 v
= alchemy_rdsys(c
->reg
);
520 v
|= (1 << c
->shift
);
522 v
&= ~(1 << c
->shift
);
523 alchemy_wrsys(v
, c
->reg
);
524 spin_unlock_irqrestore(c
->reglock
, flags
);
529 static u8
alchemy_clk_fgv1_getp(struct clk_hw
*hw
)
531 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
533 return (alchemy_rdsys(c
->reg
) >> c
->shift
) & 1;
536 static int alchemy_clk_fgv1_setr(struct clk_hw
*hw
, unsigned long rate
,
537 unsigned long parent_rate
)
539 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
540 unsigned long div
, v
, flags
, ret
;
541 int sh
= c
->shift
+ 2;
543 if (!rate
|| !parent_rate
|| rate
> (parent_rate
/ 2))
545 ret
= alchemy_calc_div(rate
, parent_rate
, 2, 512, &div
);
546 spin_lock_irqsave(c
->reglock
, flags
);
547 v
= alchemy_rdsys(c
->reg
);
550 alchemy_wrsys(v
, c
->reg
);
551 spin_unlock_irqrestore(c
->reglock
, flags
);
556 static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw
*hw
,
557 unsigned long parent_rate
)
559 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
560 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 2);
562 v
= ((v
& 0xff) + 1) * 2;
563 return parent_rate
/ v
;
566 static int alchemy_clk_fgv1_detr(struct clk_hw
*hw
,
567 struct clk_rate_request
*req
)
569 return alchemy_clk_fgcs_detr(hw
, req
, 2, 512);
572 /* Au1000, Au1100, Au15x0, Au12x0 */
573 static struct clk_ops alchemy_clkops_fgenv1
= {
574 .recalc_rate
= alchemy_clk_fgv1_recalc
,
575 .determine_rate
= alchemy_clk_fgv1_detr
,
576 .set_rate
= alchemy_clk_fgv1_setr
,
577 .set_parent
= alchemy_clk_fgv1_setp
,
578 .get_parent
= alchemy_clk_fgv1_getp
,
579 .enable
= alchemy_clk_fgv1_en
,
580 .disable
= alchemy_clk_fgv1_dis
,
581 .is_enabled
= alchemy_clk_fgv1_isen
,
584 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk
*c
)
586 unsigned long v
= alchemy_rdsys(c
->reg
);
588 v
&= ~(3 << c
->shift
);
589 v
|= (c
->parent
& 3) << c
->shift
;
590 alchemy_wrsys(v
, c
->reg
);
594 static int alchemy_clk_fgv2_en(struct clk_hw
*hw
)
596 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
599 /* enable by setting the previous parent clock */
600 spin_lock_irqsave(c
->reglock
, flags
);
601 __alchemy_clk_fgv2_en(c
);
602 spin_unlock_irqrestore(c
->reglock
, flags
);
607 static int alchemy_clk_fgv2_isen(struct clk_hw
*hw
)
609 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
611 return ((alchemy_rdsys(c
->reg
) >> c
->shift
) & 3) != 0;
614 static void alchemy_clk_fgv2_dis(struct clk_hw
*hw
)
616 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
617 unsigned long v
, flags
;
619 spin_lock_irqsave(c
->reglock
, flags
);
620 v
= alchemy_rdsys(c
->reg
);
621 v
&= ~(3 << c
->shift
); /* set input mux to "disabled" state */
622 alchemy_wrsys(v
, c
->reg
);
624 spin_unlock_irqrestore(c
->reglock
, flags
);
627 static int alchemy_clk_fgv2_setp(struct clk_hw
*hw
, u8 index
)
629 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
632 spin_lock_irqsave(c
->reglock
, flags
);
633 c
->parent
= index
+ 1; /* value to write to register */
635 __alchemy_clk_fgv2_en(c
);
636 spin_unlock_irqrestore(c
->reglock
, flags
);
641 static u8
alchemy_clk_fgv2_getp(struct clk_hw
*hw
)
643 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
644 unsigned long flags
, v
;
646 spin_lock_irqsave(c
->reglock
, flags
);
648 spin_unlock_irqrestore(c
->reglock
, flags
);
652 /* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
653 * dividers behave exactly as on previous models (dividers are multiples
654 * of 2); with the bit set, dividers are multiples of 1, halving their
655 * range, but making them also much more flexible.
657 static int alchemy_clk_fgv2_setr(struct clk_hw
*hw
, unsigned long rate
,
658 unsigned long parent_rate
)
660 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
661 int sh
= c
->shift
+ 2;
662 unsigned long div
, v
, flags
, ret
;
664 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
667 v
= alchemy_rdsys(c
->reg
) & (1 << 30); /* test "scale" bit */
668 ret
= alchemy_calc_div(rate
, parent_rate
, v
? 1 : 2,
669 v
? 256 : 512, &div
);
671 spin_lock_irqsave(c
->reglock
, flags
);
672 v
= alchemy_rdsys(c
->reg
);
674 v
|= (div
& 0xff) << sh
;
675 alchemy_wrsys(v
, c
->reg
);
676 spin_unlock_irqrestore(c
->reglock
, flags
);
681 static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw
*hw
,
682 unsigned long parent_rate
)
684 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
685 int sh
= c
->shift
+ 2;
688 v
= alchemy_rdsys(c
->reg
);
689 t
= parent_rate
/ (((v
>> sh
) & 0xff) + 1);
690 if ((v
& (1 << 30)) == 0) /* test scale bit */
696 static int alchemy_clk_fgv2_detr(struct clk_hw
*hw
,
697 struct clk_rate_request
*req
)
699 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
702 if (alchemy_rdsys(c
->reg
) & (1 << 30)) {
710 return alchemy_clk_fgcs_detr(hw
, req
, scale
, maxdiv
);
713 /* Au1300 larger input mux, no separate disable bit, flexible divider */
714 static struct clk_ops alchemy_clkops_fgenv2
= {
715 .recalc_rate
= alchemy_clk_fgv2_recalc
,
716 .determine_rate
= alchemy_clk_fgv2_detr
,
717 .set_rate
= alchemy_clk_fgv2_setr
,
718 .set_parent
= alchemy_clk_fgv2_setp
,
719 .get_parent
= alchemy_clk_fgv2_getp
,
720 .enable
= alchemy_clk_fgv2_en
,
721 .disable
= alchemy_clk_fgv2_dis
,
722 .is_enabled
= alchemy_clk_fgv2_isen
,
725 static const char * const alchemy_clk_fgv1_parents
[] = {
726 ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
729 static const char * const alchemy_clk_fgv2_parents
[] = {
730 ALCHEMY_AUXPLL2_CLK
, ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
733 static const char * const alchemy_clk_fgen_names
[] = {
734 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
735 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
};
737 static int __init
alchemy_clk_init_fgens(int ctype
)
740 struct clk_init_data id
;
741 struct alchemy_fgcs_clk
*a
;
746 case ALCHEMY_CPU_AU1000
...ALCHEMY_CPU_AU1200
:
747 id
.ops
= &alchemy_clkops_fgenv1
;
748 id
.parent_names
= alchemy_clk_fgv1_parents
;
751 case ALCHEMY_CPU_AU1300
:
752 id
.ops
= &alchemy_clkops_fgenv2
;
753 id
.parent_names
= alchemy_clk_fgv2_parents
;
759 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
761 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
765 spin_lock_init(&alchemy_clk_fg0_lock
);
766 spin_lock_init(&alchemy_clk_fg1_lock
);
768 for (i
= 0; i
< 6; i
++) {
769 id
.name
= alchemy_clk_fgen_names
[i
];
770 a
->shift
= 10 * (i
< 3 ? i
: i
- 3);
772 a
->reg
= AU1000_SYS_FREQCTRL1
;
773 a
->reglock
= &alchemy_clk_fg1_lock
;
775 a
->reg
= AU1000_SYS_FREQCTRL0
;
776 a
->reglock
= &alchemy_clk_fg0_lock
;
779 /* default to first parent if bootloader has set
780 * the mux to disabled state.
782 if (ctype
== ALCHEMY_CPU_AU1300
) {
783 v
= alchemy_rdsys(a
->reg
);
784 a
->parent
= (v
>> a
->shift
) & 3;
793 c
= clk_register(NULL
, &a
->hw
);
797 clk_register_clkdev(c
, id
.name
, NULL
);
804 /* internal sources muxes *********************************************/
806 static int alchemy_clk_csrc_isen(struct clk_hw
*hw
)
808 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
809 unsigned long v
= alchemy_rdsys(c
->reg
);
811 return (((v
>> c
->shift
) >> 2) & 7) != 0;
814 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk
*c
)
816 unsigned long v
= alchemy_rdsys(c
->reg
);
818 v
&= ~((7 << 2) << c
->shift
);
819 v
|= ((c
->parent
& 7) << 2) << c
->shift
;
820 alchemy_wrsys(v
, c
->reg
);
824 static int alchemy_clk_csrc_en(struct clk_hw
*hw
)
826 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
829 /* enable by setting the previous parent clock */
830 spin_lock_irqsave(c
->reglock
, flags
);
831 __alchemy_clk_csrc_en(c
);
832 spin_unlock_irqrestore(c
->reglock
, flags
);
837 static void alchemy_clk_csrc_dis(struct clk_hw
*hw
)
839 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
840 unsigned long v
, flags
;
842 spin_lock_irqsave(c
->reglock
, flags
);
843 v
= alchemy_rdsys(c
->reg
);
844 v
&= ~((3 << 2) << c
->shift
); /* mux to "disabled" state */
845 alchemy_wrsys(v
, c
->reg
);
847 spin_unlock_irqrestore(c
->reglock
, flags
);
850 static int alchemy_clk_csrc_setp(struct clk_hw
*hw
, u8 index
)
852 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
855 spin_lock_irqsave(c
->reglock
, flags
);
856 c
->parent
= index
+ 1; /* value to write to register */
858 __alchemy_clk_csrc_en(c
);
859 spin_unlock_irqrestore(c
->reglock
, flags
);
864 static u8
alchemy_clk_csrc_getp(struct clk_hw
*hw
)
866 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
868 return c
->parent
- 1;
871 static unsigned long alchemy_clk_csrc_recalc(struct clk_hw
*hw
,
872 unsigned long parent_rate
)
874 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
875 unsigned long v
= (alchemy_rdsys(c
->reg
) >> c
->shift
) & 3;
877 return parent_rate
/ c
->dt
[v
];
880 static int alchemy_clk_csrc_setr(struct clk_hw
*hw
, unsigned long rate
,
881 unsigned long parent_rate
)
883 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
884 unsigned long d
, v
, flags
;
887 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
890 d
= (parent_rate
+ (rate
/ 2)) / rate
;
893 if ((d
== 3) && (c
->dt
[2] != 3))
896 for (i
= 0; i
< 4; i
++)
901 return -EINVAL
; /* oops */
903 spin_lock_irqsave(c
->reglock
, flags
);
904 v
= alchemy_rdsys(c
->reg
);
905 v
&= ~(3 << c
->shift
);
906 v
|= (i
& 3) << c
->shift
;
907 alchemy_wrsys(v
, c
->reg
);
908 spin_unlock_irqrestore(c
->reglock
, flags
);
913 static int alchemy_clk_csrc_detr(struct clk_hw
*hw
,
914 struct clk_rate_request
*req
)
916 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
917 int scale
= c
->dt
[2] == 3 ? 1 : 2; /* au1300 check */
919 return alchemy_clk_fgcs_detr(hw
, req
, scale
, 4);
922 static struct clk_ops alchemy_clkops_csrc
= {
923 .recalc_rate
= alchemy_clk_csrc_recalc
,
924 .determine_rate
= alchemy_clk_csrc_detr
,
925 .set_rate
= alchemy_clk_csrc_setr
,
926 .set_parent
= alchemy_clk_csrc_setp
,
927 .get_parent
= alchemy_clk_csrc_getp
,
928 .enable
= alchemy_clk_csrc_en
,
929 .disable
= alchemy_clk_csrc_dis
,
930 .is_enabled
= alchemy_clk_csrc_isen
,
933 static const char * const alchemy_clk_csrc_parents
[] = {
934 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK
,
935 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
936 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
940 static int alchemy_csrc_dt1
[] = { 1, 4, 1, 2 }; /* rest */
941 static int alchemy_csrc_dt2
[] = { 1, 4, 3, 2 }; /* Au1300 */
943 static int __init
alchemy_clk_setup_imux(int ctype
)
945 struct alchemy_fgcs_clk
*a
;
946 const char * const *names
;
947 struct clk_init_data id
;
952 id
.ops
= &alchemy_clkops_csrc
;
953 id
.parent_names
= alchemy_clk_csrc_parents
;
955 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
957 dt
= alchemy_csrc_dt1
;
959 case ALCHEMY_CPU_AU1000
:
960 names
= alchemy_au1000_intclknames
;
962 case ALCHEMY_CPU_AU1500
:
963 names
= alchemy_au1500_intclknames
;
965 case ALCHEMY_CPU_AU1100
:
966 names
= alchemy_au1100_intclknames
;
968 case ALCHEMY_CPU_AU1550
:
969 names
= alchemy_au1550_intclknames
;
971 case ALCHEMY_CPU_AU1200
:
972 names
= alchemy_au1200_intclknames
;
974 case ALCHEMY_CPU_AU1300
:
975 dt
= alchemy_csrc_dt2
;
976 names
= alchemy_au1300_intclknames
;
982 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
986 spin_lock_init(&alchemy_clk_csrc_lock
);
989 for (i
= 0; i
< 6; i
++) {
995 a
->reg
= AU1000_SYS_CLKSRC
;
996 a
->reglock
= &alchemy_clk_csrc_lock
;
999 /* default to first parent clock if mux is initially
1000 * set to disabled state.
1002 v
= alchemy_rdsys(a
->reg
);
1003 a
->parent
= ((v
>> a
->shift
) >> 2) & 7;
1011 c
= clk_register(NULL
, &a
->hw
);
1015 clk_register_clkdev(c
, id
.name
, NULL
);
1024 /**********************************************************************/
1033 static int __init
alchemy_clk_init(void)
1035 int ctype
= alchemy_get_cputype(), ret
, i
;
1036 struct clk_aliastable
*t
= alchemy_clk_aliases
;
1039 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1040 c
= clk_register_fixed_rate(NULL
, ALCHEMY_ROOT_CLK
, NULL
,
1042 ALCHEMY_ROOTCLK_RATE
);
1045 /* CPU core clock */
1046 c
= alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK
, ctype
);
1049 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1050 i
= (ctype
== ALCHEMY_CPU_AU1300
) ? 84 : 63;
1051 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
, ALCHEMY_AUXPLL_CLK
,
1052 i
, AU1000_SYS_AUXPLL
);
1055 if (ctype
== ALCHEMY_CPU_AU1300
) {
1056 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
,
1057 ALCHEMY_AUXPLL2_CLK
, i
,
1058 AU1300_SYS_AUXPLL2
);
1062 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1063 c
= alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK
);
1066 /* peripheral clock: runs at half rate of sysbus clk */
1067 c
= alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK
);
1070 /* SDR/DDR memory clock */
1071 c
= alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK
, ctype
);
1074 /* L/RCLK: external static bus clock for synchronous mode */
1075 c
= alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK
, ctype
);
1078 /* Frequency dividers 0-5 */
1079 ret
= alchemy_clk_init_fgens(ctype
);
1085 /* diving muxes for internal sources */
1086 ret
= alchemy_clk_setup_imux(ctype
);
1092 /* set up aliases drivers might look for */
1094 if (t
->cputype
== ctype
)
1095 clk_add_alias(t
->alias
, NULL
, t
->base
, NULL
);
1099 pr_info("Alchemy clocktree installed\n");
1105 postcore_initcall(alchemy_clk_init
);