4 * Exposes all configurable internal clock sources to the clk framework.
7 * - Root source, usually 12MHz supplied by an external crystal
8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
11 * - 6 clock dividers with:
12 * * selectable source [one of the PLLs],
13 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14 * or [1 .. 256 in steps of 1] (Au1300),
15 * * can be enabled individually.
17 * - up to 6 "internal" (fixed) consumers which:
18 * * take either AUXPLL or one of the above 6 dividers as input,
19 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20 * * can be disabled separately.
23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24 * depends on board design and should be set by bootloader, read-only.
25 * - peripheral clock: half the rate of sysbus clock, source for a lot
26 * of peripheral blocks, read-only.
27 * - memory clock: clk rate to main memory chips, depends on board
28 * design and is read-only,
29 * - lrclk: the static bus clock signal for synchronous operation.
30 * depends on board design, must be set by bootloader,
31 * but may be required to correctly configure devices attached to
32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33 * later models it's called RCLK.
36 #include <linux/init.h>
38 #include <linux/clk-provider.h>
39 #include <linux/clkdev.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/types.h>
43 #include <asm/mach-au1x00/au1000.h>
45 /* Base clock: 12MHz is the default in all databooks, and I haven't
46 * found any board yet which uses a different rate.
48 #define ALCHEMY_ROOTCLK_RATE 12000000
51 * the internal sources which can be driven by the PLLs and dividers.
52 * Names taken from the databooks, refer to them for more information,
53 * especially which ones are share a clock line.
55 static const char * const alchemy_au1300_intclknames
[] = {
56 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
60 static const char * const alchemy_au1200_intclknames
[] = {
61 "lcd_intclk", NULL
, NULL
, NULL
, "EXTCLK0", "EXTCLK1"
64 static const char * const alchemy_au1550_intclknames
[] = {
65 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
69 static const char * const alchemy_au1100_intclknames
[] = {
70 "usb_clk", "lcd_intclk", NULL
, "i2s_clk", "EXTCLK0", "EXTCLK1"
73 static const char * const alchemy_au1500_intclknames
[] = {
74 NULL
, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
77 static const char * const alchemy_au1000_intclknames
[] = {
78 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
82 /* aliases for a few on-chip sources which are either shared
83 * or have gone through name changes.
85 static struct clk_aliastable
{
89 } alchemy_clk_aliases
[] __initdata
= {
90 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
91 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
92 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100
},
93 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
94 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550
},
95 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550
},
96 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550
},
97 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200
},
98 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200
},
99 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
100 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300
},
101 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
102 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300
},
107 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
109 /* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
110 static spinlock_t alchemy_clk_fg0_lock
;
111 static spinlock_t alchemy_clk_fg1_lock
;
112 static spinlock_t alchemy_clk_csrc_lock
;
114 /* CPU Core clock *****************************************************/
116 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw
*hw
,
117 unsigned long parent_rate
)
122 * On early Au1000, sys_cpupll was write-only. Since these
123 * silicon versions of Au1000 are not sold, we don't bend
124 * over backwards trying to determine the frequency.
126 if (unlikely(au1xxx_cpu_has_pll_wo()))
129 t
= alchemy_rdsys(AU1000_SYS_CPUPLL
) & 0x7f;
136 void __init
alchemy_set_lpj(void)
138 preset_lpj
= alchemy_clk_cpu_recalc(NULL
, ALCHEMY_ROOTCLK_RATE
);
139 preset_lpj
/= 2 * HZ
;
142 static struct clk_ops alchemy_clkops_cpu
= {
143 .recalc_rate
= alchemy_clk_cpu_recalc
,
146 static struct clk __init
*alchemy_clk_setup_cpu(const char *parent_name
,
149 struct clk_init_data id
;
152 h
= kzalloc(sizeof(*h
), GFP_KERNEL
);
154 return ERR_PTR(-ENOMEM
);
156 id
.name
= ALCHEMY_CPU_CLK
;
157 id
.parent_names
= &parent_name
;
159 id
.flags
= CLK_IS_BASIC
;
160 id
.ops
= &alchemy_clkops_cpu
;
163 return clk_register(NULL
, h
);
166 /* AUXPLLs ************************************************************/
168 struct alchemy_auxpll_clk
{
170 unsigned long reg
; /* au1300 has also AUXPLL2 */
171 int maxmult
; /* max multiplier */
173 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
175 static unsigned long alchemy_clk_aux_recalc(struct clk_hw
*hw
,
176 unsigned long parent_rate
)
178 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
180 return (alchemy_rdsys(a
->reg
) & 0xff) * parent_rate
;
183 static int alchemy_clk_aux_setr(struct clk_hw
*hw
,
185 unsigned long parent_rate
)
187 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
188 unsigned long d
= rate
;
195 /* minimum is 84MHz, max is 756-1032 depending on variant */
196 if (((d
< 7) && (d
!= 0)) || (d
> a
->maxmult
))
199 alchemy_wrsys(d
, a
->reg
);
203 static long alchemy_clk_aux_roundr(struct clk_hw
*hw
,
205 unsigned long *parent_rate
)
207 struct alchemy_auxpll_clk
*a
= to_auxpll_clk(hw
);
210 if (!rate
|| !*parent_rate
)
213 mult
= rate
/ (*parent_rate
);
215 if (mult
&& (mult
< 7))
217 if (mult
> a
->maxmult
)
220 return (*parent_rate
) * mult
;
223 static struct clk_ops alchemy_clkops_aux
= {
224 .recalc_rate
= alchemy_clk_aux_recalc
,
225 .set_rate
= alchemy_clk_aux_setr
,
226 .round_rate
= alchemy_clk_aux_roundr
,
229 static struct clk __init
*alchemy_clk_setup_aux(const char *parent_name
,
230 char *name
, int maxmult
,
233 struct clk_init_data id
;
235 struct alchemy_auxpll_clk
*a
;
237 a
= kzalloc(sizeof(*a
), GFP_KERNEL
);
239 return ERR_PTR(-ENOMEM
);
242 id
.parent_names
= &parent_name
;
244 id
.flags
= CLK_GET_RATE_NOCACHE
;
245 id
.ops
= &alchemy_clkops_aux
;
248 a
->maxmult
= maxmult
;
251 c
= clk_register(NULL
, &a
->hw
);
253 clk_register_clkdev(c
, name
, NULL
);
260 /* sysbus_clk *********************************************************/
262 static struct clk __init
*alchemy_clk_setup_sysbus(const char *pn
)
264 unsigned long v
= (alchemy_rdsys(AU1000_SYS_POWERCTRL
) & 3) + 2;
267 c
= clk_register_fixed_factor(NULL
, ALCHEMY_SYSBUS_CLK
,
270 clk_register_clkdev(c
, ALCHEMY_SYSBUS_CLK
, NULL
);
274 /* Peripheral Clock ***************************************************/
276 static struct clk __init
*alchemy_clk_setup_periph(const char *pn
)
278 /* Peripheral clock runs at half the rate of sysbus clk */
281 c
= clk_register_fixed_factor(NULL
, ALCHEMY_PERIPH_CLK
,
284 clk_register_clkdev(c
, ALCHEMY_PERIPH_CLK
, NULL
);
288 /* mem clock **********************************************************/
290 static struct clk __init
*alchemy_clk_setup_mem(const char *pn
, int ct
)
292 void __iomem
*addr
= IOMEM(AU1000_MEM_PHYS_ADDR
);
298 case ALCHEMY_CPU_AU1550
:
299 case ALCHEMY_CPU_AU1200
:
300 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
301 div
= (v
& (1 << 15)) ? 1 : 2;
303 case ALCHEMY_CPU_AU1300
:
304 v
= __raw_readl(addr
+ AU1550_MEM_SDCONFIGB
);
305 div
= (v
& (1 << 31)) ? 1 : 2;
307 case ALCHEMY_CPU_AU1000
:
308 case ALCHEMY_CPU_AU1500
:
309 case ALCHEMY_CPU_AU1100
:
315 c
= clk_register_fixed_factor(NULL
, ALCHEMY_MEM_CLK
, pn
,
318 clk_register_clkdev(c
, ALCHEMY_MEM_CLK
, NULL
);
322 /* lrclk: external synchronous static bus clock ***********************/
324 static struct clk __init
*alchemy_clk_setup_lrclk(const char *pn
, int t
)
326 /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
327 * otherwise lrclk=pclk/4.
328 * All other variants: MEM_STCFG0[15:13] = divisor.
329 * L/RCLK = periph_clk / (divisor + 1)
330 * On Au1000, Au1500, Au1100 it's called LCLK,
331 * on later models it's called RCLK, but it's the same thing.
334 unsigned long v
= alchemy_rdsmem(AU1000_MEM_STCFG0
);
337 case ALCHEMY_CPU_AU1000
:
338 case ALCHEMY_CPU_AU1500
:
339 v
= 4 + ((v
>> 11) & 1);
341 default: /* all other models */
342 v
= ((v
>> 13) & 7) + 1;
344 c
= clk_register_fixed_factor(NULL
, ALCHEMY_LR_CLK
,
347 clk_register_clkdev(c
, ALCHEMY_LR_CLK
, NULL
);
351 /* Clock dividers and muxes *******************************************/
353 /* data for fgen and csrc mux-dividers */
354 struct alchemy_fgcs_clk
{
356 spinlock_t
*reglock
; /* register lock */
357 unsigned long reg
; /* SYS_FREQCTRL0/1 */
358 int shift
; /* offset in register */
359 int parent
; /* parent before disable [Au1300] */
360 int isen
; /* is it enabled? */
361 int *dt
; /* dividertable for csrc */
363 #define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
365 static long alchemy_calc_div(unsigned long rate
, unsigned long prate
,
366 int scale
, int maxdiv
, unsigned long *rv
)
371 if ((prate
/ div1
) > rate
)
374 if (scale
== 2) { /* only div-by-multiple-of-2 possible */
376 div1
++; /* stay <=prate */
379 div2
= (div1
/ scale
) - 1; /* value to write to register */
386 div1
= ((div2
+ 1) * scale
);
390 static long alchemy_clk_fgcs_detr(struct clk_hw
*hw
, unsigned long rate
,
391 unsigned long *best_parent_rate
,
392 struct clk_hw
**best_parent_clk
,
393 int scale
, int maxdiv
)
395 struct clk
*pc
, *bpc
, *free
;
396 long tdv
, tpr
, pr
, nr
, br
, bpr
, diff
, lastdiff
;
405 /* look at the rates each enabled parent supplies and select
406 * the one that gets closest to but not over the requested rate.
408 for (j
= 0; j
< 7; j
++) {
409 pc
= clk_get_parent_by_index(hw
->clk
, j
);
413 /* if this parent is currently unused, remember it.
414 * XXX: we would actually want clk_has_active_children()
415 * but this is a good-enough approximation for now.
417 if (!__clk_is_prepared(pc
)) {
422 pr
= clk_get_rate(pc
);
426 /* what can hardware actually provide */
427 tdv
= alchemy_calc_div(rate
, pr
, scale
, maxdiv
, NULL
);
433 if (diff
< lastdiff
) {
443 /* if we couldn't get the exact rate we wanted from the enabled
444 * parents, maybe we can tell an available disabled/inactive one
445 * to give us a rate we can divide down to the requested rate.
447 if (lastdiff
&& free
) {
448 for (j
= (maxdiv
== 4) ? 1 : scale
; j
<= maxdiv
; j
+= scale
) {
452 pr
= clk_round_rate(free
, tpr
);
454 tdv
= alchemy_calc_div(rate
, pr
, scale
, maxdiv
, NULL
);
459 if (diff
< lastdiff
) {
470 *best_parent_rate
= bpr
;
471 *best_parent_clk
= __clk_get_hw(bpc
);
475 static int alchemy_clk_fgv1_en(struct clk_hw
*hw
)
477 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
478 unsigned long v
, flags
;
480 spin_lock_irqsave(c
->reglock
, flags
);
481 v
= alchemy_rdsys(c
->reg
);
482 v
|= (1 << 1) << c
->shift
;
483 alchemy_wrsys(v
, c
->reg
);
484 spin_unlock_irqrestore(c
->reglock
, flags
);
489 static int alchemy_clk_fgv1_isen(struct clk_hw
*hw
)
491 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
492 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 1);
497 static void alchemy_clk_fgv1_dis(struct clk_hw
*hw
)
499 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
500 unsigned long v
, flags
;
502 spin_lock_irqsave(c
->reglock
, flags
);
503 v
= alchemy_rdsys(c
->reg
);
504 v
&= ~((1 << 1) << c
->shift
);
505 alchemy_wrsys(v
, c
->reg
);
506 spin_unlock_irqrestore(c
->reglock
, flags
);
509 static int alchemy_clk_fgv1_setp(struct clk_hw
*hw
, u8 index
)
511 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
512 unsigned long v
, flags
;
514 spin_lock_irqsave(c
->reglock
, flags
);
515 v
= alchemy_rdsys(c
->reg
);
517 v
|= (1 << c
->shift
);
519 v
&= ~(1 << c
->shift
);
520 alchemy_wrsys(v
, c
->reg
);
521 spin_unlock_irqrestore(c
->reglock
, flags
);
526 static u8
alchemy_clk_fgv1_getp(struct clk_hw
*hw
)
528 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
530 return (alchemy_rdsys(c
->reg
) >> c
->shift
) & 1;
533 static int alchemy_clk_fgv1_setr(struct clk_hw
*hw
, unsigned long rate
,
534 unsigned long parent_rate
)
536 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
537 unsigned long div
, v
, flags
, ret
;
538 int sh
= c
->shift
+ 2;
540 if (!rate
|| !parent_rate
|| rate
> (parent_rate
/ 2))
542 ret
= alchemy_calc_div(rate
, parent_rate
, 2, 512, &div
);
543 spin_lock_irqsave(c
->reglock
, flags
);
544 v
= alchemy_rdsys(c
->reg
);
547 alchemy_wrsys(v
, c
->reg
);
548 spin_unlock_irqrestore(c
->reglock
, flags
);
553 static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw
*hw
,
554 unsigned long parent_rate
)
556 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
557 unsigned long v
= alchemy_rdsys(c
->reg
) >> (c
->shift
+ 2);
559 v
= ((v
& 0xff) + 1) * 2;
560 return parent_rate
/ v
;
563 static long alchemy_clk_fgv1_detr(struct clk_hw
*hw
, unsigned long rate
,
564 unsigned long *best_parent_rate
,
565 struct clk_hw
**best_parent_clk
)
567 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
568 best_parent_clk
, 2, 512);
571 /* Au1000, Au1100, Au15x0, Au12x0 */
572 static struct clk_ops alchemy_clkops_fgenv1
= {
573 .recalc_rate
= alchemy_clk_fgv1_recalc
,
574 .determine_rate
= alchemy_clk_fgv1_detr
,
575 .set_rate
= alchemy_clk_fgv1_setr
,
576 .set_parent
= alchemy_clk_fgv1_setp
,
577 .get_parent
= alchemy_clk_fgv1_getp
,
578 .enable
= alchemy_clk_fgv1_en
,
579 .disable
= alchemy_clk_fgv1_dis
,
580 .is_enabled
= alchemy_clk_fgv1_isen
,
583 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk
*c
)
585 unsigned long v
= alchemy_rdsys(c
->reg
);
587 v
&= ~(3 << c
->shift
);
588 v
|= (c
->parent
& 3) << c
->shift
;
589 alchemy_wrsys(v
, c
->reg
);
593 static int alchemy_clk_fgv2_en(struct clk_hw
*hw
)
595 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
598 /* enable by setting the previous parent clock */
599 spin_lock_irqsave(c
->reglock
, flags
);
600 __alchemy_clk_fgv2_en(c
);
601 spin_unlock_irqrestore(c
->reglock
, flags
);
606 static int alchemy_clk_fgv2_isen(struct clk_hw
*hw
)
608 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
610 return ((alchemy_rdsys(c
->reg
) >> c
->shift
) & 3) != 0;
613 static void alchemy_clk_fgv2_dis(struct clk_hw
*hw
)
615 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
616 unsigned long v
, flags
;
618 spin_lock_irqsave(c
->reglock
, flags
);
619 v
= alchemy_rdsys(c
->reg
);
620 v
&= ~(3 << c
->shift
); /* set input mux to "disabled" state */
621 alchemy_wrsys(v
, c
->reg
);
623 spin_unlock_irqrestore(c
->reglock
, flags
);
626 static int alchemy_clk_fgv2_setp(struct clk_hw
*hw
, u8 index
)
628 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
631 spin_lock_irqsave(c
->reglock
, flags
);
632 c
->parent
= index
+ 1; /* value to write to register */
634 __alchemy_clk_fgv2_en(c
);
635 spin_unlock_irqrestore(c
->reglock
, flags
);
640 static u8
alchemy_clk_fgv2_getp(struct clk_hw
*hw
)
642 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
643 unsigned long flags
, v
;
645 spin_lock_irqsave(c
->reglock
, flags
);
647 spin_unlock_irqrestore(c
->reglock
, flags
);
651 /* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
652 * dividers behave exactly as on previous models (dividers are multiples
653 * of 2); with the bit set, dividers are multiples of 1, halving their
654 * range, but making them also much more flexible.
656 static int alchemy_clk_fgv2_setr(struct clk_hw
*hw
, unsigned long rate
,
657 unsigned long parent_rate
)
659 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
660 int sh
= c
->shift
+ 2;
661 unsigned long div
, v
, flags
, ret
;
663 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
666 v
= alchemy_rdsys(c
->reg
) & (1 << 30); /* test "scale" bit */
667 ret
= alchemy_calc_div(rate
, parent_rate
, v
? 1 : 2,
668 v
? 256 : 512, &div
);
670 spin_lock_irqsave(c
->reglock
, flags
);
671 v
= alchemy_rdsys(c
->reg
);
673 v
|= (div
& 0xff) << sh
;
674 alchemy_wrsys(v
, c
->reg
);
675 spin_unlock_irqrestore(c
->reglock
, flags
);
680 static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw
*hw
,
681 unsigned long parent_rate
)
683 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
684 int sh
= c
->shift
+ 2;
687 v
= alchemy_rdsys(c
->reg
);
688 t
= parent_rate
/ (((v
>> sh
) & 0xff) + 1);
689 if ((v
& (1 << 30)) == 0) /* test scale bit */
695 static long alchemy_clk_fgv2_detr(struct clk_hw
*hw
, unsigned long rate
,
696 unsigned long *best_parent_rate
,
697 struct clk_hw
**best_parent_clk
)
699 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
702 if (alchemy_rdsys(c
->reg
) & (1 << 30)) {
710 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
711 best_parent_clk
, scale
, maxdiv
);
714 /* Au1300 larger input mux, no separate disable bit, flexible divider */
715 static struct clk_ops alchemy_clkops_fgenv2
= {
716 .recalc_rate
= alchemy_clk_fgv2_recalc
,
717 .determine_rate
= alchemy_clk_fgv2_detr
,
718 .set_rate
= alchemy_clk_fgv2_setr
,
719 .set_parent
= alchemy_clk_fgv2_setp
,
720 .get_parent
= alchemy_clk_fgv2_getp
,
721 .enable
= alchemy_clk_fgv2_en
,
722 .disable
= alchemy_clk_fgv2_dis
,
723 .is_enabled
= alchemy_clk_fgv2_isen
,
726 static const char * const alchemy_clk_fgv1_parents
[] = {
727 ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
730 static const char * const alchemy_clk_fgv2_parents
[] = {
731 ALCHEMY_AUXPLL2_CLK
, ALCHEMY_CPU_CLK
, ALCHEMY_AUXPLL_CLK
734 static const char * const alchemy_clk_fgen_names
[] = {
735 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
736 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
};
738 static int __init
alchemy_clk_init_fgens(int ctype
)
741 struct clk_init_data id
;
742 struct alchemy_fgcs_clk
*a
;
747 case ALCHEMY_CPU_AU1000
...ALCHEMY_CPU_AU1200
:
748 id
.ops
= &alchemy_clkops_fgenv1
;
749 id
.parent_names
= (const char **)alchemy_clk_fgv1_parents
;
752 case ALCHEMY_CPU_AU1300
:
753 id
.ops
= &alchemy_clkops_fgenv2
;
754 id
.parent_names
= (const char **)alchemy_clk_fgv2_parents
;
760 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
762 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
766 spin_lock_init(&alchemy_clk_fg0_lock
);
767 spin_lock_init(&alchemy_clk_fg1_lock
);
769 for (i
= 0; i
< 6; i
++) {
770 id
.name
= alchemy_clk_fgen_names
[i
];
771 a
->shift
= 10 * (i
< 3 ? i
: i
- 3);
773 a
->reg
= AU1000_SYS_FREQCTRL1
;
774 a
->reglock
= &alchemy_clk_fg1_lock
;
776 a
->reg
= AU1000_SYS_FREQCTRL0
;
777 a
->reglock
= &alchemy_clk_fg0_lock
;
780 /* default to first parent if bootloader has set
781 * the mux to disabled state.
783 if (ctype
== ALCHEMY_CPU_AU1300
) {
784 v
= alchemy_rdsys(a
->reg
);
785 a
->parent
= (v
>> a
->shift
) & 3;
794 c
= clk_register(NULL
, &a
->hw
);
798 clk_register_clkdev(c
, id
.name
, NULL
);
805 /* internal sources muxes *********************************************/
807 static int alchemy_clk_csrc_isen(struct clk_hw
*hw
)
809 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
810 unsigned long v
= alchemy_rdsys(c
->reg
);
812 return (((v
>> c
->shift
) >> 2) & 7) != 0;
815 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk
*c
)
817 unsigned long v
= alchemy_rdsys(c
->reg
);
819 v
&= ~((7 << 2) << c
->shift
);
820 v
|= ((c
->parent
& 7) << 2) << c
->shift
;
821 alchemy_wrsys(v
, c
->reg
);
825 static int alchemy_clk_csrc_en(struct clk_hw
*hw
)
827 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
830 /* enable by setting the previous parent clock */
831 spin_lock_irqsave(c
->reglock
, flags
);
832 __alchemy_clk_csrc_en(c
);
833 spin_unlock_irqrestore(c
->reglock
, flags
);
838 static void alchemy_clk_csrc_dis(struct clk_hw
*hw
)
840 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
841 unsigned long v
, flags
;
843 spin_lock_irqsave(c
->reglock
, flags
);
844 v
= alchemy_rdsys(c
->reg
);
845 v
&= ~((3 << 2) << c
->shift
); /* mux to "disabled" state */
846 alchemy_wrsys(v
, c
->reg
);
848 spin_unlock_irqrestore(c
->reglock
, flags
);
851 static int alchemy_clk_csrc_setp(struct clk_hw
*hw
, u8 index
)
853 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
856 spin_lock_irqsave(c
->reglock
, flags
);
857 c
->parent
= index
+ 1; /* value to write to register */
859 __alchemy_clk_csrc_en(c
);
860 spin_unlock_irqrestore(c
->reglock
, flags
);
865 static u8
alchemy_clk_csrc_getp(struct clk_hw
*hw
)
867 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
869 return c
->parent
- 1;
872 static unsigned long alchemy_clk_csrc_recalc(struct clk_hw
*hw
,
873 unsigned long parent_rate
)
875 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
876 unsigned long v
= (alchemy_rdsys(c
->reg
) >> c
->shift
) & 3;
878 return parent_rate
/ c
->dt
[v
];
881 static int alchemy_clk_csrc_setr(struct clk_hw
*hw
, unsigned long rate
,
882 unsigned long parent_rate
)
884 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
885 unsigned long d
, v
, flags
;
888 if (!rate
|| !parent_rate
|| rate
> parent_rate
)
891 d
= (parent_rate
+ (rate
/ 2)) / rate
;
894 if ((d
== 3) && (c
->dt
[2] != 3))
897 for (i
= 0; i
< 4; i
++)
902 return -EINVAL
; /* oops */
904 spin_lock_irqsave(c
->reglock
, flags
);
905 v
= alchemy_rdsys(c
->reg
);
906 v
&= ~(3 << c
->shift
);
907 v
|= (i
& 3) << c
->shift
;
908 alchemy_wrsys(v
, c
->reg
);
909 spin_unlock_irqrestore(c
->reglock
, flags
);
914 static long alchemy_clk_csrc_detr(struct clk_hw
*hw
, unsigned long rate
,
915 unsigned long *best_parent_rate
,
916 struct clk_hw
**best_parent_clk
)
918 struct alchemy_fgcs_clk
*c
= to_fgcs_clk(hw
);
919 int scale
= c
->dt
[2] == 3 ? 1 : 2; /* au1300 check */
921 return alchemy_clk_fgcs_detr(hw
, rate
, best_parent_rate
,
922 best_parent_clk
, scale
, 4);
925 static struct clk_ops alchemy_clkops_csrc
= {
926 .recalc_rate
= alchemy_clk_csrc_recalc
,
927 .determine_rate
= alchemy_clk_csrc_detr
,
928 .set_rate
= alchemy_clk_csrc_setr
,
929 .set_parent
= alchemy_clk_csrc_setp
,
930 .get_parent
= alchemy_clk_csrc_getp
,
931 .enable
= alchemy_clk_csrc_en
,
932 .disable
= alchemy_clk_csrc_dis
,
933 .is_enabled
= alchemy_clk_csrc_isen
,
936 static const char * const alchemy_clk_csrc_parents
[] = {
937 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK
,
938 ALCHEMY_FG0_CLK
, ALCHEMY_FG1_CLK
, ALCHEMY_FG2_CLK
,
939 ALCHEMY_FG3_CLK
, ALCHEMY_FG4_CLK
, ALCHEMY_FG5_CLK
943 static int alchemy_csrc_dt1
[] = { 1, 4, 1, 2 }; /* rest */
944 static int alchemy_csrc_dt2
[] = { 1, 4, 3, 2 }; /* Au1300 */
946 static int __init
alchemy_clk_setup_imux(int ctype
)
948 struct alchemy_fgcs_clk
*a
;
949 const char * const *names
;
950 struct clk_init_data id
;
955 id
.ops
= &alchemy_clkops_csrc
;
956 id
.parent_names
= (const char **)alchemy_clk_csrc_parents
;
958 id
.flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
;
960 dt
= alchemy_csrc_dt1
;
962 case ALCHEMY_CPU_AU1000
:
963 names
= alchemy_au1000_intclknames
;
965 case ALCHEMY_CPU_AU1500
:
966 names
= alchemy_au1500_intclknames
;
968 case ALCHEMY_CPU_AU1100
:
969 names
= alchemy_au1100_intclknames
;
971 case ALCHEMY_CPU_AU1550
:
972 names
= alchemy_au1550_intclknames
;
974 case ALCHEMY_CPU_AU1200
:
975 names
= alchemy_au1200_intclknames
;
977 case ALCHEMY_CPU_AU1300
:
978 dt
= alchemy_csrc_dt2
;
979 names
= alchemy_au1300_intclknames
;
985 a
= kzalloc((sizeof(*a
)) * 6, GFP_KERNEL
);
989 spin_lock_init(&alchemy_clk_csrc_lock
);
992 for (i
= 0; i
< 6; i
++) {
998 a
->reg
= AU1000_SYS_CLKSRC
;
999 a
->reglock
= &alchemy_clk_csrc_lock
;
1002 /* default to first parent clock if mux is initially
1003 * set to disabled state.
1005 v
= alchemy_rdsys(a
->reg
);
1006 a
->parent
= ((v
>> a
->shift
) >> 2) & 7;
1014 c
= clk_register(NULL
, &a
->hw
);
1018 clk_register_clkdev(c
, id
.name
, NULL
);
1027 /**********************************************************************/
1036 static int __init
alchemy_clk_init(void)
1038 int ctype
= alchemy_get_cputype(), ret
, i
;
1039 struct clk_aliastable
*t
= alchemy_clk_aliases
;
1042 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1043 c
= clk_register_fixed_rate(NULL
, ALCHEMY_ROOT_CLK
, NULL
,
1045 ALCHEMY_ROOTCLK_RATE
);
1048 /* CPU core clock */
1049 c
= alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK
, ctype
);
1052 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1053 i
= (ctype
== ALCHEMY_CPU_AU1300
) ? 84 : 63;
1054 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
, ALCHEMY_AUXPLL_CLK
,
1055 i
, AU1000_SYS_AUXPLL
);
1058 if (ctype
== ALCHEMY_CPU_AU1300
) {
1059 c
= alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK
,
1060 ALCHEMY_AUXPLL2_CLK
, i
,
1061 AU1300_SYS_AUXPLL2
);
1065 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1066 c
= alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK
);
1069 /* peripheral clock: runs at half rate of sysbus clk */
1070 c
= alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK
);
1073 /* SDR/DDR memory clock */
1074 c
= alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK
, ctype
);
1077 /* L/RCLK: external static bus clock for synchronous mode */
1078 c
= alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK
, ctype
);
1081 /* Frequency dividers 0-5 */
1082 ret
= alchemy_clk_init_fgens(ctype
);
1088 /* diving muxes for internal sources */
1089 ret
= alchemy_clk_setup_imux(ctype
);
1095 /* set up aliases drivers might look for */
1097 if (t
->cputype
== ctype
)
1098 clk_add_alias(t
->alias
, NULL
, t
->base
, NULL
);
1102 pr_info("Alchemy clocktree installed\n");
1108 postcore_initcall(alchemy_clk_init
);