2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_pci.h>
33 #include <linux/export.h>
35 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
40 static DEFINE_SPINLOCK(hose_spinlock
);
43 /* XXX kill that some day ... */
44 static int global_phb_number
; /* Global phb counter */
46 /* ISA Memory physical address */
47 resource_size_t isa_mem_base
;
49 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
51 unsigned long isa_io_base
;
52 unsigned long pci_dram_offset
;
53 static int pci_bus_count
;
56 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
58 pci_dma_ops
= dma_ops
;
61 struct dma_map_ops
*get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops
);
67 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
69 struct pci_controller
*phb
;
71 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
74 spin_lock(&hose_spinlock
);
75 phb
->global_number
= global_phb_number
++;
76 list_add_tail(&phb
->list_node
, &hose_list
);
77 spin_unlock(&hose_spinlock
);
79 phb
->is_dynamic
= mem_init_done
;
83 void pcibios_free_controller(struct pci_controller
*phb
)
85 spin_lock(&hose_spinlock
);
86 list_del(&phb
->list_node
);
87 spin_unlock(&hose_spinlock
);
93 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
95 return resource_size(&hose
->io_resource
);
98 int pcibios_vaddr_is_ioport(void __iomem
*address
)
101 struct pci_controller
*hose
;
102 resource_size_t size
;
104 spin_lock(&hose_spinlock
);
105 list_for_each_entry(hose
, &hose_list
, list_node
) {
106 size
= pcibios_io_size(hose
);
107 if (address
>= hose
->io_base_virt
&&
108 address
< (hose
->io_base_virt
+ size
)) {
113 spin_unlock(&hose_spinlock
);
117 unsigned long pci_address_to_pio(phys_addr_t address
)
119 struct pci_controller
*hose
;
120 resource_size_t size
;
121 unsigned long ret
= ~0;
123 spin_lock(&hose_spinlock
);
124 list_for_each_entry(hose
, &hose_list
, list_node
) {
125 size
= pcibios_io_size(hose
);
126 if (address
>= hose
->io_base_phys
&&
127 address
< (hose
->io_base_phys
+ size
)) {
129 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
130 ret
= base
+ (address
- hose
->io_base_phys
);
134 spin_unlock(&hose_spinlock
);
138 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
141 * Return the domain number for this bus.
143 int pci_domain_nr(struct pci_bus
*bus
)
145 struct pci_controller
*hose
= pci_bus_to_host(bus
);
147 return hose
->global_number
;
149 EXPORT_SYMBOL(pci_domain_nr
);
151 /* This routine is meant to be used early during boot, when the
152 * PCI bus numbers have not yet been assigned, and you need to
153 * issue PCI config cycles to an OF device.
154 * It could also be used to "fix" RTAS config cycles if you want
155 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
158 struct pci_controller
*pci_find_hose_for_OF_device(struct device_node
*node
)
161 struct pci_controller
*hose
, *tmp
;
162 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
163 if (hose
->dn
== node
)
170 static ssize_t
pci_show_devspec(struct device
*dev
,
171 struct device_attribute
*attr
, char *buf
)
173 struct pci_dev
*pdev
;
174 struct device_node
*np
;
176 pdev
= to_pci_dev(dev
);
177 np
= pci_device_to_OF_node(pdev
);
178 if (np
== NULL
|| np
->full_name
== NULL
)
180 return sprintf(buf
, "%s", np
->full_name
);
182 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
184 /* Add sysfs properties */
185 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
187 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
190 void pcibios_set_master(struct pci_dev
*dev
)
192 /* No special bus mastering setup handling */
195 char __devinit
*pcibios_setup(char *str
)
201 * Reads the interrupt pin to determine if interrupt is use by card.
202 * If the interrupt is used, then gets the interrupt line from the
203 * openfirmware and sets it in the pci_dev and pci_config line.
205 int pci_read_irq_line(struct pci_dev
*pci_dev
)
210 /* The current device-tree that iSeries generates from the HV
211 * PCI informations doesn't contain proper interrupt routing,
212 * and all the fallback would do is print out crap, so we
213 * don't attempt to resolve the interrupts here at all, some
214 * iSeries specific fixup does it.
216 * In the long run, we will hopefully fix the generated device-tree
219 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
222 memset(&oirq
, 0xff, sizeof(oirq
));
224 /* Try to get a mapping from the device-tree */
225 if (of_irq_map_pci(pci_dev
, &oirq
)) {
228 /* If that fails, lets fallback to what is in the config
229 * space and map that through the default controller. We
230 * also set the type to level low since that's what PCI
231 * interrupts are. If your platform does differently, then
232 * either provide a proper interrupt tree or don't use this
235 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
239 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
240 line
== 0xff || line
== 0) {
243 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
246 virq
= irq_create_mapping(NULL
, line
);
248 irq_set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
250 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
251 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
252 oirq
.controller
? oirq
.controller
->full_name
:
255 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
259 pr_debug(" Failed to map !\n");
263 pr_debug(" Mapped to linux irq %d\n", virq
);
269 EXPORT_SYMBOL(pci_read_irq_line
);
272 * Platform support for /proc/bus/pci/X/Y mmap()s,
273 * modelled on the sparc64 implementation by Dave Miller.
278 * Adjust vm_pgoff of VMA such that it is the physical page offset
279 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
281 * Basically, the user finds the base address for his device which he wishes
282 * to mmap. They read the 32-bit value from the config space base register,
283 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
284 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
286 * Returns negative error code on failure, zero on success.
288 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
289 resource_size_t
*offset
,
290 enum pci_mmap_state mmap_state
)
292 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
293 unsigned long io_offset
= 0;
297 return NULL
; /* should never happen */
299 /* If memory, add on the PCI bridge address offset */
300 if (mmap_state
== pci_mmap_mem
) {
301 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
302 *offset
+= hose
->pci_mem_offset
;
304 res_bit
= IORESOURCE_MEM
;
306 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
307 *offset
+= io_offset
;
308 res_bit
= IORESOURCE_IO
;
312 * Check that the offset requested corresponds to one of the
313 * resources of the device.
315 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
316 struct resource
*rp
= &dev
->resource
[i
];
317 int flags
= rp
->flags
;
319 /* treat ROM as memory (should be already) */
320 if (i
== PCI_ROM_RESOURCE
)
321 flags
|= IORESOURCE_MEM
;
323 /* Active and same type? */
324 if ((flags
& res_bit
) == 0)
327 /* In the range of this resource? */
328 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
331 /* found it! construct the final physical address */
332 if (mmap_state
== pci_mmap_io
)
333 *offset
+= hose
->io_base_phys
- io_offset
;
341 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
344 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
346 enum pci_mmap_state mmap_state
,
349 pgprot_t prot
= protection
;
351 /* Write combine is always 0 on non-memory space mappings. On
352 * memory space, if the user didn't pass 1, we check for a
353 * "prefetchable" resource. This is a bit hackish, but we use
354 * this to workaround the inability of /sysfs to provide a write
357 if (mmap_state
!= pci_mmap_mem
)
359 else if (write_combine
== 0) {
360 if (rp
->flags
& IORESOURCE_PREFETCH
)
364 return pgprot_noncached(prot
);
368 * This one is used by /dev/mem and fbdev who have no clue about the
369 * PCI device, it tries to find the PCI device first and calls the
372 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
377 struct pci_dev
*pdev
= NULL
;
378 struct resource
*found
= NULL
;
379 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
382 if (page_is_ram(pfn
))
385 prot
= pgprot_noncached(prot
);
386 for_each_pci_dev(pdev
) {
387 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
388 struct resource
*rp
= &pdev
->resource
[i
];
389 int flags
= rp
->flags
;
391 /* Active and same type? */
392 if ((flags
& IORESOURCE_MEM
) == 0)
394 /* In the range of this resource? */
395 if (offset
< (rp
->start
& PAGE_MASK
) ||
405 if (found
->flags
& IORESOURCE_PREFETCH
)
406 prot
= pgprot_noncached_wc(prot
);
410 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
411 (unsigned long long)offset
, pgprot_val(prot
));
417 * Perform the actual remap of the pages for a PCI device mapping, as
418 * appropriate for this architecture. The region in the process to map
419 * is described by vm_start and vm_end members of VMA, the base physical
420 * address is found in vm_pgoff.
421 * The pci device structure is provided so that architectures may make mapping
422 * decisions on a per-device or per-bus basis.
424 * Returns a negative error code on failure, zero on success.
426 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
427 enum pci_mmap_state mmap_state
, int write_combine
)
429 resource_size_t offset
=
430 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
434 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
438 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
439 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
441 mmap_state
, write_combine
);
443 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
444 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
449 /* This provides legacy IO read access on a bus */
450 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
452 unsigned long offset
;
453 struct pci_controller
*hose
= pci_bus_to_host(bus
);
454 struct resource
*rp
= &hose
->io_resource
;
457 /* Check if port can be supported by that bus. We only check
458 * the ranges of the PHB though, not the bus itself as the rules
459 * for forwarding legacy cycles down bridges are not our problem
460 * here. So if the host bridge supports it, we do it.
462 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
465 if (!(rp
->flags
& IORESOURCE_IO
))
467 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
469 addr
= hose
->io_base_virt
+ port
;
473 *((u8
*)val
) = in_8(addr
);
478 *((u16
*)val
) = in_le16(addr
);
483 *((u32
*)val
) = in_le32(addr
);
489 /* This provides legacy IO write access on a bus */
490 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
492 unsigned long offset
;
493 struct pci_controller
*hose
= pci_bus_to_host(bus
);
494 struct resource
*rp
= &hose
->io_resource
;
497 /* Check if port can be supported by that bus. We only check
498 * the ranges of the PHB though, not the bus itself as the rules
499 * for forwarding legacy cycles down bridges are not our problem
500 * here. So if the host bridge supports it, we do it.
502 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
505 if (!(rp
->flags
& IORESOURCE_IO
))
507 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
509 addr
= hose
->io_base_virt
+ port
;
511 /* WARNING: The generic code is idiotic. It gets passed a pointer
512 * to what can be a 1, 2 or 4 byte quantity and always reads that
513 * as a u32, which means that we have to correct the location of
514 * the data read within those 32 bits for size 1 and 2
518 out_8(addr
, val
>> 24);
523 out_le16(addr
, val
>> 16);
534 /* This provides legacy IO or memory mmap access on a bus */
535 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
536 struct vm_area_struct
*vma
,
537 enum pci_mmap_state mmap_state
)
539 struct pci_controller
*hose
= pci_bus_to_host(bus
);
540 resource_size_t offset
=
541 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
542 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
545 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
546 pci_domain_nr(bus
), bus
->number
,
547 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
548 (unsigned long long)offset
,
549 (unsigned long long)(offset
+ size
- 1));
551 if (mmap_state
== pci_mmap_mem
) {
554 * Because X is lame and can fail starting if it gets an error
555 * trying to mmap legacy_mem (instead of just moving on without
556 * legacy memory access) we fake it here by giving it anonymous
557 * memory, effectively behaving just like /dev/zero
559 if ((offset
+ size
) > hose
->isa_mem_size
) {
562 "Process %s (pid:%d) mapped non-existing PCI"
563 "legacy memory for 0%04x:%02x\n",
564 current
->comm
, current
->pid
, pci_domain_nr(bus
),
567 if (vma
->vm_flags
& VM_SHARED
)
568 return shmem_zero_setup(vma
);
571 offset
+= hose
->isa_mem_phys
;
573 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- \
575 unsigned long roffset
= offset
+ io_offset
;
576 rp
= &hose
->io_resource
;
577 if (!(rp
->flags
& IORESOURCE_IO
))
579 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
581 offset
+= hose
->io_base_phys
;
583 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
585 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
586 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
587 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
588 vma
->vm_end
- vma
->vm_start
,
592 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
593 const struct resource
*rsrc
,
594 resource_size_t
*start
, resource_size_t
*end
)
596 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
597 resource_size_t offset
= 0;
602 if (rsrc
->flags
& IORESOURCE_IO
)
603 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
605 /* We pass a fully fixed up address to userland for MMIO instead of
606 * a BAR value because X is lame and expects to be able to use that
607 * to pass to /dev/mem !
609 * That means that we'll have potentially 64 bits values where some
610 * userland apps only expect 32 (like X itself since it thinks only
611 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
614 * Hopefully, the sysfs insterface is immune to that gunk. Once X
615 * has been fixed (and the fix spread enough), we can re-enable the
616 * 2 lines below and pass down a BAR value to userland. In that case
617 * we'll also have to re-enable the matching code in
618 * __pci_mmap_make_offset().
623 else if (rsrc
->flags
& IORESOURCE_MEM
)
624 offset
= hose
->pci_mem_offset
;
627 *start
= rsrc
->start
- offset
;
628 *end
= rsrc
->end
- offset
;
632 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
633 * @hose: newly allocated pci_controller to be setup
634 * @dev: device node of the host bridge
635 * @primary: set if primary bus (32 bits only, soon to be deprecated)
637 * This function will parse the "ranges" property of a PCI host bridge device
638 * node and setup the resource mapping of a pci controller based on its
641 * Life would be boring if it wasn't for a few issues that we have to deal
644 * - We can only cope with one IO space range and up to 3 Memory space
645 * ranges. However, some machines (thanks Apple !) tend to split their
646 * space into lots of small contiguous ranges. So we have to coalesce.
648 * - We can only cope with all memory ranges having the same offset
649 * between CPU addresses and PCI addresses. Unfortunately, some bridges
650 * are setup for a large 1:1 mapping along with a small "window" which
651 * maps PCI address 0 to some arbitrary high address of the CPU space in
652 * order to give access to the ISA memory hole.
653 * The way out of here that I've chosen for now is to always set the
654 * offset based on the first resource found, then override it if we
655 * have a different offset and the previous was set by an ISA hole.
657 * - Some busses have IO space not starting at 0, which causes trouble with
658 * the way we do our IO resource renumbering. The code somewhat deals with
659 * it for 64 bits but I would expect problems on 32 bits.
661 * - Some 32 bits platforms such as 4xx can have physical space larger than
662 * 32 bits so we need to use 64 bits values for the parsing
664 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
665 struct device_node
*dev
,
670 int pna
= of_n_addr_cells(dev
);
672 int memno
= 0, isa_hole
= -1;
674 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
675 unsigned long long isa_mb
= 0;
676 struct resource
*res
;
678 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
679 dev
->full_name
, primary
? "(primary)" : "");
681 /* Get ranges property */
682 ranges
= of_get_property(dev
, "ranges", &rlen
);
687 pr_debug("Parsing ranges property...\n");
688 while ((rlen
-= np
* 4) >= 0) {
689 /* Read next ranges element */
690 pci_space
= ranges
[0];
691 pci_addr
= of_read_number(ranges
+ 1, 2);
692 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
693 size
= of_read_number(ranges
+ pna
+ 3, 2);
695 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
696 "cpu_addr:0x%016llx size:0x%016llx\n",
697 pci_space
, pci_addr
, cpu_addr
, size
);
701 /* If we failed translation or got a zero-sized region
702 * (some FW try to feed us with non sensical zero sized regions
703 * such as power3 which look like some kind of attempt
704 * at exposing the VGA memory hole)
706 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
709 /* Now consume following elements while they are contiguous */
710 for (; rlen
>= np
* sizeof(u32
);
711 ranges
+= np
, rlen
-= np
* 4) {
712 if (ranges
[0] != pci_space
)
714 pci_next
= of_read_number(ranges
+ 1, 2);
715 cpu_next
= of_translate_address(dev
, ranges
+ 3);
716 if (pci_next
!= pci_addr
+ size
||
717 cpu_next
!= cpu_addr
+ size
)
719 size
+= of_read_number(ranges
+ pna
+ 3, 2);
722 /* Act based on address space type */
724 switch ((pci_space
>> 24) & 0x3) {
725 case 1: /* PCI IO space */
727 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
728 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
730 /* We support only one IO range */
731 if (hose
->pci_io_size
) {
733 " \\--> Skipped (too many) !\n");
736 /* On 32 bits, limit I/O space to 16MB */
737 if (size
> 0x01000000)
740 /* 32 bits needs to map IOs here */
741 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
743 /* Expect trouble if pci_addr is not 0 */
746 (unsigned long)hose
->io_base_virt
;
747 /* pci_io_size and io_base_phys always represent IO
748 * space starting at 0 so we factor in pci_addr
750 hose
->pci_io_size
= pci_addr
+ size
;
751 hose
->io_base_phys
= cpu_addr
- pci_addr
;
754 res
= &hose
->io_resource
;
755 res
->flags
= IORESOURCE_IO
;
756 res
->start
= pci_addr
;
758 case 2: /* PCI Memory space */
759 case 3: /* PCI 64 bits Memory space */
761 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
762 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
763 (pci_space
& 0x40000000) ? "Prefetch" : "");
765 /* We support only 3 memory ranges */
768 " \\--> Skipped (too many) !\n");
771 /* Handles ISA memory hole space here */
775 if (primary
|| isa_mem_base
== 0)
776 isa_mem_base
= cpu_addr
;
777 hose
->isa_mem_phys
= cpu_addr
;
778 hose
->isa_mem_size
= size
;
781 /* We get the PCI/Mem offset from the first range or
782 * the, current one if the offset came from an ISA
783 * hole. If they don't match, bugger.
786 (isa_hole
>= 0 && pci_addr
!= 0 &&
787 hose
->pci_mem_offset
== isa_mb
))
788 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
789 else if (pci_addr
!= 0 &&
790 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
792 " \\--> Skipped (offset mismatch) !\n");
797 res
= &hose
->mem_resources
[memno
++];
798 res
->flags
= IORESOURCE_MEM
;
799 if (pci_space
& 0x40000000)
800 res
->flags
|= IORESOURCE_PREFETCH
;
801 res
->start
= cpu_addr
;
805 res
->name
= dev
->full_name
;
806 res
->end
= res
->start
+ size
- 1;
813 /* If there's an ISA hole and the pci_mem_offset is -not- matching
814 * the ISA hole offset, then we need to remove the ISA hole from
815 * the resource list for that brige
817 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
818 unsigned int next
= isa_hole
+ 1;
819 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
821 memmove(&hose
->mem_resources
[isa_hole
],
822 &hose
->mem_resources
[next
],
823 sizeof(struct resource
) * (memno
- next
));
824 hose
->mem_resources
[--memno
].flags
= 0;
828 /* Decide whether to display the domain number in /proc */
829 int pci_proc_domain(struct pci_bus
*bus
)
831 struct pci_controller
*hose
= pci_bus_to_host(bus
);
836 /* This header fixup will do the resource fixup for all devices as they are
837 * probed, but not for bridge ranges
839 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
841 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
845 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
849 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
850 struct resource
*res
= dev
->resource
+ i
;
853 if (res
->start
== 0) {
854 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
857 (unsigned long long)res
->start
,
858 (unsigned long long)res
->end
,
859 (unsigned int)res
->flags
);
860 res
->end
-= res
->start
;
862 res
->flags
|= IORESOURCE_UNSET
;
866 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
868 (unsigned long long)res
->start
,\
869 (unsigned long long)res
->end
,
870 (unsigned int)res
->flags
);
873 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
875 /* This function tries to figure out if a bridge resource has been initialized
876 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
877 * things go more smoothly when it gets it right. It should covers cases such
878 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
880 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
881 struct resource
*res
)
883 struct pci_controller
*hose
= pci_bus_to_host(bus
);
884 struct pci_dev
*dev
= bus
->self
;
885 resource_size_t offset
;
889 /* Job is a bit different between memory and IO */
890 if (res
->flags
& IORESOURCE_MEM
) {
891 /* If the BAR is non-0 (res != pci_mem_offset) then it's
892 * probably been initialized by somebody
894 if (res
->start
!= hose
->pci_mem_offset
)
897 /* The BAR is 0, let's check if memory decoding is enabled on
898 * the bridge. If not, we consider it unassigned
900 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
901 if ((command
& PCI_COMMAND_MEMORY
) == 0)
904 /* Memory decoding is enabled and the BAR is 0. If any of
905 * the bridge resources covers that starting address (0 then
906 * it's good enough for us for memory
908 for (i
= 0; i
< 3; i
++) {
909 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
910 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
914 /* Well, it starts at 0 and we know it will collide so we may as
915 * well consider it as unassigned. That covers the Apple case.
919 /* If the BAR is non-0, then we consider it assigned */
920 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
921 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
924 /* Here, we are a bit different than memory as typically IO
925 * space starting at low addresses -is- valid. What we do
926 * instead if that we consider as unassigned anything that
927 * doesn't have IO enabled in the PCI command register,
930 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
931 if (command
& PCI_COMMAND_IO
)
934 /* It's starting at 0 and IO is disabled in the bridge, consider
941 /* Fixup resources of a PCI<->PCI bridge */
942 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
944 struct resource
*res
;
947 struct pci_dev
*dev
= bus
->self
;
949 pci_bus_for_each_resource(bus
, res
, i
) {
954 if (i
>= 3 && bus
->self
->transparent
)
957 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
959 (unsigned long long)res
->start
,\
960 (unsigned long long)res
->end
,
961 (unsigned int)res
->flags
);
963 /* Try to detect uninitialized P2P bridge resources,
964 * and clear them out so they get re-assigned later
966 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
968 pr_debug("PCI:%s (unassigned)\n",
971 pr_debug("PCI:%s %016llx-%016llx\n",
973 (unsigned long long)res
->start
,
974 (unsigned long long)res
->end
);
979 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
981 /* Fix up the bus resources for P2P bridges */
982 if (bus
->self
!= NULL
)
983 pcibios_fixup_bridge(bus
);
986 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
990 pr_debug("PCI: Fixup bus devices %d (%s)\n",
991 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
993 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
994 /* Setup OF node pointer in archdata */
995 dev
->dev
.of_node
= pci_device_to_OF_node(dev
);
997 /* Fixup NUMA node as it may not be setup yet by the generic
998 * code and is needed by the DMA init
1000 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1002 /* Hook up default DMA ops */
1003 set_dma_ops(&dev
->dev
, pci_dma_ops
);
1004 dev
->dev
.archdata
.dma_data
= (void *)PCI_DRAM_OFFSET
;
1006 /* Read default IRQs and fixup if necessary */
1007 pci_read_irq_line(dev
);
1011 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1013 /* When called from the generic PCI probe, read PCI<->PCI bridge
1014 * bases. This is -not- called when generating the PCI tree from
1015 * the OF device-tree.
1017 if (bus
->self
!= NULL
)
1018 pci_read_bridge_bases(bus
);
1020 /* Now fixup the bus bus */
1021 pcibios_setup_bus_self(bus
);
1023 /* Now fixup devices on that bus */
1024 pcibios_setup_bus_devices(bus
);
1026 EXPORT_SYMBOL(pcibios_fixup_bus
);
1028 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1034 * We need to avoid collisions with `mirrored' VGA ports
1035 * and other strange ISA hardware, so we always want the
1036 * addresses to be allocated in the 0x000-0x0ff region
1039 * Why? Because some silly external IO cards only decode
1040 * the low 10 bits of the IO address. The 0x00-0xff region
1041 * is reserved for motherboard devices that decode all 16
1042 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1043 * but we want to try to avoid allocating at 0x2900-0x2bff
1044 * which might have be mirrored at 0x0100-0x03ff..
1046 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1047 resource_size_t size
, resource_size_t align
)
1049 struct pci_dev
*dev
= data
;
1050 resource_size_t start
= res
->start
;
1052 if (res
->flags
& IORESOURCE_IO
) {
1053 if (skip_isa_ioresource_align(dev
))
1056 start
= (start
+ 0x3ff) & ~0x3ff;
1061 EXPORT_SYMBOL(pcibios_align_resource
);
1064 * Reparent resource children of pr that conflict with res
1065 * under res, and make res replace those children.
1067 static int __init
reparent_resources(struct resource
*parent
,
1068 struct resource
*res
)
1070 struct resource
*p
, **pp
;
1071 struct resource
**firstpp
= NULL
;
1073 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1074 if (p
->end
< res
->start
)
1076 if (res
->end
< p
->start
)
1078 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1079 return -1; /* not completely contained */
1080 if (firstpp
== NULL
)
1083 if (firstpp
== NULL
)
1084 return -1; /* didn't find any conflicting entries? */
1085 res
->parent
= parent
;
1086 res
->child
= *firstpp
;
1090 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1092 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1094 (unsigned long long)p
->start
,
1095 (unsigned long long)p
->end
, res
->name
);
1101 * Handle resources of PCI devices. If the world were perfect, we could
1102 * just allocate all the resource regions and do nothing more. It isn't.
1103 * On the other hand, we cannot just re-allocate all devices, as it would
1104 * require us to know lots of host bridge internals. So we attempt to
1105 * keep as much of the original configuration as possible, but tweak it
1106 * when it's found to be wrong.
1108 * Known BIOS problems we have to work around:
1109 * - I/O or memory regions not configured
1110 * - regions configured, but not enabled in the command register
1111 * - bogus I/O addresses above 64K used
1112 * - expansion ROMs left enabled (this may sound harmless, but given
1113 * the fact the PCI specs explicitly allow address decoders to be
1114 * shared between expansion ROMs and other resource regions, it's
1115 * at least dangerous)
1118 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1119 * This gives us fixed barriers on where we can allocate.
1120 * (2) Allocate resources for all enabled devices. If there is
1121 * a collision, just mark the resource as unallocated. Also
1122 * disable expansion ROMs during this step.
1123 * (3) Try to allocate resources for disabled devices. If the
1124 * resources were assigned correctly, everything goes well,
1125 * if they weren't, they won't disturb allocation of other
1127 * (4) Assign new addresses to resources which were either
1128 * not configured at all or misconfigured. If explicitly
1129 * requested by the user, configure expansion ROM address
1133 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1137 struct resource
*res
, *pr
;
1139 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1140 pci_domain_nr(bus
), bus
->number
);
1142 pci_bus_for_each_resource(bus
, res
, i
) {
1143 if (!res
|| !res
->flags
1144 || res
->start
> res
->end
|| res
->parent
)
1146 if (bus
->parent
== NULL
)
1147 pr
= (res
->flags
& IORESOURCE_IO
) ?
1148 &ioport_resource
: &iomem_resource
;
1150 /* Don't bother with non-root busses when
1151 * re-assigning all resources. We clear the
1152 * resource flags as if they were colliding
1153 * and as such ensure proper re-allocation
1156 pr
= pci_find_parent_resource(bus
->self
, res
);
1158 /* this happens when the generic PCI
1159 * code (wrongly) decides that this
1160 * bridge is transparent -- paulus
1166 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1167 "[0x%x], parent %p (%s)\n",
1168 bus
->self
? pci_name(bus
->self
) : "PHB",
1170 (unsigned long long)res
->start
,
1171 (unsigned long long)res
->end
,
1172 (unsigned int)res
->flags
,
1173 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1175 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1176 if (request_resource(pr
, res
) == 0)
1179 * Must be a conflict with an existing entry.
1180 * Move that entry (or entries) under the
1181 * bridge resource and try again.
1183 if (reparent_resources(pr
, res
) == 0)
1186 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1187 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1189 res
->start
= res
->end
= 0;
1193 list_for_each_entry(b
, &bus
->children
, node
)
1194 pcibios_allocate_bus_resources(b
);
1197 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1199 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1201 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1203 (unsigned long long)r
->start
,
1204 (unsigned long long)r
->end
,
1205 (unsigned int)r
->flags
);
1207 pr
= pci_find_parent_resource(dev
, r
);
1208 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1209 request_resource(pr
, r
) < 0) {
1210 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1211 " of device %s, will remap\n", idx
, pci_name(dev
));
1213 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1215 (unsigned long long)pr
->start
,
1216 (unsigned long long)pr
->end
,
1217 (unsigned int)pr
->flags
);
1218 /* We'll assign a new address later */
1219 r
->flags
|= IORESOURCE_UNSET
;
1225 static void __init
pcibios_allocate_resources(int pass
)
1227 struct pci_dev
*dev
= NULL
;
1232 for_each_pci_dev(dev
) {
1233 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1234 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1235 r
= &dev
->resource
[idx
];
1236 if (r
->parent
) /* Already allocated */
1238 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1239 continue; /* Not assigned at all */
1240 /* We only allocate ROMs on pass 1 just in case they
1241 * have been screwed up by firmware
1243 if (idx
== PCI_ROM_RESOURCE
)
1245 if (r
->flags
& IORESOURCE_IO
)
1246 disabled
= !(command
& PCI_COMMAND_IO
);
1248 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1249 if (pass
== disabled
)
1250 alloc_resource(dev
, idx
);
1254 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1256 /* Turn the ROM off, leave the resource region,
1257 * but keep it unregistered.
1260 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1261 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1262 pr_debug("PCI: Switching off ROM of %s\n",
1264 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1265 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1266 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1272 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1274 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1275 resource_size_t offset
;
1276 struct resource
*res
, *pres
;
1279 pr_debug("Reserving legacy ranges for domain %04x\n",
1280 pci_domain_nr(bus
));
1283 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1285 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1286 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1287 BUG_ON(res
== NULL
);
1288 res
->name
= "Legacy IO";
1289 res
->flags
= IORESOURCE_IO
;
1290 res
->start
= offset
;
1291 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1292 pr_debug("Candidate legacy IO: %pR\n", res
);
1293 if (request_resource(&hose
->io_resource
, res
)) {
1295 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1296 pci_domain_nr(bus
), bus
->number
, res
);
1301 /* Check for memory */
1302 offset
= hose
->pci_mem_offset
;
1303 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1304 for (i
= 0; i
< 3; i
++) {
1305 pres
= &hose
->mem_resources
[i
];
1306 if (!(pres
->flags
& IORESOURCE_MEM
))
1308 pr_debug("hose mem res: %pR\n", pres
);
1309 if ((pres
->start
- offset
) <= 0xa0000 &&
1310 (pres
->end
- offset
) >= 0xbffff)
1315 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1316 BUG_ON(res
== NULL
);
1317 res
->name
= "Legacy VGA memory";
1318 res
->flags
= IORESOURCE_MEM
;
1319 res
->start
= 0xa0000 + offset
;
1320 res
->end
= 0xbffff + offset
;
1321 pr_debug("Candidate VGA memory: %pR\n", res
);
1322 if (request_resource(pres
, res
)) {
1324 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1325 pci_domain_nr(bus
), bus
->number
, res
);
1330 void __init
pcibios_resource_survey(void)
1334 /* Allocate and assign resources. If we re-assign everything, then
1335 * we skip the allocate phase
1337 list_for_each_entry(b
, &pci_root_buses
, node
)
1338 pcibios_allocate_bus_resources(b
);
1340 pcibios_allocate_resources(0);
1341 pcibios_allocate_resources(1);
1343 /* Before we start assigning unassigned resource, we try to reserve
1344 * the low IO area and the VGA memory area if they intersect the
1345 * bus available resources to avoid allocating things on top of them
1347 list_for_each_entry(b
, &pci_root_buses
, node
)
1348 pcibios_reserve_legacy_regions(b
);
1350 /* Now proceed to assigning things that were left unassigned */
1351 pr_debug("PCI: Assigning unassigned resources...\n");
1352 pci_assign_unassigned_resources();
1355 #ifdef CONFIG_HOTPLUG
1357 /* This is used by the PCI hotplug driver to allocate resource
1358 * of newly plugged busses. We can try to consolidate with the
1359 * rest of the code later, for now, keep it as-is as our main
1360 * resource allocation function doesn't deal with sub-trees yet.
1362 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1364 struct pci_dev
*dev
;
1365 struct pci_bus
*child_bus
;
1367 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1370 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1371 struct resource
*r
= &dev
->resource
[i
];
1373 if (r
->parent
|| !r
->start
|| !r
->flags
)
1376 pr_debug("PCI: Claiming %s: "
1377 "Resource %d: %016llx..%016llx [%x]\n",
1379 (unsigned long long)r
->start
,
1380 (unsigned long long)r
->end
,
1381 (unsigned int)r
->flags
);
1383 pci_claim_resource(dev
, i
);
1387 list_for_each_entry(child_bus
, &bus
->children
, node
)
1388 pcibios_claim_one_bus(child_bus
);
1390 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1393 /* pcibios_finish_adding_to_bus
1395 * This is to be called by the hotplug code after devices have been
1396 * added to a bus, this include calling it for a PHB that is just
1399 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1401 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1402 pci_domain_nr(bus
), bus
->number
);
1404 /* Allocate bus and devices resources */
1405 pcibios_allocate_bus_resources(bus
);
1406 pcibios_claim_one_bus(bus
);
1408 /* Add new devices to global lists. Register in proc, sysfs. */
1409 pci_bus_add_devices(bus
);
1412 /* eeh_add_device_tree_late(bus); */
1414 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1416 #endif /* CONFIG_HOTPLUG */
1418 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1420 return pci_enable_resources(dev
, mask
);
1423 static void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
, struct list_head
*resources
)
1425 unsigned long io_offset
;
1426 struct resource
*res
;
1429 /* Hookup PHB IO resource */
1430 res
= &hose
->io_resource
;
1432 /* Fixup IO space offset */
1433 io_offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1434 res
->start
= (res
->start
+ io_offset
) & 0xffffffffu
;
1435 res
->end
= (res
->end
+ io_offset
) & 0xffffffffu
;
1438 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1439 " bridge %s (domain %d)\n",
1440 hose
->dn
->full_name
, hose
->global_number
);
1441 /* Workaround for lack of IO resource only on 32-bit */
1442 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1443 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1444 res
->flags
= IORESOURCE_IO
;
1446 pci_add_resource_offset(resources
, res
, hose
->io_base_virt
- _IO_BASE
);
1448 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1449 (unsigned long long)res
->start
,
1450 (unsigned long long)res
->end
,
1451 (unsigned long)res
->flags
);
1453 /* Hookup PHB Memory resources */
1454 for (i
= 0; i
< 3; ++i
) {
1455 res
= &hose
->mem_resources
[i
];
1459 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1460 "host bridge %s (domain %d)\n",
1461 hose
->dn
->full_name
, hose
->global_number
);
1463 /* Workaround for lack of MEM resource only on 32-bit */
1464 res
->start
= hose
->pci_mem_offset
;
1465 res
->end
= (resource_size_t
)-1LL;
1466 res
->flags
= IORESOURCE_MEM
;
1469 pci_add_resource_offset(resources
, res
, hose
->pci_mem_offset
);
1471 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1472 i
, (unsigned long long)res
->start
,
1473 (unsigned long long)res
->end
,
1474 (unsigned long)res
->flags
);
1477 pr_debug("PCI: PHB MEM offset = %016llx\n",
1478 (unsigned long long)hose
->pci_mem_offset
);
1479 pr_debug("PCI: PHB IO offset = %08lx\n",
1480 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1483 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
)
1485 struct pci_controller
*hose
= bus
->sysdata
;
1487 return of_node_get(hose
->dn
);
1490 static void __devinit
pcibios_scan_phb(struct pci_controller
*hose
)
1492 LIST_HEAD(resources
);
1493 struct pci_bus
*bus
;
1494 struct device_node
*node
= hose
->dn
;
1496 pr_debug("PCI: Scanning PHB %s\n",
1497 node
? node
->full_name
: "<NO NAME>");
1499 pcibios_setup_phb_resources(hose
, &resources
);
1501 bus
= pci_scan_root_bus(hose
->parent
, hose
->first_busno
,
1502 hose
->ops
, hose
, &resources
);
1504 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
1505 hose
->global_number
);
1506 pci_free_resource_list(&resources
);
1509 bus
->secondary
= hose
->first_busno
;
1512 hose
->last_busno
= bus
->subordinate
;
1515 static int __init
pcibios_init(void)
1517 struct pci_controller
*hose
, *tmp
;
1520 printk(KERN_INFO
"PCI: Probing PCI hardware\n");
1522 /* Scan all of the recorded PCI controllers. */
1523 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1524 hose
->last_busno
= 0xff;
1525 pcibios_scan_phb(hose
);
1526 if (next_busno
<= hose
->last_busno
)
1527 next_busno
= hose
->last_busno
+ 1;
1529 pci_bus_count
= next_busno
;
1531 /* Call common code to handle resource allocation */
1532 pcibios_resource_survey();
1537 subsys_initcall(pcibios_init
);
1539 static struct pci_controller
*pci_bus_to_hose(int bus
)
1541 struct pci_controller
*hose
, *tmp
;
1543 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1544 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
1549 /* Provide information on locations of various I/O regions in physical
1550 * memory. Do this on a per-card basis so that we choose the right
1552 * Note that the returned IO or memory base is a physical address
1555 long sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
1557 struct pci_controller
*hose
;
1558 long result
= -EOPNOTSUPP
;
1560 hose
= pci_bus_to_hose(bus
);
1565 case IOBASE_BRIDGE_NUMBER
:
1566 return (long)hose
->first_busno
;
1568 return (long)hose
->pci_mem_offset
;
1570 return (long)hose
->io_base_phys
;
1572 return (long)isa_io_base
;
1573 case IOBASE_ISA_MEM
:
1574 return (long)isa_mem_base
;
1581 * Null PCI config access functions, for the case when we can't
1584 #define NULL_PCI_OP(rw, size, type) \
1586 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1588 return PCIBIOS_DEVICE_NOT_FOUND; \
1592 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1595 return PCIBIOS_DEVICE_NOT_FOUND
;
1599 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1602 return PCIBIOS_DEVICE_NOT_FOUND
;
1605 static struct pci_ops null_pci_ops
= {
1606 .read
= null_read_config
,
1607 .write
= null_write_config
,
1611 * These functions are used early on before PCI scanning is done
1612 * and all of the pci_dev and pci_bus structures have been created.
1614 static struct pci_bus
*
1615 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1617 static struct pci_bus bus
;
1620 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1624 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1628 #define EARLY_PCI_OP(rw, size, type) \
1629 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1630 int devfn, int offset, type value) \
1632 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1633 devfn, offset, value); \
1636 EARLY_PCI_OP(read
, byte
, u8
*)
1637 EARLY_PCI_OP(read
, word
, u16
*)
1638 EARLY_PCI_OP(read
, dword
, u32
*)
1639 EARLY_PCI_OP(write
, byte
, u8
)
1640 EARLY_PCI_OP(write
, word
, u16
)
1641 EARLY_PCI_OP(write
, dword
, u32
)
1643 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1646 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);