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[PATCH] genirq: clean up irq-flow-type naming
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / i386 / kernel / io_apic.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37
38 #include <asm/io.h>
39 #include <asm/smp.h>
40 #include <asm/desc.h>
41 #include <asm/timer.h>
42 #include <asm/i8259.h>
43 #include <asm/nmi.h>
44 #include <asm/msidef.h>
45 #include <asm/hypertransport.h>
46
47 #include <mach_apic.h>
48 #include <mach_apicdef.h>
49
50 #include "io_ports.h"
51
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
54
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
57
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
60
61 int timer_over_8254 __initdata = 1;
62
63 /*
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
66 */
67 int sis_apic_bug = -1;
68
69 /*
70 * # of IRQ routing registers
71 */
72 int nr_ioapic_registers[MAX_IO_APICS];
73
74 static int disable_timer_pin_1 __initdata;
75
76 /*
77 * Rough estimation of how many shared IRQs there are, can
78 * be changed anytime.
79 */
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
82
83 /*
84 * This is performance-critical, we want to do it O(1)
85 *
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
88 */
89
90 static struct irq_pin_list {
91 int apic, pin, next;
92 } irq_2_pin[PIN_MAP_SIZE];
93
94 union entry_union {
95 struct { u32 w1, w2; };
96 struct IO_APIC_route_entry entry;
97 };
98
99 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
100 {
101 union entry_union eu;
102 unsigned long flags;
103 spin_lock_irqsave(&ioapic_lock, flags);
104 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
105 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
106 spin_unlock_irqrestore(&ioapic_lock, flags);
107 return eu.entry;
108 }
109
110 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
111 {
112 unsigned long flags;
113 union entry_union eu;
114 eu.entry = e;
115 spin_lock_irqsave(&ioapic_lock, flags);
116 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
117 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
118 spin_unlock_irqrestore(&ioapic_lock, flags);
119 }
120
121 /*
122 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
123 * shared ISA-space IRQs, so we have to support them. We are super
124 * fast in the common case, and fast for shared ISA-space IRQs.
125 */
126 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
127 {
128 static int first_free_entry = NR_IRQS;
129 struct irq_pin_list *entry = irq_2_pin + irq;
130
131 while (entry->next)
132 entry = irq_2_pin + entry->next;
133
134 if (entry->pin != -1) {
135 entry->next = first_free_entry;
136 entry = irq_2_pin + entry->next;
137 if (++first_free_entry >= PIN_MAP_SIZE)
138 panic("io_apic.c: whoops");
139 }
140 entry->apic = apic;
141 entry->pin = pin;
142 }
143
144 /*
145 * Reroute an IRQ to a different pin.
146 */
147 static void __init replace_pin_at_irq(unsigned int irq,
148 int oldapic, int oldpin,
149 int newapic, int newpin)
150 {
151 struct irq_pin_list *entry = irq_2_pin + irq;
152
153 while (1) {
154 if (entry->apic == oldapic && entry->pin == oldpin) {
155 entry->apic = newapic;
156 entry->pin = newpin;
157 }
158 if (!entry->next)
159 break;
160 entry = irq_2_pin + entry->next;
161 }
162 }
163
164 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
165 {
166 struct irq_pin_list *entry = irq_2_pin + irq;
167 unsigned int pin, reg;
168
169 for (;;) {
170 pin = entry->pin;
171 if (pin == -1)
172 break;
173 reg = io_apic_read(entry->apic, 0x10 + pin*2);
174 reg &= ~disable;
175 reg |= enable;
176 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
177 if (!entry->next)
178 break;
179 entry = irq_2_pin + entry->next;
180 }
181 }
182
183 /* mask = 1 */
184 static void __mask_IO_APIC_irq (unsigned int irq)
185 {
186 __modify_IO_APIC_irq(irq, 0x00010000, 0);
187 }
188
189 /* mask = 0 */
190 static void __unmask_IO_APIC_irq (unsigned int irq)
191 {
192 __modify_IO_APIC_irq(irq, 0, 0x00010000);
193 }
194
195 /* mask = 1, trigger = 0 */
196 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
197 {
198 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
199 }
200
201 /* mask = 0, trigger = 1 */
202 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
203 {
204 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
205 }
206
207 static void mask_IO_APIC_irq (unsigned int irq)
208 {
209 unsigned long flags;
210
211 spin_lock_irqsave(&ioapic_lock, flags);
212 __mask_IO_APIC_irq(irq);
213 spin_unlock_irqrestore(&ioapic_lock, flags);
214 }
215
216 static void unmask_IO_APIC_irq (unsigned int irq)
217 {
218 unsigned long flags;
219
220 spin_lock_irqsave(&ioapic_lock, flags);
221 __unmask_IO_APIC_irq(irq);
222 spin_unlock_irqrestore(&ioapic_lock, flags);
223 }
224
225 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
226 {
227 struct IO_APIC_route_entry entry;
228
229 /* Check delivery_mode to be sure we're not clearing an SMI pin */
230 entry = ioapic_read_entry(apic, pin);
231 if (entry.delivery_mode == dest_SMI)
232 return;
233
234 /*
235 * Disable it in the IO-APIC irq-routing table:
236 */
237 memset(&entry, 0, sizeof(entry));
238 entry.mask = 1;
239 ioapic_write_entry(apic, pin, entry);
240 }
241
242 static void clear_IO_APIC (void)
243 {
244 int apic, pin;
245
246 for (apic = 0; apic < nr_ioapics; apic++)
247 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
248 clear_IO_APIC_pin(apic, pin);
249 }
250
251 #ifdef CONFIG_SMP
252 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
253 {
254 unsigned long flags;
255 int pin;
256 struct irq_pin_list *entry = irq_2_pin + irq;
257 unsigned int apicid_value;
258 cpumask_t tmp;
259
260 cpus_and(tmp, cpumask, cpu_online_map);
261 if (cpus_empty(tmp))
262 tmp = TARGET_CPUS;
263
264 cpus_and(cpumask, tmp, CPU_MASK_ALL);
265
266 apicid_value = cpu_mask_to_apicid(cpumask);
267 /* Prepare to do the io_apic_write */
268 apicid_value = apicid_value << 24;
269 spin_lock_irqsave(&ioapic_lock, flags);
270 for (;;) {
271 pin = entry->pin;
272 if (pin == -1)
273 break;
274 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
275 if (!entry->next)
276 break;
277 entry = irq_2_pin + entry->next;
278 }
279 set_native_irq_info(irq, cpumask);
280 spin_unlock_irqrestore(&ioapic_lock, flags);
281 }
282
283 #if defined(CONFIG_IRQBALANCE)
284 # include <asm/processor.h> /* kernel_thread() */
285 # include <linux/kernel_stat.h> /* kstat */
286 # include <linux/slab.h> /* kmalloc() */
287 # include <linux/timer.h> /* time_after() */
288
289 #ifdef CONFIG_BALANCED_IRQ_DEBUG
290 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
291 # define Dprintk(x...) do { TDprintk(x); } while (0)
292 # else
293 # define TDprintk(x...)
294 # define Dprintk(x...)
295 # endif
296
297 #define IRQBALANCE_CHECK_ARCH -999
298 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
299 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
300 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
301 #define BALANCED_IRQ_LESS_DELTA (HZ)
302
303 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
304 static int physical_balance __read_mostly;
305 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
306
307 static struct irq_cpu_info {
308 unsigned long * last_irq;
309 unsigned long * irq_delta;
310 unsigned long irq;
311 } irq_cpu_data[NR_CPUS];
312
313 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
314 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
315 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
316
317 #define IDLE_ENOUGH(cpu,now) \
318 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
319
320 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
321
322 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
323
324 static cpumask_t balance_irq_affinity[NR_IRQS] = {
325 [0 ... NR_IRQS-1] = CPU_MASK_ALL
326 };
327
328 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
329 {
330 balance_irq_affinity[irq] = mask;
331 }
332
333 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
334 unsigned long now, int direction)
335 {
336 int search_idle = 1;
337 int cpu = curr_cpu;
338
339 goto inside;
340
341 do {
342 if (unlikely(cpu == curr_cpu))
343 search_idle = 0;
344 inside:
345 if (direction == 1) {
346 cpu++;
347 if (cpu >= NR_CPUS)
348 cpu = 0;
349 } else {
350 cpu--;
351 if (cpu == -1)
352 cpu = NR_CPUS-1;
353 }
354 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
355 (search_idle && !IDLE_ENOUGH(cpu,now)));
356
357 return cpu;
358 }
359
360 static inline void balance_irq(int cpu, int irq)
361 {
362 unsigned long now = jiffies;
363 cpumask_t allowed_mask;
364 unsigned int new_cpu;
365
366 if (irqbalance_disabled)
367 return;
368
369 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
370 new_cpu = move(cpu, allowed_mask, now, 1);
371 if (cpu != new_cpu) {
372 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
373 }
374 }
375
376 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
377 {
378 int i, j;
379 Dprintk("Rotating IRQs among CPUs.\n");
380 for_each_online_cpu(i) {
381 for (j = 0; j < NR_IRQS; j++) {
382 if (!irq_desc[j].action)
383 continue;
384 /* Is it a significant load ? */
385 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
386 useful_load_threshold)
387 continue;
388 balance_irq(i, j);
389 }
390 }
391 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
392 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
393 return;
394 }
395
396 static void do_irq_balance(void)
397 {
398 int i, j;
399 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
400 unsigned long move_this_load = 0;
401 int max_loaded = 0, min_loaded = 0;
402 int load;
403 unsigned long useful_load_threshold = balanced_irq_interval + 10;
404 int selected_irq;
405 int tmp_loaded, first_attempt = 1;
406 unsigned long tmp_cpu_irq;
407 unsigned long imbalance = 0;
408 cpumask_t allowed_mask, target_cpu_mask, tmp;
409
410 for_each_possible_cpu(i) {
411 int package_index;
412 CPU_IRQ(i) = 0;
413 if (!cpu_online(i))
414 continue;
415 package_index = CPU_TO_PACKAGEINDEX(i);
416 for (j = 0; j < NR_IRQS; j++) {
417 unsigned long value_now, delta;
418 /* Is this an active IRQ? */
419 if (!irq_desc[j].action)
420 continue;
421 if ( package_index == i )
422 IRQ_DELTA(package_index,j) = 0;
423 /* Determine the total count per processor per IRQ */
424 value_now = (unsigned long) kstat_cpu(i).irqs[j];
425
426 /* Determine the activity per processor per IRQ */
427 delta = value_now - LAST_CPU_IRQ(i,j);
428
429 /* Update last_cpu_irq[][] for the next time */
430 LAST_CPU_IRQ(i,j) = value_now;
431
432 /* Ignore IRQs whose rate is less than the clock */
433 if (delta < useful_load_threshold)
434 continue;
435 /* update the load for the processor or package total */
436 IRQ_DELTA(package_index,j) += delta;
437
438 /* Keep track of the higher numbered sibling as well */
439 if (i != package_index)
440 CPU_IRQ(i) += delta;
441 /*
442 * We have sibling A and sibling B in the package
443 *
444 * cpu_irq[A] = load for cpu A + load for cpu B
445 * cpu_irq[B] = load for cpu B
446 */
447 CPU_IRQ(package_index) += delta;
448 }
449 }
450 /* Find the least loaded processor package */
451 for_each_online_cpu(i) {
452 if (i != CPU_TO_PACKAGEINDEX(i))
453 continue;
454 if (min_cpu_irq > CPU_IRQ(i)) {
455 min_cpu_irq = CPU_IRQ(i);
456 min_loaded = i;
457 }
458 }
459 max_cpu_irq = ULONG_MAX;
460
461 tryanothercpu:
462 /* Look for heaviest loaded processor.
463 * We may come back to get the next heaviest loaded processor.
464 * Skip processors with trivial loads.
465 */
466 tmp_cpu_irq = 0;
467 tmp_loaded = -1;
468 for_each_online_cpu(i) {
469 if (i != CPU_TO_PACKAGEINDEX(i))
470 continue;
471 if (max_cpu_irq <= CPU_IRQ(i))
472 continue;
473 if (tmp_cpu_irq < CPU_IRQ(i)) {
474 tmp_cpu_irq = CPU_IRQ(i);
475 tmp_loaded = i;
476 }
477 }
478
479 if (tmp_loaded == -1) {
480 /* In the case of small number of heavy interrupt sources,
481 * loading some of the cpus too much. We use Ingo's original
482 * approach to rotate them around.
483 */
484 if (!first_attempt && imbalance >= useful_load_threshold) {
485 rotate_irqs_among_cpus(useful_load_threshold);
486 return;
487 }
488 goto not_worth_the_effort;
489 }
490
491 first_attempt = 0; /* heaviest search */
492 max_cpu_irq = tmp_cpu_irq; /* load */
493 max_loaded = tmp_loaded; /* processor */
494 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
495
496 Dprintk("max_loaded cpu = %d\n", max_loaded);
497 Dprintk("min_loaded cpu = %d\n", min_loaded);
498 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
499 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
500 Dprintk("load imbalance = %lu\n", imbalance);
501
502 /* if imbalance is less than approx 10% of max load, then
503 * observe diminishing returns action. - quit
504 */
505 if (imbalance < (max_cpu_irq >> 3)) {
506 Dprintk("Imbalance too trivial\n");
507 goto not_worth_the_effort;
508 }
509
510 tryanotherirq:
511 /* if we select an IRQ to move that can't go where we want, then
512 * see if there is another one to try.
513 */
514 move_this_load = 0;
515 selected_irq = -1;
516 for (j = 0; j < NR_IRQS; j++) {
517 /* Is this an active IRQ? */
518 if (!irq_desc[j].action)
519 continue;
520 if (imbalance <= IRQ_DELTA(max_loaded,j))
521 continue;
522 /* Try to find the IRQ that is closest to the imbalance
523 * without going over.
524 */
525 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
526 move_this_load = IRQ_DELTA(max_loaded,j);
527 selected_irq = j;
528 }
529 }
530 if (selected_irq == -1) {
531 goto tryanothercpu;
532 }
533
534 imbalance = move_this_load;
535
536 /* For physical_balance case, we accumlated both load
537 * values in the one of the siblings cpu_irq[],
538 * to use the same code for physical and logical processors
539 * as much as possible.
540 *
541 * NOTE: the cpu_irq[] array holds the sum of the load for
542 * sibling A and sibling B in the slot for the lowest numbered
543 * sibling (A), _AND_ the load for sibling B in the slot for
544 * the higher numbered sibling.
545 *
546 * We seek the least loaded sibling by making the comparison
547 * (A+B)/2 vs B
548 */
549 load = CPU_IRQ(min_loaded) >> 1;
550 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
551 if (load > CPU_IRQ(j)) {
552 /* This won't change cpu_sibling_map[min_loaded] */
553 load = CPU_IRQ(j);
554 min_loaded = j;
555 }
556 }
557
558 cpus_and(allowed_mask,
559 cpu_online_map,
560 balance_irq_affinity[selected_irq]);
561 target_cpu_mask = cpumask_of_cpu(min_loaded);
562 cpus_and(tmp, target_cpu_mask, allowed_mask);
563
564 if (!cpus_empty(tmp)) {
565
566 Dprintk("irq = %d moved to cpu = %d\n",
567 selected_irq, min_loaded);
568 /* mark for change destination */
569 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
570
571 /* Since we made a change, come back sooner to
572 * check for more variation.
573 */
574 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
575 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
576 return;
577 }
578 goto tryanotherirq;
579
580 not_worth_the_effort:
581 /*
582 * if we did not find an IRQ to move, then adjust the time interval
583 * upward
584 */
585 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
586 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
587 Dprintk("IRQ worth rotating not found\n");
588 return;
589 }
590
591 static int balanced_irq(void *unused)
592 {
593 int i;
594 unsigned long prev_balance_time = jiffies;
595 long time_remaining = balanced_irq_interval;
596
597 daemonize("kirqd");
598
599 /* push everything to CPU 0 to give us a starting point. */
600 for (i = 0 ; i < NR_IRQS ; i++) {
601 irq_desc[i].pending_mask = cpumask_of_cpu(0);
602 set_pending_irq(i, cpumask_of_cpu(0));
603 }
604
605 for ( ; ; ) {
606 time_remaining = schedule_timeout_interruptible(time_remaining);
607 try_to_freeze();
608 if (time_after(jiffies,
609 prev_balance_time+balanced_irq_interval)) {
610 preempt_disable();
611 do_irq_balance();
612 prev_balance_time = jiffies;
613 time_remaining = balanced_irq_interval;
614 preempt_enable();
615 }
616 }
617 return 0;
618 }
619
620 static int __init balanced_irq_init(void)
621 {
622 int i;
623 struct cpuinfo_x86 *c;
624 cpumask_t tmp;
625
626 cpus_shift_right(tmp, cpu_online_map, 2);
627 c = &boot_cpu_data;
628 /* When not overwritten by the command line ask subarchitecture. */
629 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
630 irqbalance_disabled = NO_BALANCE_IRQ;
631 if (irqbalance_disabled)
632 return 0;
633
634 /* disable irqbalance completely if there is only one processor online */
635 if (num_online_cpus() < 2) {
636 irqbalance_disabled = 1;
637 return 0;
638 }
639 /*
640 * Enable physical balance only if more than 1 physical processor
641 * is present
642 */
643 if (smp_num_siblings > 1 && !cpus_empty(tmp))
644 physical_balance = 1;
645
646 for_each_online_cpu(i) {
647 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
648 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
649 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
650 printk(KERN_ERR "balanced_irq_init: out of memory");
651 goto failed;
652 }
653 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
654 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
655 }
656
657 printk(KERN_INFO "Starting balanced_irq\n");
658 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
659 return 0;
660 else
661 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
662 failed:
663 for_each_possible_cpu(i) {
664 kfree(irq_cpu_data[i].irq_delta);
665 irq_cpu_data[i].irq_delta = NULL;
666 kfree(irq_cpu_data[i].last_irq);
667 irq_cpu_data[i].last_irq = NULL;
668 }
669 return 0;
670 }
671
672 int __init irqbalance_disable(char *str)
673 {
674 irqbalance_disabled = 1;
675 return 1;
676 }
677
678 __setup("noirqbalance", irqbalance_disable);
679
680 late_initcall(balanced_irq_init);
681 #endif /* CONFIG_IRQBALANCE */
682 #endif /* CONFIG_SMP */
683
684 #ifndef CONFIG_SMP
685 void fastcall send_IPI_self(int vector)
686 {
687 unsigned int cfg;
688
689 /*
690 * Wait for idle.
691 */
692 apic_wait_icr_idle();
693 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
694 /*
695 * Send the IPI. The write to APIC_ICR fires this off.
696 */
697 apic_write_around(APIC_ICR, cfg);
698 }
699 #endif /* !CONFIG_SMP */
700
701
702 /*
703 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
704 * specific CPU-side IRQs.
705 */
706
707 #define MAX_PIRQS 8
708 static int pirq_entries [MAX_PIRQS];
709 static int pirqs_enabled;
710 int skip_ioapic_setup;
711
712 static int __init ioapic_setup(char *str)
713 {
714 skip_ioapic_setup = 1;
715 return 1;
716 }
717
718 __setup("noapic", ioapic_setup);
719
720 static int __init ioapic_pirq_setup(char *str)
721 {
722 int i, max;
723 int ints[MAX_PIRQS+1];
724
725 get_options(str, ARRAY_SIZE(ints), ints);
726
727 for (i = 0; i < MAX_PIRQS; i++)
728 pirq_entries[i] = -1;
729
730 pirqs_enabled = 1;
731 apic_printk(APIC_VERBOSE, KERN_INFO
732 "PIRQ redirection, working around broken MP-BIOS.\n");
733 max = MAX_PIRQS;
734 if (ints[0] < MAX_PIRQS)
735 max = ints[0];
736
737 for (i = 0; i < max; i++) {
738 apic_printk(APIC_VERBOSE, KERN_DEBUG
739 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
740 /*
741 * PIRQs are mapped upside down, usually.
742 */
743 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
744 }
745 return 1;
746 }
747
748 __setup("pirq=", ioapic_pirq_setup);
749
750 /*
751 * Find the IRQ entry number of a certain pin.
752 */
753 static int find_irq_entry(int apic, int pin, int type)
754 {
755 int i;
756
757 for (i = 0; i < mp_irq_entries; i++)
758 if (mp_irqs[i].mpc_irqtype == type &&
759 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
760 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
761 mp_irqs[i].mpc_dstirq == pin)
762 return i;
763
764 return -1;
765 }
766
767 /*
768 * Find the pin to which IRQ[irq] (ISA) is connected
769 */
770 static int __init find_isa_irq_pin(int irq, int type)
771 {
772 int i;
773
774 for (i = 0; i < mp_irq_entries; i++) {
775 int lbus = mp_irqs[i].mpc_srcbus;
776
777 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
778 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
779 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
780 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
781 ) &&
782 (mp_irqs[i].mpc_irqtype == type) &&
783 (mp_irqs[i].mpc_srcbusirq == irq))
784
785 return mp_irqs[i].mpc_dstirq;
786 }
787 return -1;
788 }
789
790 static int __init find_isa_irq_apic(int irq, int type)
791 {
792 int i;
793
794 for (i = 0; i < mp_irq_entries; i++) {
795 int lbus = mp_irqs[i].mpc_srcbus;
796
797 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
798 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
799 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
800 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
801 ) &&
802 (mp_irqs[i].mpc_irqtype == type) &&
803 (mp_irqs[i].mpc_srcbusirq == irq))
804 break;
805 }
806 if (i < mp_irq_entries) {
807 int apic;
808 for(apic = 0; apic < nr_ioapics; apic++) {
809 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
810 return apic;
811 }
812 }
813
814 return -1;
815 }
816
817 /*
818 * Find a specific PCI IRQ entry.
819 * Not an __init, possibly needed by modules
820 */
821 static int pin_2_irq(int idx, int apic, int pin);
822
823 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
824 {
825 int apic, i, best_guess = -1;
826
827 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
828 "slot:%d, pin:%d.\n", bus, slot, pin);
829 if (mp_bus_id_to_pci_bus[bus] == -1) {
830 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
831 return -1;
832 }
833 for (i = 0; i < mp_irq_entries; i++) {
834 int lbus = mp_irqs[i].mpc_srcbus;
835
836 for (apic = 0; apic < nr_ioapics; apic++)
837 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
838 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
839 break;
840
841 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
842 !mp_irqs[i].mpc_irqtype &&
843 (bus == lbus) &&
844 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
845 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
846
847 if (!(apic || IO_APIC_IRQ(irq)))
848 continue;
849
850 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
851 return irq;
852 /*
853 * Use the first all-but-pin matching entry as a
854 * best-guess fuzzy result for broken mptables.
855 */
856 if (best_guess < 0)
857 best_guess = irq;
858 }
859 }
860 return best_guess;
861 }
862 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
863
864 /*
865 * This function currently is only a helper for the i386 smp boot process where
866 * we need to reprogram the ioredtbls to cater for the cpus which have come online
867 * so mask in all cases should simply be TARGET_CPUS
868 */
869 #ifdef CONFIG_SMP
870 void __init setup_ioapic_dest(void)
871 {
872 int pin, ioapic, irq, irq_entry;
873
874 if (skip_ioapic_setup == 1)
875 return;
876
877 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
878 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
879 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
880 if (irq_entry == -1)
881 continue;
882 irq = pin_2_irq(irq_entry, ioapic, pin);
883 set_ioapic_affinity_irq(irq, TARGET_CPUS);
884 }
885
886 }
887 }
888 #endif
889
890 /*
891 * EISA Edge/Level control register, ELCR
892 */
893 static int EISA_ELCR(unsigned int irq)
894 {
895 if (irq < 16) {
896 unsigned int port = 0x4d0 + (irq >> 3);
897 return (inb(port) >> (irq & 7)) & 1;
898 }
899 apic_printk(APIC_VERBOSE, KERN_INFO
900 "Broken MPtable reports ISA irq %d\n", irq);
901 return 0;
902 }
903
904 /* EISA interrupts are always polarity zero and can be edge or level
905 * trigger depending on the ELCR value. If an interrupt is listed as
906 * EISA conforming in the MP table, that means its trigger type must
907 * be read in from the ELCR */
908
909 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
910 #define default_EISA_polarity(idx) (0)
911
912 /* ISA interrupts are always polarity zero edge triggered,
913 * when listed as conforming in the MP table. */
914
915 #define default_ISA_trigger(idx) (0)
916 #define default_ISA_polarity(idx) (0)
917
918 /* PCI interrupts are always polarity one level triggered,
919 * when listed as conforming in the MP table. */
920
921 #define default_PCI_trigger(idx) (1)
922 #define default_PCI_polarity(idx) (1)
923
924 /* MCA interrupts are always polarity zero level triggered,
925 * when listed as conforming in the MP table. */
926
927 #define default_MCA_trigger(idx) (1)
928 #define default_MCA_polarity(idx) (0)
929
930 /* NEC98 interrupts are always polarity zero edge triggered,
931 * when listed as conforming in the MP table. */
932
933 #define default_NEC98_trigger(idx) (0)
934 #define default_NEC98_polarity(idx) (0)
935
936 static int __init MPBIOS_polarity(int idx)
937 {
938 int bus = mp_irqs[idx].mpc_srcbus;
939 int polarity;
940
941 /*
942 * Determine IRQ line polarity (high active or low active):
943 */
944 switch (mp_irqs[idx].mpc_irqflag & 3)
945 {
946 case 0: /* conforms, ie. bus-type dependent polarity */
947 {
948 switch (mp_bus_id_to_type[bus])
949 {
950 case MP_BUS_ISA: /* ISA pin */
951 {
952 polarity = default_ISA_polarity(idx);
953 break;
954 }
955 case MP_BUS_EISA: /* EISA pin */
956 {
957 polarity = default_EISA_polarity(idx);
958 break;
959 }
960 case MP_BUS_PCI: /* PCI pin */
961 {
962 polarity = default_PCI_polarity(idx);
963 break;
964 }
965 case MP_BUS_MCA: /* MCA pin */
966 {
967 polarity = default_MCA_polarity(idx);
968 break;
969 }
970 case MP_BUS_NEC98: /* NEC 98 pin */
971 {
972 polarity = default_NEC98_polarity(idx);
973 break;
974 }
975 default:
976 {
977 printk(KERN_WARNING "broken BIOS!!\n");
978 polarity = 1;
979 break;
980 }
981 }
982 break;
983 }
984 case 1: /* high active */
985 {
986 polarity = 0;
987 break;
988 }
989 case 2: /* reserved */
990 {
991 printk(KERN_WARNING "broken BIOS!!\n");
992 polarity = 1;
993 break;
994 }
995 case 3: /* low active */
996 {
997 polarity = 1;
998 break;
999 }
1000 default: /* invalid */
1001 {
1002 printk(KERN_WARNING "broken BIOS!!\n");
1003 polarity = 1;
1004 break;
1005 }
1006 }
1007 return polarity;
1008 }
1009
1010 static int MPBIOS_trigger(int idx)
1011 {
1012 int bus = mp_irqs[idx].mpc_srcbus;
1013 int trigger;
1014
1015 /*
1016 * Determine IRQ trigger mode (edge or level sensitive):
1017 */
1018 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1019 {
1020 case 0: /* conforms, ie. bus-type dependent */
1021 {
1022 switch (mp_bus_id_to_type[bus])
1023 {
1024 case MP_BUS_ISA: /* ISA pin */
1025 {
1026 trigger = default_ISA_trigger(idx);
1027 break;
1028 }
1029 case MP_BUS_EISA: /* EISA pin */
1030 {
1031 trigger = default_EISA_trigger(idx);
1032 break;
1033 }
1034 case MP_BUS_PCI: /* PCI pin */
1035 {
1036 trigger = default_PCI_trigger(idx);
1037 break;
1038 }
1039 case MP_BUS_MCA: /* MCA pin */
1040 {
1041 trigger = default_MCA_trigger(idx);
1042 break;
1043 }
1044 case MP_BUS_NEC98: /* NEC 98 pin */
1045 {
1046 trigger = default_NEC98_trigger(idx);
1047 break;
1048 }
1049 default:
1050 {
1051 printk(KERN_WARNING "broken BIOS!!\n");
1052 trigger = 1;
1053 break;
1054 }
1055 }
1056 break;
1057 }
1058 case 1: /* edge */
1059 {
1060 trigger = 0;
1061 break;
1062 }
1063 case 2: /* reserved */
1064 {
1065 printk(KERN_WARNING "broken BIOS!!\n");
1066 trigger = 1;
1067 break;
1068 }
1069 case 3: /* level */
1070 {
1071 trigger = 1;
1072 break;
1073 }
1074 default: /* invalid */
1075 {
1076 printk(KERN_WARNING "broken BIOS!!\n");
1077 trigger = 0;
1078 break;
1079 }
1080 }
1081 return trigger;
1082 }
1083
1084 static inline int irq_polarity(int idx)
1085 {
1086 return MPBIOS_polarity(idx);
1087 }
1088
1089 static inline int irq_trigger(int idx)
1090 {
1091 return MPBIOS_trigger(idx);
1092 }
1093
1094 static int pin_2_irq(int idx, int apic, int pin)
1095 {
1096 int irq, i;
1097 int bus = mp_irqs[idx].mpc_srcbus;
1098
1099 /*
1100 * Debugging check, we are in big trouble if this message pops up!
1101 */
1102 if (mp_irqs[idx].mpc_dstirq != pin)
1103 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1104
1105 switch (mp_bus_id_to_type[bus])
1106 {
1107 case MP_BUS_ISA: /* ISA pin */
1108 case MP_BUS_EISA:
1109 case MP_BUS_MCA:
1110 case MP_BUS_NEC98:
1111 {
1112 irq = mp_irqs[idx].mpc_srcbusirq;
1113 break;
1114 }
1115 case MP_BUS_PCI: /* PCI pin */
1116 {
1117 /*
1118 * PCI IRQs are mapped in order
1119 */
1120 i = irq = 0;
1121 while (i < apic)
1122 irq += nr_ioapic_registers[i++];
1123 irq += pin;
1124
1125 /*
1126 * For MPS mode, so far only needed by ES7000 platform
1127 */
1128 if (ioapic_renumber_irq)
1129 irq = ioapic_renumber_irq(apic, irq);
1130
1131 break;
1132 }
1133 default:
1134 {
1135 printk(KERN_ERR "unknown bus type %d.\n",bus);
1136 irq = 0;
1137 break;
1138 }
1139 }
1140
1141 /*
1142 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1143 */
1144 if ((pin >= 16) && (pin <= 23)) {
1145 if (pirq_entries[pin-16] != -1) {
1146 if (!pirq_entries[pin-16]) {
1147 apic_printk(APIC_VERBOSE, KERN_DEBUG
1148 "disabling PIRQ%d\n", pin-16);
1149 } else {
1150 irq = pirq_entries[pin-16];
1151 apic_printk(APIC_VERBOSE, KERN_DEBUG
1152 "using PIRQ%d -> IRQ %d\n",
1153 pin-16, irq);
1154 }
1155 }
1156 }
1157 return irq;
1158 }
1159
1160 static inline int IO_APIC_irq_trigger(int irq)
1161 {
1162 int apic, idx, pin;
1163
1164 for (apic = 0; apic < nr_ioapics; apic++) {
1165 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1166 idx = find_irq_entry(apic,pin,mp_INT);
1167 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1168 return irq_trigger(idx);
1169 }
1170 }
1171 /*
1172 * nonexistent IRQs are edge default
1173 */
1174 return 0;
1175 }
1176
1177 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1178 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1179
1180 static int __assign_irq_vector(int irq)
1181 {
1182 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1183 int vector;
1184
1185 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1186
1187 if (irq_vector[irq] > 0)
1188 return irq_vector[irq];
1189
1190 current_vector += 8;
1191 if (current_vector == SYSCALL_VECTOR)
1192 current_vector += 8;
1193
1194 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1195 offset++;
1196 if (!(offset % 8))
1197 return -ENOSPC;
1198 current_vector = FIRST_DEVICE_VECTOR + offset;
1199 }
1200
1201 vector = current_vector;
1202 irq_vector[irq] = vector;
1203
1204 return vector;
1205 }
1206
1207 static int assign_irq_vector(int irq)
1208 {
1209 unsigned long flags;
1210 int vector;
1211
1212 spin_lock_irqsave(&vector_lock, flags);
1213 vector = __assign_irq_vector(irq);
1214 spin_unlock_irqrestore(&vector_lock, flags);
1215
1216 return vector;
1217 }
1218 static struct irq_chip ioapic_chip;
1219
1220 #define IOAPIC_AUTO -1
1221 #define IOAPIC_EDGE 0
1222 #define IOAPIC_LEVEL 1
1223
1224 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1225 {
1226 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1227 trigger == IOAPIC_LEVEL)
1228 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1229 handle_fasteoi_irq, "fasteoi");
1230 else
1231 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1232 handle_edge_irq, "edge");
1233 set_intr_gate(vector, interrupt[irq]);
1234 }
1235
1236 static void __init setup_IO_APIC_irqs(void)
1237 {
1238 struct IO_APIC_route_entry entry;
1239 int apic, pin, idx, irq, first_notcon = 1, vector;
1240 unsigned long flags;
1241
1242 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1243
1244 for (apic = 0; apic < nr_ioapics; apic++) {
1245 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1246
1247 /*
1248 * add it to the IO-APIC irq-routing table:
1249 */
1250 memset(&entry,0,sizeof(entry));
1251
1252 entry.delivery_mode = INT_DELIVERY_MODE;
1253 entry.dest_mode = INT_DEST_MODE;
1254 entry.mask = 0; /* enable IRQ */
1255 entry.dest.logical.logical_dest =
1256 cpu_mask_to_apicid(TARGET_CPUS);
1257
1258 idx = find_irq_entry(apic,pin,mp_INT);
1259 if (idx == -1) {
1260 if (first_notcon) {
1261 apic_printk(APIC_VERBOSE, KERN_DEBUG
1262 " IO-APIC (apicid-pin) %d-%d",
1263 mp_ioapics[apic].mpc_apicid,
1264 pin);
1265 first_notcon = 0;
1266 } else
1267 apic_printk(APIC_VERBOSE, ", %d-%d",
1268 mp_ioapics[apic].mpc_apicid, pin);
1269 continue;
1270 }
1271
1272 entry.trigger = irq_trigger(idx);
1273 entry.polarity = irq_polarity(idx);
1274
1275 if (irq_trigger(idx)) {
1276 entry.trigger = 1;
1277 entry.mask = 1;
1278 }
1279
1280 irq = pin_2_irq(idx, apic, pin);
1281 /*
1282 * skip adding the timer int on secondary nodes, which causes
1283 * a small but painful rift in the time-space continuum
1284 */
1285 if (multi_timer_check(apic, irq))
1286 continue;
1287 else
1288 add_pin_to_irq(irq, apic, pin);
1289
1290 if (!apic && !IO_APIC_IRQ(irq))
1291 continue;
1292
1293 if (IO_APIC_IRQ(irq)) {
1294 vector = assign_irq_vector(irq);
1295 entry.vector = vector;
1296 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1297
1298 if (!apic && (irq < 16))
1299 disable_8259A_irq(irq);
1300 }
1301 ioapic_write_entry(apic, pin, entry);
1302 spin_lock_irqsave(&ioapic_lock, flags);
1303 set_native_irq_info(irq, TARGET_CPUS);
1304 spin_unlock_irqrestore(&ioapic_lock, flags);
1305 }
1306 }
1307
1308 if (!first_notcon)
1309 apic_printk(APIC_VERBOSE, " not connected.\n");
1310 }
1311
1312 /*
1313 * Set up the 8259A-master output pin:
1314 */
1315 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1316 {
1317 struct IO_APIC_route_entry entry;
1318
1319 memset(&entry,0,sizeof(entry));
1320
1321 disable_8259A_irq(0);
1322
1323 /* mask LVT0 */
1324 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1325
1326 /*
1327 * We use logical delivery to get the timer IRQ
1328 * to the first CPU.
1329 */
1330 entry.dest_mode = INT_DEST_MODE;
1331 entry.mask = 0; /* unmask IRQ now */
1332 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1333 entry.delivery_mode = INT_DELIVERY_MODE;
1334 entry.polarity = 0;
1335 entry.trigger = 0;
1336 entry.vector = vector;
1337
1338 /*
1339 * The timer IRQ doesn't have to know that behind the
1340 * scene we have a 8259A-master in AEOI mode ...
1341 */
1342 irq_desc[0].chip = &ioapic_chip;
1343 set_irq_handler(0, handle_edge_irq);
1344
1345 /*
1346 * Add it to the IO-APIC irq-routing table:
1347 */
1348 ioapic_write_entry(apic, pin, entry);
1349
1350 enable_8259A_irq(0);
1351 }
1352
1353 static inline void UNEXPECTED_IO_APIC(void)
1354 {
1355 }
1356
1357 void __init print_IO_APIC(void)
1358 {
1359 int apic, i;
1360 union IO_APIC_reg_00 reg_00;
1361 union IO_APIC_reg_01 reg_01;
1362 union IO_APIC_reg_02 reg_02;
1363 union IO_APIC_reg_03 reg_03;
1364 unsigned long flags;
1365
1366 if (apic_verbosity == APIC_QUIET)
1367 return;
1368
1369 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1370 for (i = 0; i < nr_ioapics; i++)
1371 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1372 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1373
1374 /*
1375 * We are a bit conservative about what we expect. We have to
1376 * know about every hardware change ASAP.
1377 */
1378 printk(KERN_INFO "testing the IO APIC.......................\n");
1379
1380 for (apic = 0; apic < nr_ioapics; apic++) {
1381
1382 spin_lock_irqsave(&ioapic_lock, flags);
1383 reg_00.raw = io_apic_read(apic, 0);
1384 reg_01.raw = io_apic_read(apic, 1);
1385 if (reg_01.bits.version >= 0x10)
1386 reg_02.raw = io_apic_read(apic, 2);
1387 if (reg_01.bits.version >= 0x20)
1388 reg_03.raw = io_apic_read(apic, 3);
1389 spin_unlock_irqrestore(&ioapic_lock, flags);
1390
1391 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1392 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1393 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1394 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1395 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1396 if (reg_00.bits.ID >= get_physical_broadcast())
1397 UNEXPECTED_IO_APIC();
1398 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1399 UNEXPECTED_IO_APIC();
1400
1401 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1402 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1403 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1404 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1405 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1406 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1407 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1408 (reg_01.bits.entries != 0x2E) &&
1409 (reg_01.bits.entries != 0x3F)
1410 )
1411 UNEXPECTED_IO_APIC();
1412
1413 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1414 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1415 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1416 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1417 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1418 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1419 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1420 )
1421 UNEXPECTED_IO_APIC();
1422 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1423 UNEXPECTED_IO_APIC();
1424
1425 /*
1426 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1427 * but the value of reg_02 is read as the previous read register
1428 * value, so ignore it if reg_02 == reg_01.
1429 */
1430 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1431 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1432 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1433 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1434 UNEXPECTED_IO_APIC();
1435 }
1436
1437 /*
1438 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1439 * or reg_03, but the value of reg_0[23] is read as the previous read
1440 * register value, so ignore it if reg_03 == reg_0[12].
1441 */
1442 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1443 reg_03.raw != reg_01.raw) {
1444 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1445 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1446 if (reg_03.bits.__reserved_1)
1447 UNEXPECTED_IO_APIC();
1448 }
1449
1450 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1451
1452 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1453 " Stat Dest Deli Vect: \n");
1454
1455 for (i = 0; i <= reg_01.bits.entries; i++) {
1456 struct IO_APIC_route_entry entry;
1457
1458 entry = ioapic_read_entry(apic, i);
1459
1460 printk(KERN_DEBUG " %02x %03X %02X ",
1461 i,
1462 entry.dest.logical.logical_dest,
1463 entry.dest.physical.physical_dest
1464 );
1465
1466 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1467 entry.mask,
1468 entry.trigger,
1469 entry.irr,
1470 entry.polarity,
1471 entry.delivery_status,
1472 entry.dest_mode,
1473 entry.delivery_mode,
1474 entry.vector
1475 );
1476 }
1477 }
1478 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1479 for (i = 0; i < NR_IRQS; i++) {
1480 struct irq_pin_list *entry = irq_2_pin + i;
1481 if (entry->pin < 0)
1482 continue;
1483 printk(KERN_DEBUG "IRQ%d ", i);
1484 for (;;) {
1485 printk("-> %d:%d", entry->apic, entry->pin);
1486 if (!entry->next)
1487 break;
1488 entry = irq_2_pin + entry->next;
1489 }
1490 printk("\n");
1491 }
1492
1493 printk(KERN_INFO ".................................... done.\n");
1494
1495 return;
1496 }
1497
1498 #if 0
1499
1500 static void print_APIC_bitfield (int base)
1501 {
1502 unsigned int v;
1503 int i, j;
1504
1505 if (apic_verbosity == APIC_QUIET)
1506 return;
1507
1508 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1509 for (i = 0; i < 8; i++) {
1510 v = apic_read(base + i*0x10);
1511 for (j = 0; j < 32; j++) {
1512 if (v & (1<<j))
1513 printk("1");
1514 else
1515 printk("0");
1516 }
1517 printk("\n");
1518 }
1519 }
1520
1521 void /*__init*/ print_local_APIC(void * dummy)
1522 {
1523 unsigned int v, ver, maxlvt;
1524
1525 if (apic_verbosity == APIC_QUIET)
1526 return;
1527
1528 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1529 smp_processor_id(), hard_smp_processor_id());
1530 v = apic_read(APIC_ID);
1531 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1532 v = apic_read(APIC_LVR);
1533 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1534 ver = GET_APIC_VERSION(v);
1535 maxlvt = get_maxlvt();
1536
1537 v = apic_read(APIC_TASKPRI);
1538 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1539
1540 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1541 v = apic_read(APIC_ARBPRI);
1542 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1543 v & APIC_ARBPRI_MASK);
1544 v = apic_read(APIC_PROCPRI);
1545 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1546 }
1547
1548 v = apic_read(APIC_EOI);
1549 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1550 v = apic_read(APIC_RRR);
1551 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1552 v = apic_read(APIC_LDR);
1553 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1554 v = apic_read(APIC_DFR);
1555 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1556 v = apic_read(APIC_SPIV);
1557 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1558
1559 printk(KERN_DEBUG "... APIC ISR field:\n");
1560 print_APIC_bitfield(APIC_ISR);
1561 printk(KERN_DEBUG "... APIC TMR field:\n");
1562 print_APIC_bitfield(APIC_TMR);
1563 printk(KERN_DEBUG "... APIC IRR field:\n");
1564 print_APIC_bitfield(APIC_IRR);
1565
1566 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1567 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1568 apic_write(APIC_ESR, 0);
1569 v = apic_read(APIC_ESR);
1570 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1571 }
1572
1573 v = apic_read(APIC_ICR);
1574 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1575 v = apic_read(APIC_ICR2);
1576 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1577
1578 v = apic_read(APIC_LVTT);
1579 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1580
1581 if (maxlvt > 3) { /* PC is LVT#4. */
1582 v = apic_read(APIC_LVTPC);
1583 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1584 }
1585 v = apic_read(APIC_LVT0);
1586 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1587 v = apic_read(APIC_LVT1);
1588 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1589
1590 if (maxlvt > 2) { /* ERR is LVT#3. */
1591 v = apic_read(APIC_LVTERR);
1592 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1593 }
1594
1595 v = apic_read(APIC_TMICT);
1596 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1597 v = apic_read(APIC_TMCCT);
1598 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1599 v = apic_read(APIC_TDCR);
1600 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1601 printk("\n");
1602 }
1603
1604 void print_all_local_APICs (void)
1605 {
1606 on_each_cpu(print_local_APIC, NULL, 1, 1);
1607 }
1608
1609 void /*__init*/ print_PIC(void)
1610 {
1611 unsigned int v;
1612 unsigned long flags;
1613
1614 if (apic_verbosity == APIC_QUIET)
1615 return;
1616
1617 printk(KERN_DEBUG "\nprinting PIC contents\n");
1618
1619 spin_lock_irqsave(&i8259A_lock, flags);
1620
1621 v = inb(0xa1) << 8 | inb(0x21);
1622 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1623
1624 v = inb(0xa0) << 8 | inb(0x20);
1625 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1626
1627 outb(0x0b,0xa0);
1628 outb(0x0b,0x20);
1629 v = inb(0xa0) << 8 | inb(0x20);
1630 outb(0x0a,0xa0);
1631 outb(0x0a,0x20);
1632
1633 spin_unlock_irqrestore(&i8259A_lock, flags);
1634
1635 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1636
1637 v = inb(0x4d1) << 8 | inb(0x4d0);
1638 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1639 }
1640
1641 #endif /* 0 */
1642
1643 static void __init enable_IO_APIC(void)
1644 {
1645 union IO_APIC_reg_01 reg_01;
1646 int i8259_apic, i8259_pin;
1647 int i, apic;
1648 unsigned long flags;
1649
1650 for (i = 0; i < PIN_MAP_SIZE; i++) {
1651 irq_2_pin[i].pin = -1;
1652 irq_2_pin[i].next = 0;
1653 }
1654 if (!pirqs_enabled)
1655 for (i = 0; i < MAX_PIRQS; i++)
1656 pirq_entries[i] = -1;
1657
1658 /*
1659 * The number of IO-APIC IRQ registers (== #pins):
1660 */
1661 for (apic = 0; apic < nr_ioapics; apic++) {
1662 spin_lock_irqsave(&ioapic_lock, flags);
1663 reg_01.raw = io_apic_read(apic, 1);
1664 spin_unlock_irqrestore(&ioapic_lock, flags);
1665 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1666 }
1667 for(apic = 0; apic < nr_ioapics; apic++) {
1668 int pin;
1669 /* See if any of the pins is in ExtINT mode */
1670 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1671 struct IO_APIC_route_entry entry;
1672 entry = ioapic_read_entry(apic, pin);
1673
1674
1675 /* If the interrupt line is enabled and in ExtInt mode
1676 * I have found the pin where the i8259 is connected.
1677 */
1678 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1679 ioapic_i8259.apic = apic;
1680 ioapic_i8259.pin = pin;
1681 goto found_i8259;
1682 }
1683 }
1684 }
1685 found_i8259:
1686 /* Look to see what if the MP table has reported the ExtINT */
1687 /* If we could not find the appropriate pin by looking at the ioapic
1688 * the i8259 probably is not connected the ioapic but give the
1689 * mptable a chance anyway.
1690 */
1691 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1692 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1693 /* Trust the MP table if nothing is setup in the hardware */
1694 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1695 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1696 ioapic_i8259.pin = i8259_pin;
1697 ioapic_i8259.apic = i8259_apic;
1698 }
1699 /* Complain if the MP table and the hardware disagree */
1700 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1701 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1702 {
1703 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1704 }
1705
1706 /*
1707 * Do not trust the IO-APIC being empty at bootup
1708 */
1709 clear_IO_APIC();
1710 }
1711
1712 /*
1713 * Not an __init, needed by the reboot code
1714 */
1715 void disable_IO_APIC(void)
1716 {
1717 /*
1718 * Clear the IO-APIC before rebooting:
1719 */
1720 clear_IO_APIC();
1721
1722 /*
1723 * If the i8259 is routed through an IOAPIC
1724 * Put that IOAPIC in virtual wire mode
1725 * so legacy interrupts can be delivered.
1726 */
1727 if (ioapic_i8259.pin != -1) {
1728 struct IO_APIC_route_entry entry;
1729
1730 memset(&entry, 0, sizeof(entry));
1731 entry.mask = 0; /* Enabled */
1732 entry.trigger = 0; /* Edge */
1733 entry.irr = 0;
1734 entry.polarity = 0; /* High */
1735 entry.delivery_status = 0;
1736 entry.dest_mode = 0; /* Physical */
1737 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1738 entry.vector = 0;
1739 entry.dest.physical.physical_dest =
1740 GET_APIC_ID(apic_read(APIC_ID));
1741
1742 /*
1743 * Add it to the IO-APIC irq-routing table:
1744 */
1745 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1746 }
1747 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1748 }
1749
1750 /*
1751 * function to set the IO-APIC physical IDs based on the
1752 * values stored in the MPC table.
1753 *
1754 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1755 */
1756
1757 #ifndef CONFIG_X86_NUMAQ
1758 static void __init setup_ioapic_ids_from_mpc(void)
1759 {
1760 union IO_APIC_reg_00 reg_00;
1761 physid_mask_t phys_id_present_map;
1762 int apic;
1763 int i;
1764 unsigned char old_id;
1765 unsigned long flags;
1766
1767 /*
1768 * Don't check I/O APIC IDs for xAPIC systems. They have
1769 * no meaning without the serial APIC bus.
1770 */
1771 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1772 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1773 return;
1774 /*
1775 * This is broken; anything with a real cpu count has to
1776 * circumvent this idiocy regardless.
1777 */
1778 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1779
1780 /*
1781 * Set the IOAPIC ID to the value stored in the MPC table.
1782 */
1783 for (apic = 0; apic < nr_ioapics; apic++) {
1784
1785 /* Read the register 0 value */
1786 spin_lock_irqsave(&ioapic_lock, flags);
1787 reg_00.raw = io_apic_read(apic, 0);
1788 spin_unlock_irqrestore(&ioapic_lock, flags);
1789
1790 old_id = mp_ioapics[apic].mpc_apicid;
1791
1792 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1793 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1794 apic, mp_ioapics[apic].mpc_apicid);
1795 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1796 reg_00.bits.ID);
1797 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1798 }
1799
1800 /*
1801 * Sanity check, is the ID really free? Every APIC in a
1802 * system must have a unique ID or we get lots of nice
1803 * 'stuck on smp_invalidate_needed IPI wait' messages.
1804 */
1805 if (check_apicid_used(phys_id_present_map,
1806 mp_ioapics[apic].mpc_apicid)) {
1807 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1808 apic, mp_ioapics[apic].mpc_apicid);
1809 for (i = 0; i < get_physical_broadcast(); i++)
1810 if (!physid_isset(i, phys_id_present_map))
1811 break;
1812 if (i >= get_physical_broadcast())
1813 panic("Max APIC ID exceeded!\n");
1814 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1815 i);
1816 physid_set(i, phys_id_present_map);
1817 mp_ioapics[apic].mpc_apicid = i;
1818 } else {
1819 physid_mask_t tmp;
1820 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1821 apic_printk(APIC_VERBOSE, "Setting %d in the "
1822 "phys_id_present_map\n",
1823 mp_ioapics[apic].mpc_apicid);
1824 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1825 }
1826
1827
1828 /*
1829 * We need to adjust the IRQ routing table
1830 * if the ID changed.
1831 */
1832 if (old_id != mp_ioapics[apic].mpc_apicid)
1833 for (i = 0; i < mp_irq_entries; i++)
1834 if (mp_irqs[i].mpc_dstapic == old_id)
1835 mp_irqs[i].mpc_dstapic
1836 = mp_ioapics[apic].mpc_apicid;
1837
1838 /*
1839 * Read the right value from the MPC table and
1840 * write it into the ID register.
1841 */
1842 apic_printk(APIC_VERBOSE, KERN_INFO
1843 "...changing IO-APIC physical APIC ID to %d ...",
1844 mp_ioapics[apic].mpc_apicid);
1845
1846 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1847 spin_lock_irqsave(&ioapic_lock, flags);
1848 io_apic_write(apic, 0, reg_00.raw);
1849 spin_unlock_irqrestore(&ioapic_lock, flags);
1850
1851 /*
1852 * Sanity check
1853 */
1854 spin_lock_irqsave(&ioapic_lock, flags);
1855 reg_00.raw = io_apic_read(apic, 0);
1856 spin_unlock_irqrestore(&ioapic_lock, flags);
1857 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1858 printk("could not set ID!\n");
1859 else
1860 apic_printk(APIC_VERBOSE, " ok.\n");
1861 }
1862 }
1863 #else
1864 static void __init setup_ioapic_ids_from_mpc(void) { }
1865 #endif
1866
1867 /*
1868 * There is a nasty bug in some older SMP boards, their mptable lies
1869 * about the timer IRQ. We do the following to work around the situation:
1870 *
1871 * - timer IRQ defaults to IO-APIC IRQ
1872 * - if this function detects that timer IRQs are defunct, then we fall
1873 * back to ISA timer IRQs
1874 */
1875 static int __init timer_irq_works(void)
1876 {
1877 unsigned long t1 = jiffies;
1878
1879 local_irq_enable();
1880 /* Let ten ticks pass... */
1881 mdelay((10 * 1000) / HZ);
1882
1883 /*
1884 * Expect a few ticks at least, to be sure some possible
1885 * glue logic does not lock up after one or two first
1886 * ticks in a non-ExtINT mode. Also the local APIC
1887 * might have cached one ExtINT interrupt. Finally, at
1888 * least one tick may be lost due to delays.
1889 */
1890 if (jiffies - t1 > 4)
1891 return 1;
1892
1893 return 0;
1894 }
1895
1896 /*
1897 * In the SMP+IOAPIC case it might happen that there are an unspecified
1898 * number of pending IRQ events unhandled. These cases are very rare,
1899 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1900 * better to do it this way as thus we do not have to be aware of
1901 * 'pending' interrupts in the IRQ path, except at this point.
1902 */
1903 /*
1904 * Edge triggered needs to resend any interrupt
1905 * that was delayed but this is now handled in the device
1906 * independent code.
1907 */
1908
1909 /*
1910 * Startup quirk:
1911 *
1912 * Starting up a edge-triggered IO-APIC interrupt is
1913 * nasty - we need to make sure that we get the edge.
1914 * If it is already asserted for some reason, we need
1915 * return 1 to indicate that is was pending.
1916 *
1917 * This is not complete - we should be able to fake
1918 * an edge even if it isn't on the 8259A...
1919 *
1920 * (We do this for level-triggered IRQs too - it cannot hurt.)
1921 */
1922 static unsigned int startup_ioapic_irq(unsigned int irq)
1923 {
1924 int was_pending = 0;
1925 unsigned long flags;
1926
1927 spin_lock_irqsave(&ioapic_lock, flags);
1928 if (irq < 16) {
1929 disable_8259A_irq(irq);
1930 if (i8259A_irq_pending(irq))
1931 was_pending = 1;
1932 }
1933 __unmask_IO_APIC_irq(irq);
1934 spin_unlock_irqrestore(&ioapic_lock, flags);
1935
1936 return was_pending;
1937 }
1938
1939 static void ack_ioapic_irq(unsigned int irq)
1940 {
1941 move_native_irq(irq);
1942 ack_APIC_irq();
1943 }
1944
1945 static void ack_ioapic_quirk_irq(unsigned int irq)
1946 {
1947 unsigned long v;
1948 int i;
1949
1950 move_native_irq(irq);
1951 /*
1952 * It appears there is an erratum which affects at least version 0x11
1953 * of I/O APIC (that's the 82093AA and cores integrated into various
1954 * chipsets). Under certain conditions a level-triggered interrupt is
1955 * erroneously delivered as edge-triggered one but the respective IRR
1956 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1957 * message but it will never arrive and further interrupts are blocked
1958 * from the source. The exact reason is so far unknown, but the
1959 * phenomenon was observed when two consecutive interrupt requests
1960 * from a given source get delivered to the same CPU and the source is
1961 * temporarily disabled in between.
1962 *
1963 * A workaround is to simulate an EOI message manually. We achieve it
1964 * by setting the trigger mode to edge and then to level when the edge
1965 * trigger mode gets detected in the TMR of a local APIC for a
1966 * level-triggered interrupt. We mask the source for the time of the
1967 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1968 * The idea is from Manfred Spraul. --macro
1969 */
1970 i = irq_vector[irq];
1971
1972 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1973
1974 ack_APIC_irq();
1975
1976 if (!(v & (1 << (i & 0x1f)))) {
1977 atomic_inc(&irq_mis_count);
1978 spin_lock(&ioapic_lock);
1979 __mask_and_edge_IO_APIC_irq(irq);
1980 __unmask_and_level_IO_APIC_irq(irq);
1981 spin_unlock(&ioapic_lock);
1982 }
1983 }
1984
1985 static int ioapic_retrigger_irq(unsigned int irq)
1986 {
1987 send_IPI_self(irq_vector[irq]);
1988
1989 return 1;
1990 }
1991
1992 static struct irq_chip ioapic_chip __read_mostly = {
1993 .name = "IO-APIC",
1994 .startup = startup_ioapic_irq,
1995 .mask = mask_IO_APIC_irq,
1996 .unmask = unmask_IO_APIC_irq,
1997 .ack = ack_ioapic_irq,
1998 .eoi = ack_ioapic_quirk_irq,
1999 #ifdef CONFIG_SMP
2000 .set_affinity = set_ioapic_affinity_irq,
2001 #endif
2002 .retrigger = ioapic_retrigger_irq,
2003 };
2004
2005
2006 static inline void init_IO_APIC_traps(void)
2007 {
2008 int irq;
2009
2010 /*
2011 * NOTE! The local APIC isn't very good at handling
2012 * multiple interrupts at the same interrupt level.
2013 * As the interrupt level is determined by taking the
2014 * vector number and shifting that right by 4, we
2015 * want to spread these out a bit so that they don't
2016 * all fall in the same interrupt level.
2017 *
2018 * Also, we've got to be careful not to trash gate
2019 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2020 */
2021 for (irq = 0; irq < NR_IRQS ; irq++) {
2022 int tmp = irq;
2023 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2024 /*
2025 * Hmm.. We don't have an entry for this,
2026 * so default to an old-fashioned 8259
2027 * interrupt if we can..
2028 */
2029 if (irq < 16)
2030 make_8259A_irq(irq);
2031 else
2032 /* Strange. Oh, well.. */
2033 irq_desc[irq].chip = &no_irq_chip;
2034 }
2035 }
2036 }
2037
2038 /*
2039 * The local APIC irq-chip implementation:
2040 */
2041
2042 static void ack_apic(unsigned int irq)
2043 {
2044 ack_APIC_irq();
2045 }
2046
2047 static void mask_lapic_irq (unsigned int irq)
2048 {
2049 unsigned long v;
2050
2051 v = apic_read(APIC_LVT0);
2052 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2053 }
2054
2055 static void unmask_lapic_irq (unsigned int irq)
2056 {
2057 unsigned long v;
2058
2059 v = apic_read(APIC_LVT0);
2060 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2061 }
2062
2063 static struct irq_chip lapic_chip __read_mostly = {
2064 .name = "local-APIC-edge",
2065 .mask = mask_lapic_irq,
2066 .unmask = unmask_lapic_irq,
2067 .eoi = ack_apic,
2068 };
2069
2070 static void setup_nmi (void)
2071 {
2072 /*
2073 * Dirty trick to enable the NMI watchdog ...
2074 * We put the 8259A master into AEOI mode and
2075 * unmask on all local APICs LVT0 as NMI.
2076 *
2077 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2078 * is from Maciej W. Rozycki - so we do not have to EOI from
2079 * the NMI handler or the timer interrupt.
2080 */
2081 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2082
2083 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2084
2085 apic_printk(APIC_VERBOSE, " done.\n");
2086 }
2087
2088 /*
2089 * This looks a bit hackish but it's about the only one way of sending
2090 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2091 * not support the ExtINT mode, unfortunately. We need to send these
2092 * cycles as some i82489DX-based boards have glue logic that keeps the
2093 * 8259A interrupt line asserted until INTA. --macro
2094 */
2095 static inline void unlock_ExtINT_logic(void)
2096 {
2097 int apic, pin, i;
2098 struct IO_APIC_route_entry entry0, entry1;
2099 unsigned char save_control, save_freq_select;
2100
2101 pin = find_isa_irq_pin(8, mp_INT);
2102 apic = find_isa_irq_apic(8, mp_INT);
2103 if (pin == -1)
2104 return;
2105
2106 entry0 = ioapic_read_entry(apic, pin);
2107 clear_IO_APIC_pin(apic, pin);
2108
2109 memset(&entry1, 0, sizeof(entry1));
2110
2111 entry1.dest_mode = 0; /* physical delivery */
2112 entry1.mask = 0; /* unmask IRQ now */
2113 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2114 entry1.delivery_mode = dest_ExtINT;
2115 entry1.polarity = entry0.polarity;
2116 entry1.trigger = 0;
2117 entry1.vector = 0;
2118
2119 ioapic_write_entry(apic, pin, entry1);
2120
2121 save_control = CMOS_READ(RTC_CONTROL);
2122 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2123 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2124 RTC_FREQ_SELECT);
2125 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2126
2127 i = 100;
2128 while (i-- > 0) {
2129 mdelay(10);
2130 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2131 i -= 10;
2132 }
2133
2134 CMOS_WRITE(save_control, RTC_CONTROL);
2135 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2136 clear_IO_APIC_pin(apic, pin);
2137
2138 ioapic_write_entry(apic, pin, entry0);
2139 }
2140
2141 int timer_uses_ioapic_pin_0;
2142
2143 /*
2144 * This code may look a bit paranoid, but it's supposed to cooperate with
2145 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2146 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2147 * fanatically on his truly buggy board.
2148 */
2149 static inline void check_timer(void)
2150 {
2151 int apic1, pin1, apic2, pin2;
2152 int vector;
2153
2154 /*
2155 * get/set the timer IRQ vector:
2156 */
2157 disable_8259A_irq(0);
2158 vector = assign_irq_vector(0);
2159 set_intr_gate(vector, interrupt[0]);
2160
2161 /*
2162 * Subtle, code in do_timer_interrupt() expects an AEOI
2163 * mode for the 8259A whenever interrupts are routed
2164 * through I/O APICs. Also IRQ0 has to be enabled in
2165 * the 8259A which implies the virtual wire has to be
2166 * disabled in the local APIC.
2167 */
2168 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2169 init_8259A(1);
2170 timer_ack = 1;
2171 if (timer_over_8254 > 0)
2172 enable_8259A_irq(0);
2173
2174 pin1 = find_isa_irq_pin(0, mp_INT);
2175 apic1 = find_isa_irq_apic(0, mp_INT);
2176 pin2 = ioapic_i8259.pin;
2177 apic2 = ioapic_i8259.apic;
2178
2179 if (pin1 == 0)
2180 timer_uses_ioapic_pin_0 = 1;
2181
2182 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2183 vector, apic1, pin1, apic2, pin2);
2184
2185 if (pin1 != -1) {
2186 /*
2187 * Ok, does IRQ0 through the IOAPIC work?
2188 */
2189 unmask_IO_APIC_irq(0);
2190 if (timer_irq_works()) {
2191 if (nmi_watchdog == NMI_IO_APIC) {
2192 disable_8259A_irq(0);
2193 setup_nmi();
2194 enable_8259A_irq(0);
2195 }
2196 if (disable_timer_pin_1 > 0)
2197 clear_IO_APIC_pin(0, pin1);
2198 return;
2199 }
2200 clear_IO_APIC_pin(apic1, pin1);
2201 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2202 "IO-APIC\n");
2203 }
2204
2205 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2206 if (pin2 != -1) {
2207 printk("\n..... (found pin %d) ...", pin2);
2208 /*
2209 * legacy devices should be connected to IO APIC #0
2210 */
2211 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2212 if (timer_irq_works()) {
2213 printk("works.\n");
2214 if (pin1 != -1)
2215 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2216 else
2217 add_pin_to_irq(0, apic2, pin2);
2218 if (nmi_watchdog == NMI_IO_APIC) {
2219 setup_nmi();
2220 }
2221 return;
2222 }
2223 /*
2224 * Cleanup, just in case ...
2225 */
2226 clear_IO_APIC_pin(apic2, pin2);
2227 }
2228 printk(" failed.\n");
2229
2230 if (nmi_watchdog == NMI_IO_APIC) {
2231 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2232 nmi_watchdog = 0;
2233 }
2234
2235 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2236
2237 disable_8259A_irq(0);
2238 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2239 "fasteio");
2240 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2241 enable_8259A_irq(0);
2242
2243 if (timer_irq_works()) {
2244 printk(" works.\n");
2245 return;
2246 }
2247 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2248 printk(" failed.\n");
2249
2250 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2251
2252 timer_ack = 0;
2253 init_8259A(0);
2254 make_8259A_irq(0);
2255 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2256
2257 unlock_ExtINT_logic();
2258
2259 if (timer_irq_works()) {
2260 printk(" works.\n");
2261 return;
2262 }
2263 printk(" failed :(.\n");
2264 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2265 "report. Then try booting with the 'noapic' option");
2266 }
2267
2268 /*
2269 *
2270 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2271 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2272 * Linux doesn't really care, as it's not actually used
2273 * for any interrupt handling anyway.
2274 */
2275 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2276
2277 void __init setup_IO_APIC(void)
2278 {
2279 enable_IO_APIC();
2280
2281 if (acpi_ioapic)
2282 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2283 else
2284 io_apic_irqs = ~PIC_IRQS;
2285
2286 printk("ENABLING IO-APIC IRQs\n");
2287
2288 /*
2289 * Set up IO-APIC IRQ routing.
2290 */
2291 if (!acpi_ioapic)
2292 setup_ioapic_ids_from_mpc();
2293 sync_Arb_IDs();
2294 setup_IO_APIC_irqs();
2295 init_IO_APIC_traps();
2296 check_timer();
2297 if (!acpi_ioapic)
2298 print_IO_APIC();
2299 }
2300
2301 static int __init setup_disable_8254_timer(char *s)
2302 {
2303 timer_over_8254 = -1;
2304 return 1;
2305 }
2306 static int __init setup_enable_8254_timer(char *s)
2307 {
2308 timer_over_8254 = 2;
2309 return 1;
2310 }
2311
2312 __setup("disable_8254_timer", setup_disable_8254_timer);
2313 __setup("enable_8254_timer", setup_enable_8254_timer);
2314
2315 /*
2316 * Called after all the initialization is done. If we didnt find any
2317 * APIC bugs then we can allow the modify fast path
2318 */
2319
2320 static int __init io_apic_bug_finalize(void)
2321 {
2322 if(sis_apic_bug == -1)
2323 sis_apic_bug = 0;
2324 return 0;
2325 }
2326
2327 late_initcall(io_apic_bug_finalize);
2328
2329 struct sysfs_ioapic_data {
2330 struct sys_device dev;
2331 struct IO_APIC_route_entry entry[0];
2332 };
2333 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2334
2335 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2336 {
2337 struct IO_APIC_route_entry *entry;
2338 struct sysfs_ioapic_data *data;
2339 int i;
2340
2341 data = container_of(dev, struct sysfs_ioapic_data, dev);
2342 entry = data->entry;
2343 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2344 entry[i] = ioapic_read_entry(dev->id, i);
2345
2346 return 0;
2347 }
2348
2349 static int ioapic_resume(struct sys_device *dev)
2350 {
2351 struct IO_APIC_route_entry *entry;
2352 struct sysfs_ioapic_data *data;
2353 unsigned long flags;
2354 union IO_APIC_reg_00 reg_00;
2355 int i;
2356
2357 data = container_of(dev, struct sysfs_ioapic_data, dev);
2358 entry = data->entry;
2359
2360 spin_lock_irqsave(&ioapic_lock, flags);
2361 reg_00.raw = io_apic_read(dev->id, 0);
2362 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2363 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2364 io_apic_write(dev->id, 0, reg_00.raw);
2365 }
2366 spin_unlock_irqrestore(&ioapic_lock, flags);
2367 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2368 ioapic_write_entry(dev->id, i, entry[i]);
2369
2370 return 0;
2371 }
2372
2373 static struct sysdev_class ioapic_sysdev_class = {
2374 set_kset_name("ioapic"),
2375 .suspend = ioapic_suspend,
2376 .resume = ioapic_resume,
2377 };
2378
2379 static int __init ioapic_init_sysfs(void)
2380 {
2381 struct sys_device * dev;
2382 int i, size, error = 0;
2383
2384 error = sysdev_class_register(&ioapic_sysdev_class);
2385 if (error)
2386 return error;
2387
2388 for (i = 0; i < nr_ioapics; i++ ) {
2389 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2390 * sizeof(struct IO_APIC_route_entry);
2391 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2392 if (!mp_ioapic_data[i]) {
2393 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2394 continue;
2395 }
2396 memset(mp_ioapic_data[i], 0, size);
2397 dev = &mp_ioapic_data[i]->dev;
2398 dev->id = i;
2399 dev->cls = &ioapic_sysdev_class;
2400 error = sysdev_register(dev);
2401 if (error) {
2402 kfree(mp_ioapic_data[i]);
2403 mp_ioapic_data[i] = NULL;
2404 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2405 continue;
2406 }
2407 }
2408
2409 return 0;
2410 }
2411
2412 device_initcall(ioapic_init_sysfs);
2413
2414 /*
2415 * Dynamic irq allocate and deallocation
2416 */
2417 int create_irq(void)
2418 {
2419 /* Allocate an unused irq */
2420 int irq, new, vector;
2421 unsigned long flags;
2422
2423 irq = -ENOSPC;
2424 spin_lock_irqsave(&vector_lock, flags);
2425 for (new = (NR_IRQS - 1); new >= 0; new--) {
2426 if (platform_legacy_irq(new))
2427 continue;
2428 if (irq_vector[new] != 0)
2429 continue;
2430 vector = __assign_irq_vector(new);
2431 if (likely(vector > 0))
2432 irq = new;
2433 break;
2434 }
2435 spin_unlock_irqrestore(&vector_lock, flags);
2436
2437 if (irq >= 0) {
2438 set_intr_gate(vector, interrupt[irq]);
2439 dynamic_irq_init(irq);
2440 }
2441 return irq;
2442 }
2443
2444 void destroy_irq(unsigned int irq)
2445 {
2446 unsigned long flags;
2447
2448 dynamic_irq_cleanup(irq);
2449
2450 spin_lock_irqsave(&vector_lock, flags);
2451 irq_vector[irq] = 0;
2452 spin_unlock_irqrestore(&vector_lock, flags);
2453 }
2454
2455 /*
2456 * MSI mesage composition
2457 */
2458 #ifdef CONFIG_PCI_MSI
2459 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2460 {
2461 int vector;
2462 unsigned dest;
2463
2464 vector = assign_irq_vector(irq);
2465 if (vector >= 0) {
2466 dest = cpu_mask_to_apicid(TARGET_CPUS);
2467
2468 msg->address_hi = MSI_ADDR_BASE_HI;
2469 msg->address_lo =
2470 MSI_ADDR_BASE_LO |
2471 ((INT_DEST_MODE == 0) ?
2472 MSI_ADDR_DEST_MODE_PHYSICAL:
2473 MSI_ADDR_DEST_MODE_LOGICAL) |
2474 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2475 MSI_ADDR_REDIRECTION_CPU:
2476 MSI_ADDR_REDIRECTION_LOWPRI) |
2477 MSI_ADDR_DEST_ID(dest);
2478
2479 msg->data =
2480 MSI_DATA_TRIGGER_EDGE |
2481 MSI_DATA_LEVEL_ASSERT |
2482 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2483 MSI_DATA_DELIVERY_FIXED:
2484 MSI_DATA_DELIVERY_LOWPRI) |
2485 MSI_DATA_VECTOR(vector);
2486 }
2487 return vector;
2488 }
2489
2490 #ifdef CONFIG_SMP
2491 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2492 {
2493 struct msi_msg msg;
2494 unsigned int dest;
2495 cpumask_t tmp;
2496 int vector;
2497
2498 cpus_and(tmp, mask, cpu_online_map);
2499 if (cpus_empty(tmp))
2500 tmp = TARGET_CPUS;
2501
2502 vector = assign_irq_vector(irq);
2503 if (vector < 0)
2504 return;
2505
2506 dest = cpu_mask_to_apicid(mask);
2507
2508 read_msi_msg(irq, &msg);
2509
2510 msg.data &= ~MSI_DATA_VECTOR_MASK;
2511 msg.data |= MSI_DATA_VECTOR(vector);
2512 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2513 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2514
2515 write_msi_msg(irq, &msg);
2516 set_native_irq_info(irq, mask);
2517 }
2518 #endif /* CONFIG_SMP */
2519
2520 /*
2521 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2522 * which implement the MSI or MSI-X Capability Structure.
2523 */
2524 static struct irq_chip msi_chip = {
2525 .name = "PCI-MSI",
2526 .unmask = unmask_msi_irq,
2527 .mask = mask_msi_irq,
2528 .ack = ack_ioapic_irq,
2529 #ifdef CONFIG_SMP
2530 .set_affinity = set_msi_irq_affinity,
2531 #endif
2532 .retrigger = ioapic_retrigger_irq,
2533 };
2534
2535 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
2536 {
2537 struct msi_msg msg;
2538 int ret;
2539 ret = msi_compose_msg(dev, irq, &msg);
2540 if (ret < 0)
2541 return ret;
2542
2543 write_msi_msg(irq, &msg);
2544
2545 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2546 "edge");
2547
2548 return 0;
2549 }
2550
2551 void arch_teardown_msi_irq(unsigned int irq)
2552 {
2553 return;
2554 }
2555
2556 #endif /* CONFIG_PCI_MSI */
2557
2558 /*
2559 * Hypertransport interrupt support
2560 */
2561 #ifdef CONFIG_HT_IRQ
2562
2563 #ifdef CONFIG_SMP
2564
2565 static void target_ht_irq(unsigned int irq, unsigned int dest)
2566 {
2567 u32 low, high;
2568 low = read_ht_irq_low(irq);
2569 high = read_ht_irq_high(irq);
2570
2571 low &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2572 high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2573
2574 low |= HT_IRQ_LOW_DEST_ID(dest);
2575 high |= HT_IRQ_HIGH_DEST_ID(dest);
2576
2577 write_ht_irq_low(irq, low);
2578 write_ht_irq_high(irq, high);
2579 }
2580
2581 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2582 {
2583 unsigned int dest;
2584 cpumask_t tmp;
2585
2586 cpus_and(tmp, mask, cpu_online_map);
2587 if (cpus_empty(tmp))
2588 tmp = TARGET_CPUS;
2589
2590 cpus_and(mask, tmp, CPU_MASK_ALL);
2591
2592 dest = cpu_mask_to_apicid(mask);
2593
2594 target_ht_irq(irq, dest);
2595 set_native_irq_info(irq, mask);
2596 }
2597 #endif
2598
2599 static struct irq_chip ht_irq_chip = {
2600 .name = "PCI-HT",
2601 .mask = mask_ht_irq,
2602 .unmask = unmask_ht_irq,
2603 .ack = ack_ioapic_irq,
2604 #ifdef CONFIG_SMP
2605 .set_affinity = set_ht_irq_affinity,
2606 #endif
2607 .retrigger = ioapic_retrigger_irq,
2608 };
2609
2610 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2611 {
2612 int vector;
2613
2614 vector = assign_irq_vector(irq);
2615 if (vector >= 0) {
2616 u32 low, high;
2617 unsigned dest;
2618 cpumask_t tmp;
2619
2620 cpus_clear(tmp);
2621 cpu_set(vector >> 8, tmp);
2622 dest = cpu_mask_to_apicid(tmp);
2623
2624 high = HT_IRQ_HIGH_DEST_ID(dest);
2625
2626 low = HT_IRQ_LOW_BASE |
2627 HT_IRQ_LOW_DEST_ID(dest) |
2628 HT_IRQ_LOW_VECTOR(vector) |
2629 ((INT_DEST_MODE == 0) ?
2630 HT_IRQ_LOW_DM_PHYSICAL :
2631 HT_IRQ_LOW_DM_LOGICAL) |
2632 HT_IRQ_LOW_RQEOI_EDGE |
2633 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2634 HT_IRQ_LOW_MT_FIXED :
2635 HT_IRQ_LOW_MT_ARBITRATED) |
2636 HT_IRQ_LOW_IRQ_MASKED;
2637
2638 write_ht_irq_low(irq, low);
2639 write_ht_irq_high(irq, high);
2640
2641 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2642 handle_edge_irq, "edge");
2643 }
2644 return vector;
2645 }
2646 #endif /* CONFIG_HT_IRQ */
2647
2648 /* --------------------------------------------------------------------------
2649 ACPI-based IOAPIC Configuration
2650 -------------------------------------------------------------------------- */
2651
2652 #ifdef CONFIG_ACPI
2653
2654 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2655 {
2656 union IO_APIC_reg_00 reg_00;
2657 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2658 physid_mask_t tmp;
2659 unsigned long flags;
2660 int i = 0;
2661
2662 /*
2663 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2664 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2665 * supports up to 16 on one shared APIC bus.
2666 *
2667 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2668 * advantage of new APIC bus architecture.
2669 */
2670
2671 if (physids_empty(apic_id_map))
2672 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2673
2674 spin_lock_irqsave(&ioapic_lock, flags);
2675 reg_00.raw = io_apic_read(ioapic, 0);
2676 spin_unlock_irqrestore(&ioapic_lock, flags);
2677
2678 if (apic_id >= get_physical_broadcast()) {
2679 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2680 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2681 apic_id = reg_00.bits.ID;
2682 }
2683
2684 /*
2685 * Every APIC in a system must have a unique ID or we get lots of nice
2686 * 'stuck on smp_invalidate_needed IPI wait' messages.
2687 */
2688 if (check_apicid_used(apic_id_map, apic_id)) {
2689
2690 for (i = 0; i < get_physical_broadcast(); i++) {
2691 if (!check_apicid_used(apic_id_map, i))
2692 break;
2693 }
2694
2695 if (i == get_physical_broadcast())
2696 panic("Max apic_id exceeded!\n");
2697
2698 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2699 "trying %d\n", ioapic, apic_id, i);
2700
2701 apic_id = i;
2702 }
2703
2704 tmp = apicid_to_cpu_present(apic_id);
2705 physids_or(apic_id_map, apic_id_map, tmp);
2706
2707 if (reg_00.bits.ID != apic_id) {
2708 reg_00.bits.ID = apic_id;
2709
2710 spin_lock_irqsave(&ioapic_lock, flags);
2711 io_apic_write(ioapic, 0, reg_00.raw);
2712 reg_00.raw = io_apic_read(ioapic, 0);
2713 spin_unlock_irqrestore(&ioapic_lock, flags);
2714
2715 /* Sanity check */
2716 if (reg_00.bits.ID != apic_id) {
2717 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2718 return -1;
2719 }
2720 }
2721
2722 apic_printk(APIC_VERBOSE, KERN_INFO
2723 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2724
2725 return apic_id;
2726 }
2727
2728
2729 int __init io_apic_get_version (int ioapic)
2730 {
2731 union IO_APIC_reg_01 reg_01;
2732 unsigned long flags;
2733
2734 spin_lock_irqsave(&ioapic_lock, flags);
2735 reg_01.raw = io_apic_read(ioapic, 1);
2736 spin_unlock_irqrestore(&ioapic_lock, flags);
2737
2738 return reg_01.bits.version;
2739 }
2740
2741
2742 int __init io_apic_get_redir_entries (int ioapic)
2743 {
2744 union IO_APIC_reg_01 reg_01;
2745 unsigned long flags;
2746
2747 spin_lock_irqsave(&ioapic_lock, flags);
2748 reg_01.raw = io_apic_read(ioapic, 1);
2749 spin_unlock_irqrestore(&ioapic_lock, flags);
2750
2751 return reg_01.bits.entries;
2752 }
2753
2754
2755 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2756 {
2757 struct IO_APIC_route_entry entry;
2758 unsigned long flags;
2759
2760 if (!IO_APIC_IRQ(irq)) {
2761 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2762 ioapic);
2763 return -EINVAL;
2764 }
2765
2766 /*
2767 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2768 * Note that we mask (disable) IRQs now -- these get enabled when the
2769 * corresponding device driver registers for this IRQ.
2770 */
2771
2772 memset(&entry,0,sizeof(entry));
2773
2774 entry.delivery_mode = INT_DELIVERY_MODE;
2775 entry.dest_mode = INT_DEST_MODE;
2776 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2777 entry.trigger = edge_level;
2778 entry.polarity = active_high_low;
2779 entry.mask = 1;
2780
2781 /*
2782 * IRQs < 16 are already in the irq_2_pin[] map
2783 */
2784 if (irq >= 16)
2785 add_pin_to_irq(irq, ioapic, pin);
2786
2787 entry.vector = assign_irq_vector(irq);
2788
2789 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2790 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2791 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2792 edge_level, active_high_low);
2793
2794 ioapic_register_intr(irq, entry.vector, edge_level);
2795
2796 if (!ioapic && (irq < 16))
2797 disable_8259A_irq(irq);
2798
2799 ioapic_write_entry(ioapic, pin, entry);
2800 spin_lock_irqsave(&ioapic_lock, flags);
2801 set_native_irq_info(irq, TARGET_CPUS);
2802 spin_unlock_irqrestore(&ioapic_lock, flags);
2803
2804 return 0;
2805 }
2806
2807 #endif /* CONFIG_ACPI */
2808
2809 static int __init parse_disable_timer_pin_1(char *arg)
2810 {
2811 disable_timer_pin_1 = 1;
2812 return 0;
2813 }
2814 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2815
2816 static int __init parse_enable_timer_pin_1(char *arg)
2817 {
2818 disable_timer_pin_1 = -1;
2819 return 0;
2820 }
2821 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2822
2823 static int __init parse_noapic(char *arg)
2824 {
2825 /* disable IO-APIC */
2826 disable_ioapic_setup();
2827 return 0;
2828 }
2829 early_param("noapic", parse_noapic);
kernel source for telekom puls (alcatel/mediatek)