arch/frv/kernel/cmode.S

   1 /* cmode.S: clock mode management
   2  *
   3  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Woodhouse (dwmw2@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/sys.h>
  14 #include <linux/config.h>
  15 #include <linux/linkage.h>
  16 #include <asm/setup.h>
  17 #include <asm/segment.h>
  18 #include <asm/ptrace.h>
  19 #include <asm/errno.h>
  20 #include <asm/cache.h>
  21 #include <asm/spr-regs.h>
  22
  23 #define __addr_MASK     0xfeff9820      /* interrupt controller mask */
  24
  25 #define __addr_SDRAMC   0xfe000400      /* SDRAM controller regs */
  26 #define SDRAMC_DSTS     0x28            /* SDRAM status */
  27 #define SDRAMC_DSTS_SSI 0x00000001      /* indicates that the SDRAM is in self-refresh mode */
  28 #define SDRAMC_DRCN     0x30            /* SDRAM refresh control */
  29 #define SDRAMC_DRCN_SR  0x00000001      /* transition SDRAM into self-refresh mode */
  30 #define __addr_CLKC     0xfeff9a00
  31 #define CLKC_SWCMODE    0x00000008
  32 #define __addr_LEDS     0xe1200004
  33
  34 .macro li v r
  35         sethi.p         %hi(\v),\r
  36         setlo           %lo(\v),\r
  37 .endm
  38
  39         .text
  40         .balign         4
  41
  42
  43 ###############################################################################
  44 #
  45 # Change CMODE
  46 # - void frv_change_cmode(int cmode)
  47 #
  48 ###############################################################################
  49         .globl          frv_change_cmode
  50         .type           frv_change_cmode,@function
  51
  52 .macro  LEDS v
  53 #ifdef DEBUG_CMODE
  54         setlos  #~\v,gr10
  55         sti     gr10,@(gr11,#0)
  56         membar
  57 #endif
  58 .endm
  59
  60 frv_change_cmode:
  61         movsg           lr,gr9
  62 #ifdef DEBUG_CMODE
  63         li              __addr_LEDS,gr11
  64 #endif
  65         dcef            @(gr0,gr0),#1
  66
  67         # Shift argument left by 24 bits to fit in SWCMODE register later.
  68         slli            gr8,#24,gr8
  69
  70         # (1) Set '0' in the PSR.ET bit, and prohibit interrupts.
  71         movsg           psr,gr14
  72         andi            gr14,#~PSR_ET,gr3
  73         movgs           gr3,psr
  74
  75 #if 0 // Fujitsu recommend to skip this and will update docs.
  76         # (2) Set '0' to all bits of the MASK register of the interrupt
  77         #     controller, and mask interrupts.
  78         li              __addr_MASK,gr12
  79         ldi             @(gr12,#0),gr13
  80         li              0xffff0000,gr4
  81         sti             gr4,@(gr12,#0)
  82 #endif
  83
  84         # (3) Stop the transfer function of DMAC. Stop all the bus masters
  85         #     to access SDRAM and the internal resources.
  86
  87         # (already done by caller)
  88
  89         # (4) Preload a series of following instructions to the instruction
  90         #     cache.
  91         li              #__cmode_icache_lock_start,gr3
  92         li              #__cmode_icache_lock_end,gr4
  93
  94 1:      icpl            gr3,gr0,#1
  95         addi            gr3,#L1_CACHE_BYTES,gr3
  96         cmp             gr4,gr3,icc0
  97         bhi             icc0,#0,1b
  98
  99         # Set up addresses in regs for later steps.
 100         setlos          SDRAMC_DRCN_SR,gr3
 101         li              __addr_SDRAMC,gr4
 102         li              __addr_CLKC,gr5
 103         ldi             @(gr5,#0),gr6
 104         li              #0x80000000,gr7
 105         or              gr6,gr7,gr6
 106
 107         bra             __cmode_icache_lock_start
 108
 109         .balign L1_CACHE_BYTES
 110 __cmode_icache_lock_start:
 111
 112         # (5) Flush the content of all caches by the DCEF instruction.
 113         dcef            @(gr0,gr0),#1
 114
 115         # (6) Execute loading the dummy for SDRAM.
 116         ldi             @(gr9,#0),gr0
 117
 118         # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
 119         #     self-refresh mode. Execute the dummy load to all memory
 120         #     devices set to cacheable on the external bus side in parallel
 121         #     with this.
 122         sti             gr3,@(gr4,#SDRAMC_DRCN)
 123
 124         # (8) Execute memory barrier instruction (MEMBAR).
 125         membar
 126
 127         # (9) Read the DSTS register repeatedly until '1' stands in the
 128         #     DSTS.SSI field.
 129 1:      ldi             @(gr4,#SDRAMC_DSTS),gr3
 130         andicc          gr3,#SDRAMC_DSTS_SSI,gr3,icc0
 131         beq             icc0,#0,1b
 132
 133         # (10) Execute memory barrier instruction (MEMBAR).
 134         membar
 135
 136 #if 1
 137         # (11) Set the value of CMODE that you want to change to
 138         #      SWCMODE.SWCM[3:0].
 139         sti             gr8,@(gr5,#CLKC_SWCMODE)
 140
 141         # (12) Set '1' to the CLKC.SWEN bit. In that case, do not change
 142         #      fields other than SWEN of the CLKC register.
 143         sti             gr6,@(gr5,#0)
 144 #endif
 145         # (13) Execute the instruction just after the memory barrier
 146         # instruction that executes the self-loop 256 times. (Meanwhile,
 147         # the CMODE switch is done.)
 148         membar
 149         setlos          #256,gr7
 150 2:      subicc          gr7,#1,gr7,icc0
 151         bne             icc0,#2,2b
 152
 153         LEDS    0x36
 154
 155         # (14) Release the self-refresh of SDRAM.
 156         sti             gr0,@(gr4,#SDRAMC_DRCN)
 157
 158         # Wait for it...
 159 3:      ldi             @(gr4,#SDRAMC_DSTS),gr3
 160         andicc          gr3,#SDRAMC_DSTS_SSI,gr3,icc0
 161         bne             icc0,#2,3b
 162
 163 #if 0
 164         li              0x0100000,gr10
 165 4:      subicc          gr10,#1,gr10,icc0
 166
 167         bne             icc0,#0,4b
 168 #endif
 169
 170 __cmode_icache_lock_end:
 171
 172         li              #__cmode_icache_lock_start,gr3
 173         li              #__cmode_icache_lock_end,gr4
 174
 175 4:      icul            gr3
 176         addi            gr3,#L1_CACHE_BYTES,gr3
 177         cmp             gr4,gr3,icc0
 178         bhi             icc0,#0,4b
 179
 180 #if 0 // Fujitsu recommend to skip this and will update docs.
 181         # (15) Release the interrupt mask setting of the MASK register of
 182         # the interrupt controller if necessary.
 183         sti             gr13,@(gr12,#0)
 184 #endif
 185         # (16) Set  1' in the PSR.ET bit, and permit interrupt.
 186         movgs           gr14,psr
 187
 188         bralr
 189
 190         .size           frv_change_cmode, .-frv_change_cmode