arch/cris/arch-v32/kernel/time.c

   1 /*
   2  *  linux/arch/cris/arch-v32/kernel/time.c
   3  *
   4  *  Copyright (C) 2003-2007 Axis Communications AB
   5  *
   6  */
   7
   8 #include <linux/timex.h>
   9 #include <linux/time.h>
  10 #include <linux/jiffies.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/swap.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15 #include <linux/threads.h>
  16 #include <linux/cpufreq.h>
  17 #include <asm/types.h>
  18 #include <asm/signal.h>
  19 #include <asm/io.h>
  20 #include <asm/delay.h>
  21 #include <asm/rtc.h>
  22 #include <asm/irq.h>
  23 #include <asm/irq_regs.h>
  24
  25 #include <hwregs/reg_map.h>
  26 #include <hwregs/reg_rdwr.h>
  27 #include <hwregs/timer_defs.h>
  28 #include <hwregs/intr_vect_defs.h>
  29 #ifdef CONFIG_CRIS_MACH_ARTPEC3
  30 #include <hwregs/clkgen_defs.h>
  31 #endif
  32
  33 /* Watchdog defines */
  34 #define ETRAX_WD_KEY_MASK       0x7F /* key is 7 bit */
  35 #define ETRAX_WD_HZ             763 /* watchdog counts at 763 Hz */
  36 /* Number of 763 counts before watchdog bites */
  37 #define ETRAX_WD_CNT            ((2*ETRAX_WD_HZ)/HZ + 1)
  38
  39 unsigned long timer_regs[NR_CPUS] =
  40 {
  41         regi_timer0,
  42 #ifdef CONFIG_SMP
  43         regi_timer2
  44 #endif
  45 };
  46
  47 extern int set_rtc_mmss(unsigned long nowtime);
  48 extern int have_rtc;
  49
  50 #ifdef CONFIG_CPU_FREQ
  51 static int
  52 cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
  53                         void *data);
  54
  55 static struct notifier_block cris_time_freq_notifier_block = {
  56         .notifier_call = cris_time_freq_notifier,
  57 };
  58 #endif
  59
  60 unsigned long get_ns_in_jiffie(void)
  61 {
  62         reg_timer_r_tmr0_data data;
  63         unsigned long ns;
  64
  65         data = REG_RD(timer, regi_timer0, r_tmr0_data);
  66         ns = (TIMER0_DIV - data) * 10;
  67         return ns;
  68 }
  69
  70 unsigned long do_slow_gettimeoffset(void)
  71 {
  72         unsigned long count;
  73         unsigned long usec_count = 0;
  74
  75         /* For the first call after boot */
  76         static unsigned long count_p = TIMER0_DIV;
  77         static unsigned long jiffies_p = 0;
  78
  79         /* Cache volatile jiffies temporarily; we have IRQs turned off. */
  80         unsigned long jiffies_t;
  81
  82         /* The timer interrupt comes from Etrax timer 0. In order to get
  83          * better precision, we check the current value. It might have
  84          * underflowed already though. */
  85         count = REG_RD(timer, regi_timer0, r_tmr0_data);
  86         jiffies_t = jiffies;
  87
  88         /* Avoiding timer inconsistencies (they are rare, but they happen)
  89          * There is one problem that must be avoided here:
  90          *      1. the timer counter underflows
  91          */
  92         if( jiffies_t == jiffies_p ) {
  93                 if( count > count_p ) {
  94                         /* Timer wrapped, use new count and prescale.
  95                          * Increase the time corresponding to one jiffy.
  96                          */
  97                         usec_count = 1000000/HZ;
  98                 }
  99         } else
 100                 jiffies_p = jiffies_t;
 101         count_p = count;
 102         /* Convert timer value to usec */
 103         /* 100 MHz timer, divide by 100 to get usec */
 104         usec_count +=  (TIMER0_DIV - count) / 100;
 105         return usec_count;
 106 }
 107
 108 /* From timer MDS describing the hardware watchdog:
 109  * 4.3.1 Watchdog Operation
 110  * The watchdog timer is an 8-bit timer with a configurable start value.
 111  * Once started the watchdog counts downwards with a frequency of 763 Hz
 112  * (100/131072 MHz). When the watchdog counts down to 1, it generates an
 113  * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
 114  * chip.
 115  */
 116 /* This gives us 1.3 ms to do something useful when the NMI comes */
 117
 118 /* Right now, starting the watchdog is the same as resetting it */
 119 #define start_watchdog reset_watchdog
 120
 121 #if defined(CONFIG_ETRAX_WATCHDOG)
 122 static short int watchdog_key = 42;  /* arbitrary 7 bit number */
 123 #endif
 124
 125 /* Number of pages to consider "out of memory". It is normal that the memory
 126  * is used though, so set this really low. */
 127 #define WATCHDOG_MIN_FREE_PAGES 8
 128
 129 void
 130 reset_watchdog(void)
 131 {
 132 #if defined(CONFIG_ETRAX_WATCHDOG)
 133         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 134
 135         /* Only keep watchdog happy as long as we have memory left! */
 136         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 137                 /* Reset the watchdog with the inverse of the old key */
 138                 /* Invert key, which is 7 bits */
 139                 watchdog_key ^= ETRAX_WD_KEY_MASK;
 140                 wd_ctrl.cnt = ETRAX_WD_CNT;
 141                 wd_ctrl.cmd = regk_timer_start;
 142                 wd_ctrl.key = watchdog_key;
 143                 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 144         }
 145 #endif
 146 }
 147
 148 /* stop the watchdog - we still need the correct key */
 149
 150 void
 151 stop_watchdog(void)
 152 {
 153 #if defined(CONFIG_ETRAX_WATCHDOG)
 154         reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 155         watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
 156         wd_ctrl.cnt = ETRAX_WD_CNT;
 157         wd_ctrl.cmd = regk_timer_stop;
 158         wd_ctrl.key = watchdog_key;
 159         REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 160 #endif
 161 }
 162
 163 extern void show_registers(struct pt_regs *regs);
 164
 165 void
 166 handle_watchdog_bite(struct pt_regs* regs)
 167 {
 168 #if defined(CONFIG_ETRAX_WATCHDOG)
 169         extern int cause_of_death;
 170
 171         oops_in_progress = 1;
 172         printk(KERN_WARNING "Watchdog bite\n");
 173
 174         /* Check if forced restart or unexpected watchdog */
 175         if (cause_of_death == 0xbedead) {
 176 #ifdef CONFIG_CRIS_MACH_ARTPEC3
 177                 /* There is a bug in Artpec-3 (voodoo TR 78) that requires
 178                  * us to go to lower frequency for the reset to be reliable
 179                  */
 180                 reg_clkgen_rw_clk_ctrl ctrl =
 181                         REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
 182                 ctrl.pll = 0;
 183                 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
 184 #endif
 185                 while(1);
 186         }
 187
 188         /* Unexpected watchdog, stop the watchdog and dump registers. */
 189         stop_watchdog();
 190         printk(KERN_WARNING "Oops: bitten by watchdog\n");
 191         show_registers(regs);
 192         oops_in_progress = 0;
 193 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
 194         reset_watchdog();
 195 #endif
 196         while(1) /* nothing */;
 197 #endif
 198 }
 199
 200 /*
 201  * timer_interrupt() needs to keep up the real-time clock,
 202  * as well as call the "do_timer()" routine every clocktick.
 203  */
 204 extern void cris_do_profile(struct pt_regs *regs);
 205
 206 static inline irqreturn_t
 207 timer_interrupt(int irq, void *dev_id)
 208 {
 209         struct pt_regs *regs = get_irq_regs();
 210         int cpu = smp_processor_id();
 211         reg_timer_r_masked_intr masked_intr;
 212         reg_timer_rw_ack_intr ack_intr = { 0 };
 213
 214         /* Check if the timer interrupt is for us (a tmr0 int) */
 215         masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
 216         if (!masked_intr.tmr0)
 217                 return IRQ_NONE;
 218
 219         /* Acknowledge the timer irq. */
 220         ack_intr.tmr0 = 1;
 221         REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
 222
 223         /* Reset watchdog otherwise it resets us! */
 224         reset_watchdog();
 225
 226         /* Update statistics. */
 227         update_process_times(user_mode(regs));
 228
 229         cris_do_profile(regs); /* Save profiling information */
 230
 231         /* The master CPU is responsible for the time keeping. */
 232         if (cpu != 0)
 233                 return IRQ_HANDLED;
 234
 235         /* Call the real timer interrupt handler */
 236         do_timer(1);
 237         return IRQ_HANDLED;
 238 }
 239
 240 /* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain.
 241  * It needs to be IRQF_DISABLED to make the jiffies update work properly.
 242  */
 243 static struct irqaction irq_timer = {
 244         .handler = timer_interrupt,
 245         .flags = IRQF_SHARED | IRQF_DISABLED,
 246         .name = "timer"
 247 };
 248
 249 void __init
 250 cris_timer_init(void)
 251 {
 252         int cpu = smp_processor_id();
 253         reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
 254         reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
 255         reg_timer_rw_intr_mask timer_intr_mask;
 256
 257         /* Setup the etrax timers.
 258          * Base frequency is 100MHz, divider 1000000 -> 100 HZ
 259          * We use timer0, so timer1 is free.
 260          * The trig timer is used by the fasttimer API if enabled.
 261          */
 262
 263         tmr0_ctrl.op = regk_timer_ld;
 264         tmr0_ctrl.freq = regk_timer_f100;
 265         REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
 266         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
 267         tmr0_ctrl.op = regk_timer_run;
 268         REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
 269
 270         /* Enable the timer irq. */
 271         timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
 272         timer_intr_mask.tmr0 = 1;
 273         REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
 274 }
 275
 276 void __init
 277 time_init(void)
 278 {
 279         reg_intr_vect_rw_mask intr_mask;
 280
 281         /* Probe for the RTC and read it if it exists.
 282          * Before the RTC can be probed the loops_per_usec variable needs
 283          * to be initialized to make usleep work. A better value for
 284          * loops_per_usec is calculated by the kernel later once the
 285          * clock has started.
 286          */
 287         loops_per_usec = 50;
 288
 289         if(RTC_INIT() < 0)
 290                 have_rtc = 0;
 291         else
 292                 have_rtc = 1;
 293
 294         /* Start CPU local timer. */
 295         cris_timer_init();
 296
 297         /* Enable the timer irq in global config. */
 298         intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
 299         intr_mask.timer0 = 1;
 300         REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
 301
 302         /* Now actually register the timer irq handler that calls
 303          * timer_interrupt(). */
 304         setup_irq(TIMER0_INTR_VECT, &irq_timer);
 305
 306         /* Enable watchdog if we should use one. */
 307
 308 #if defined(CONFIG_ETRAX_WATCHDOG)
 309         printk(KERN_INFO "Enabling watchdog...\n");
 310         start_watchdog();
 311
 312         /* If we use the hardware watchdog, we want to trap it as an NMI
 313          * and dump registers before it resets us.  For this to happen, we
 314          * must set the "m" NMI enable flag (which once set, is unset only
 315          * when an NMI is taken). */
 316         {
 317                 unsigned long flags;
 318                 local_save_flags(flags);
 319                 flags |= (1<<30); /* NMI M flag is at bit 30 */
 320                 local_irq_restore(flags);
 321         }
 322 #endif
 323
 324 #ifdef CONFIG_CPU_FREQ
 325         cpufreq_register_notifier(&cris_time_freq_notifier_block,
 326                 CPUFREQ_TRANSITION_NOTIFIER);
 327 #endif
 328 }
 329
 330 #ifdef CONFIG_CPU_FREQ
 331 static int
 332 cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
 333                         void *data)
 334 {
 335         struct cpufreq_freqs *freqs = data;
 336         if (val == CPUFREQ_POSTCHANGE) {
 337                 reg_timer_r_tmr0_data data;
 338                 reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
 339                 do {
 340                         data = REG_RD(timer, timer_regs[freqs->cpu],
 341                                 r_tmr0_data);
 342                 } while (data > 20);
 343                 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
 344         }
 345         return 0;
 346 }
 347 #endif