1 /* $Id: time.c,v 1.19 2005/04/29 05:40:09 starvik Exp $
3 * linux/arch/cris/arch-v32/kernel/time.c
5 * Copyright (C) 2003 Axis Communications AB
9 #include <linux/timex.h>
10 #include <linux/time.h>
11 #include <linux/jiffies.h>
12 #include <linux/interrupt.h>
13 #include <linux/swap.h>
14 #include <linux/sched.h>
15 #include <linux/init.h>
16 #include <linux/threads.h>
17 #include <asm/types.h>
18 #include <asm/signal.h>
20 #include <asm/delay.h>
24 #include <asm/arch/hwregs/reg_map.h>
25 #include <asm/arch/hwregs/reg_rdwr.h>
26 #include <asm/arch/hwregs/timer_defs.h>
27 #include <asm/arch/hwregs/intr_vect_defs.h>
29 /* Watchdog defines */
30 #define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
31 #define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
32 #define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) /* Number of 763 counts before watchdog bites */
34 unsigned long timer_regs
[NR_CPUS
] =
42 extern void update_xtime_from_cmos(void);
43 extern int set_rtc_mmss(unsigned long nowtime
);
44 extern int setup_irq(int, struct irqaction
*);
47 unsigned long get_ns_in_jiffie(void)
49 reg_timer_r_tmr0_data data
;
52 data
= REG_RD(timer
, regi_timer
, r_tmr0_data
);
53 ns
= (TIMER0_DIV
- data
) * 10;
57 unsigned long do_slow_gettimeoffset(void)
60 unsigned long usec_count
= 0;
62 static unsigned long count_p
= TIMER0_DIV
;/* for the first call after boot */
63 static unsigned long jiffies_p
= 0;
66 * cache volatile jiffies temporarily; we have IRQs turned off.
68 unsigned long jiffies_t
;
70 /* The timer interrupt comes from Etrax timer 0. In order to get
71 * better precision, we check the current value. It might have
72 * underflowed already though.
75 count
= REG_RD(timer
, regi_timer
, r_tmr0_data
);
79 * avoiding timer inconsistencies (they are rare, but they happen)...
80 * there are one problem that must be avoided here:
81 * 1. the timer counter underflows
83 if( jiffies_t
== jiffies_p
) {
84 if( count
> count_p
) {
85 /* Timer wrapped, use new count and prescale
86 * increase the time corresponding to one jiffie
88 usec_count
= 1000000/HZ
;
91 jiffies_p
= jiffies_t
;
93 /* Convert timer value to usec */
94 /* 100 MHz timer, divide by 100 to get usec */
95 usec_count
+= (TIMER0_DIV
- count
) / 100;
99 /* From timer MDS describing the hardware watchdog:
100 * 4.3.1 Watchdog Operation
101 * The watchdog timer is an 8-bit timer with a configurable start value.
102 * Once started the whatchdog counts downwards with a frequency of 763 Hz
103 * (100/131072 MHz). When the watchdog counts down to 1, it generates an
104 * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
107 /* This gives us 1.3 ms to do something useful when the NMI comes */
109 /* right now, starting the watchdog is the same as resetting it */
110 #define start_watchdog reset_watchdog
112 #if defined(CONFIG_ETRAX_WATCHDOG)
113 static short int watchdog_key
= 42; /* arbitrary 7 bit number */
116 /* number of pages to consider "out of memory". it is normal that the memory
117 * is used though, so put this really low.
120 #define WATCHDOG_MIN_FREE_PAGES 8
125 #if defined(CONFIG_ETRAX_WATCHDOG)
126 reg_timer_rw_wd_ctrl wd_ctrl
= { 0 };
128 /* only keep watchdog happy as long as we have memory left! */
129 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES
) {
130 /* reset the watchdog with the inverse of the old key */
131 watchdog_key
^= ETRAX_WD_KEY_MASK
; /* invert key, which is 7 bits */
132 wd_ctrl
.cnt
= ETRAX_WD_CNT
;
133 wd_ctrl
.cmd
= regk_timer_start
;
134 wd_ctrl
.key
= watchdog_key
;
135 REG_WR(timer
, regi_timer
, rw_wd_ctrl
, wd_ctrl
);
140 /* stop the watchdog - we still need the correct key */
145 #if defined(CONFIG_ETRAX_WATCHDOG)
146 reg_timer_rw_wd_ctrl wd_ctrl
= { 0 };
147 watchdog_key
^= ETRAX_WD_KEY_MASK
; /* invert key, which is 7 bits */
148 wd_ctrl
.cnt
= ETRAX_WD_CNT
;
149 wd_ctrl
.cmd
= regk_timer_stop
;
150 wd_ctrl
.key
= watchdog_key
;
151 REG_WR(timer
, regi_timer
, rw_wd_ctrl
, wd_ctrl
);
155 extern void show_registers(struct pt_regs
*regs
);
158 handle_watchdog_bite(struct pt_regs
* regs
)
160 #if defined(CONFIG_ETRAX_WATCHDOG)
161 extern int cause_of_death
;
163 raw_printk("Watchdog bite\n");
165 /* Check if forced restart or unexpected watchdog */
166 if (cause_of_death
== 0xbedead) {
170 /* Unexpected watchdog, stop the watchdog and dump registers*/
172 raw_printk("Oops: bitten by watchdog\n");
173 show_registers(regs
);
174 #ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
177 while(1) /* nothing */;
181 /* last time the cmos clock got updated */
182 static long last_rtc_update
= 0;
185 * timer_interrupt() needs to keep up the real-time clock,
186 * as well as call the "do_timer()" routine every clocktick
189 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
191 extern void cris_do_profile(struct pt_regs
*regs
);
193 static inline irqreturn_t
194 timer_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
196 int cpu
= smp_processor_id();
197 reg_timer_r_masked_intr masked_intr
;
198 reg_timer_rw_ack_intr ack_intr
= { 0 };
200 /* Check if the timer interrupt is for us (a tmr0 int) */
201 masked_intr
= REG_RD(timer
, timer_regs
[cpu
], r_masked_intr
);
202 if (!masked_intr
.tmr0
)
205 /* acknowledge the timer irq */
207 REG_WR(timer
, timer_regs
[cpu
], rw_ack_intr
, ack_intr
);
209 /* reset watchdog otherwise it resets us! */
212 /* Update statistics. */
213 update_process_times(user_mode(regs
));
215 cris_do_profile(regs
); /* Save profiling information */
217 /* The master CPU is responsible for the time keeping. */
221 /* call the real timer interrupt handler */
225 * If we have an externally synchronized Linux clock, then update
226 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
227 * called as close as possible to 500 ms before the new second starts.
229 * The division here is not time critical since it will run once in
232 if ((time_status
& STA_UNSYNC
) == 0 &&
233 xtime
.tv_sec
> last_rtc_update
+ 660 &&
234 (xtime
.tv_nsec
/ 1000) >= 500000 - (tick_nsec
/ 1000) / 2 &&
235 (xtime
.tv_nsec
/ 1000) <= 500000 + (tick_nsec
/ 1000) / 2) {
236 if (set_rtc_mmss(xtime
.tv_sec
) == 0)
237 last_rtc_update
= xtime
.tv_sec
;
239 last_rtc_update
= xtime
.tv_sec
- 600; /* do it again in 60 s */
244 /* timer is SA_SHIRQ so drivers can add stuff to the timer irq chain
245 * it needs to be SA_INTERRUPT to make the jiffies update work properly
248 static struct irqaction irq_timer
= { timer_interrupt
, SA_SHIRQ
| SA_INTERRUPT
,
249 CPU_MASK_NONE
, "timer", NULL
, NULL
};
252 cris_timer_init(void)
254 int cpu
= smp_processor_id();
255 reg_timer_rw_tmr0_ctrl tmr0_ctrl
= { 0 };
256 reg_timer_rw_tmr0_div tmr0_div
= TIMER0_DIV
;
257 reg_timer_rw_intr_mask timer_intr_mask
;
259 /* Setup the etrax timers
260 * Base frequency is 100MHz, divider 1000000 -> 100 HZ
261 * We use timer0, so timer1 is free.
262 * The trig timer is used by the fasttimer API if enabled.
265 tmr0_ctrl
.op
= regk_timer_ld
;
266 tmr0_ctrl
.freq
= regk_timer_f100
;
267 REG_WR(timer
, timer_regs
[cpu
], rw_tmr0_div
, tmr0_div
);
268 REG_WR(timer
, timer_regs
[cpu
], rw_tmr0_ctrl
, tmr0_ctrl
); /* Load */
269 tmr0_ctrl
.op
= regk_timer_run
;
270 REG_WR(timer
, timer_regs
[cpu
], rw_tmr0_ctrl
, tmr0_ctrl
); /* Start */
272 /* enable the timer irq */
273 timer_intr_mask
= REG_RD(timer
, timer_regs
[cpu
], rw_intr_mask
);
274 timer_intr_mask
.tmr0
= 1;
275 REG_WR(timer
, timer_regs
[cpu
], rw_intr_mask
, timer_intr_mask
);
281 reg_intr_vect_rw_mask intr_mask
;
283 /* probe for the RTC and read it if it exists
284 * Before the RTC can be probed the loops_per_usec variable needs
285 * to be initialized to make usleep work. A better value for
286 * loops_per_usec is calculated by the kernel later once the
292 /* no RTC, start at 1980 */
297 /* get the current time */
299 update_xtime_from_cmos();
303 * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
304 * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
306 set_normalized_timespec(&wall_to_monotonic
, -xtime
.tv_sec
, -xtime
.tv_nsec
);
308 /* Start CPU local timer */
311 /* enable the timer irq in global config */
312 intr_mask
= REG_RD(intr_vect
, regi_irq
, rw_mask
);
314 REG_WR(intr_vect
, regi_irq
, rw_mask
, intr_mask
);
316 /* now actually register the timer irq handler that calls timer_interrupt() */
318 setup_irq(TIMER_INTR_VECT
, &irq_timer
);
320 /* enable watchdog if we should use one */
322 #if defined(CONFIG_ETRAX_WATCHDOG)
323 printk("Enabling watchdog...\n");
326 /* If we use the hardware watchdog, we want to trap it as an NMI
327 and dump registers before it resets us. For this to happen, we
328 must set the "m" NMI enable flag (which once set, is unset only
329 when an NMI is taken).
331 The same goes for the external NMI, but that doesn't have any
332 driver or infrastructure support yet. */
335 local_save_flags(flags
);
336 flags
|= (1<<30); /* NMI M flag is at bit 30 */
337 local_irq_restore(flags
);