arch/blackfin/mach-common/cache.S

   1 /*
   2  * Blackfin cache control code
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/linkage.h>
  10 #include <asm/blackfin.h>
  11 #include <asm/cache.h>
  12 #include <asm/page.h>
  13
  14 .text
  15
  16 /* 05000443 - IFLUSH cannot be last instruction in hardware loop */
  17 #if ANOMALY_05000443
  18 # define BROK_FLUSH_INST "IFLUSH"
  19 #else
  20 # define BROK_FLUSH_INST "no anomaly! yeah!"
  21 #endif
  22
  23 /* Since all L1 caches work the same way, we use the same method for flushing
  24  * them.  Only the actual flush instruction differs.  We write this in asm as
  25  * GCC can be hard to coax into writing nice hardware loops.
  26  *
  27  * Also, we assume the following register setup:
  28  * R0 = start address
  29  * R1 = end address
  30  */
  31 .macro do_flush flushins:req label
  32
  33         R2 = -L1_CACHE_BYTES;
  34
  35         /* start = (start & -L1_CACHE_BYTES) */
  36         R0 = R0 & R2;
  37
  38         /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
  39         R1 += -1;
  40         R1 = R1 & R2;
  41         R1 += L1_CACHE_BYTES;
  42
  43         /* count = (end - start) >> L1_CACHE_SHIFT */
  44         R2 = R1 - R0;
  45         R2 >>= L1_CACHE_SHIFT;
  46         P1 = R2;
  47
  48 .ifnb \label
  49 \label :
  50 .endif
  51         P0 = R0;
  52
  53         LSETUP (1f, 2f) LC1 = P1;
  54 1:
  55 .ifeqs "\flushins", BROK_FLUSH_INST
  56         \flushins [P0++];
  57 2:      nop;
  58 .else
  59 2:      \flushins [P0++];
  60 .endif
  61
  62         RTS;
  63 .endm
  64
  65 /* Invalidate all instruction cache lines assocoiated with this memory area */
  66 ENTRY(_blackfin_icache_flush_range)
  67 /*
  68  * Walkaround to avoid loading wrong instruction after invalidating icache
  69  * and following sequence is met.
  70  *
  71  * 1) One instruction address is cached in the instruction cache.
  72  * 2) This instruction in SDRAM is changed.
  73  * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
  74  * 4) This instruction is executed again, but the old one is loaded.
  75  */
  76         P0 = R0;
  77         IFLUSH[P0];
  78         do_flush IFLUSH
  79 ENDPROC(_blackfin_icache_flush_range)
  80
  81 /* Throw away all D-cached data in specified region without any obligation to
  82  * write them back.  Since the Blackfin ISA does not have an "invalidate"
  83  * instruction, we use flush/invalidate.  Perhaps as a speed optimization we
  84  * could bang on the DTEST MMRs ...
  85  */
  86 ENTRY(_blackfin_dcache_invalidate_range)
  87         do_flush FLUSHINV
  88 ENDPROC(_blackfin_dcache_invalidate_range)
  89
  90 /* Flush all data cache lines assocoiated with this memory area */
  91 ENTRY(_blackfin_dcache_flush_range)
  92         do_flush FLUSH, .Ldfr
  93 ENDPROC(_blackfin_dcache_flush_range)
  94
  95 /* Our headers convert the page structure to an address, so just need to flush
  96  * its contents like normal.  We know the start address is page aligned (which
  97  * greater than our cache alignment), as is the end address.  So just jump into
  98  * the middle of the dcache flush function.
  99  */
 100 ENTRY(_blackfin_dflush_page)
 101         P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
 102         jump .Ldfr;
 103 ENDPROC(_blackfin_dflush_page)