arch/blackfin/mach-bf527/include/mach/defBF525.h

   1 /*
   2  * Copyright 2007-2008 Analog Devices Inc.
   3  *
   4  * Licensed under the ADI BSD license or the GPL-2 (or later)
   5  */
   6
   7 #ifndef _DEF_BF525_H
   8 #define _DEF_BF525_H
   9
  10 /* Include all Core registers and bit definitions */
  11 #include <asm/def_LPBlackfin.h>
  12
  13 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
  14
  15 /* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
  16 #include "defBF52x_base.h"
  17
  18 /* The following are the #defines needed by ADSP-BF525 that are not in the common header */
  19
  20 /* USB Control Registers */
  21
  22 #define                        USB_FADDR  0xffc03800   /* Function address register */
  23 #define                        USB_POWER  0xffc03804   /* Power management register */
  24 #define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
  25 #define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
  26 #define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
  27 #define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
  28 #define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
  29 #define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
  30 #define                        USB_FRAME  0xffc03820   /* USB frame number */
  31 #define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
  32 #define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
  33 #define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
  34 #define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
  35
  36 /* USB Packet Control Registers */
  37
  38 #define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
  39 #define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
  40 #define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
  41 #define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
  42 #define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
  43 #define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
  44 #define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
  45 #define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
  46 #define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
  47 #define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
  48 #define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
  49 #define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
  50 #define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
  51
  52 /* USB Endpoint FIFO Registers */
  53
  54 #define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
  55 #define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
  56 #define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
  57 #define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
  58 #define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
  59 #define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
  60 #define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
  61 #define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
  62
  63 /* USB OTG Control Registers */
  64
  65 #define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
  66 #define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
  67 #define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
  68
  69 /* USB Phy Control Registers */
  70
  71 #define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
  72 #define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
  73 #define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
  74 #define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
  75 #define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
  76
  77 /* (APHY_CNTRL is for ADI usage only) */
  78
  79 #define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
  80
  81 /* (APHY_CALIB is for ADI usage only) */
  82
  83 #define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
  84
  85 #define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
  86
  87 /* (PHY_TEST is for ADI usage only) */
  88
  89 #define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
  90
  91 #define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
  92 #define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
  93
  94 /* USB Endpoint 0 Control Registers */
  95
  96 #define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
  97 #define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
  98 #define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
  99 #define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
 100 #define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
 101 #define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 102 #define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
 103 #define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 104 #define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 105 #define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
 106
 107 /* USB Endpoint 1 Control Registers */
 108
 109 #define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
 110 #define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
 111 #define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
 112 #define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
 113 #define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
 114 #define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 115 #define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
 116 #define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 117 #define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 118 #define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 119
 120 /* USB Endpoint 2 Control Registers */
 121
 122 #define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
 123 #define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
 124 #define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
 125 #define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
 126 #define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
 127 #define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 128 #define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
 129 #define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 130 #define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 131 #define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
 132
 133 /* USB Endpoint 3 Control Registers */
 134
 135 #define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
 136 #define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
 137 #define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
 138 #define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
 139 #define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
 140 #define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 141 #define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
 142 #define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 143 #define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 144 #define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 145
 146 /* USB Endpoint 4 Control Registers */
 147
 148 #define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
 149 #define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
 150 #define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
 151 #define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
 152 #define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
 153 #define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 154 #define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
 155 #define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 156 #define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 157 #define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
 158
 159 /* USB Endpoint 5 Control Registers */
 160
 161 #define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
 162 #define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
 163 #define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
 164 #define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
 165 #define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
 166 #define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 167 #define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
 168 #define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 169 #define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 170 #define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
 171
 172 /* USB Endpoint 6 Control Registers */
 173
 174 #define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
 175 #define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
 176 #define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
 177 #define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
 178 #define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
 179 #define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 180 #define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
 181 #define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 182 #define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 183 #define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
 184
 185 /* USB Endpoint 7 Control Registers */
 186
 187 #define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
 188 #define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
 189 #define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
 190 #define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
 191 #define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
 192 #define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 193 #define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
 194 #define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 195 #define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 196 #define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
 197
 198 #define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
 199
 200 /* USB Channel 0 Config Registers */
 201
 202 #define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
 203 #define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 204 #define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 205 #define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 206 #define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 207
 208 /* USB Channel 1 Config Registers */
 209
 210 #define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
 211 #define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 212 #define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 213 #define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 214 #define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 215
 216 /* USB Channel 2 Config Registers */
 217
 218 #define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
 219 #define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 220 #define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 221 #define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 222 #define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 223
 224 /* USB Channel 3 Config Registers */
 225
 226 #define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
 227 #define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 228 #define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 229 #define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 230 #define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 231
 232 /* USB Channel 4 Config Registers */
 233
 234 #define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
 235 #define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 236 #define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 237 #define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 238 #define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 239
 240 /* USB Channel 5 Config Registers */
 241
 242 #define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
 243 #define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 244 #define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 245 #define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 246 #define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 247
 248 /* USB Channel 6 Config Registers */
 249
 250 #define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
 251 #define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 252 #define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 253 #define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 254 #define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 255
 256 /* USB Channel 7 Config Registers */
 257
 258 #define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
 259 #define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 260 #define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 261 #define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 262 #define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 263
 264 /* Bit masks for USB_FADDR */
 265
 266 #define          FUNCTION_ADDRESS  0x7f       /* Function address */
 267
 268 /* Bit masks for USB_POWER */
 269
 270 #define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
 271 #define          nENABLE_SUSPENDM  0x0
 272 #define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
 273 #define             nSUSPEND_MODE  0x0
 274 #define               RESUME_MODE  0x4        /* DMA Mode */
 275 #define              nRESUME_MODE  0x0
 276 #define                     RESET  0x8        /* Reset indicator */
 277 #define                    nRESET  0x0
 278 #define                   HS_MODE  0x10       /* High Speed mode indicator */
 279 #define                  nHS_MODE  0x0
 280 #define                 HS_ENABLE  0x20       /* high Speed Enable */
 281 #define                nHS_ENABLE  0x0
 282 #define                 SOFT_CONN  0x40       /* Soft connect */
 283 #define                nSOFT_CONN  0x0
 284 #define                ISO_UPDATE  0x80       /* Isochronous update */
 285 #define               nISO_UPDATE  0x0
 286
 287 /* Bit masks for USB_INTRTX */
 288
 289 #define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
 290 #define                   nEP0_TX  0x0
 291 #define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
 292 #define                   nEP1_TX  0x0
 293 #define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
 294 #define                   nEP2_TX  0x0
 295 #define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
 296 #define                   nEP3_TX  0x0
 297 #define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
 298 #define                   nEP4_TX  0x0
 299 #define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
 300 #define                   nEP5_TX  0x0
 301 #define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
 302 #define                   nEP6_TX  0x0
 303 #define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
 304 #define                   nEP7_TX  0x0
 305
 306 /* Bit masks for USB_INTRRX */
 307
 308 #define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
 309 #define                   nEP1_RX  0x0
 310 #define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
 311 #define                   nEP2_RX  0x0
 312 #define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
 313 #define                   nEP3_RX  0x0
 314 #define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
 315 #define                   nEP4_RX  0x0
 316 #define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
 317 #define                   nEP5_RX  0x0
 318 #define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
 319 #define                   nEP6_RX  0x0
 320 #define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
 321 #define                   nEP7_RX  0x0
 322
 323 /* Bit masks for USB_INTRTXE */
 324
 325 #define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
 326 #define                 nEP0_TX_E  0x0
 327 #define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
 328 #define                 nEP1_TX_E  0x0
 329 #define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
 330 #define                 nEP2_TX_E  0x0
 331 #define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
 332 #define                 nEP3_TX_E  0x0
 333 #define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
 334 #define                 nEP4_TX_E  0x0
 335 #define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
 336 #define                 nEP5_TX_E  0x0
 337 #define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
 338 #define                 nEP6_TX_E  0x0
 339 #define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
 340 #define                 nEP7_TX_E  0x0
 341
 342 /* Bit masks for USB_INTRRXE */
 343
 344 #define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
 345 #define                 nEP1_RX_E  0x0
 346 #define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
 347 #define                 nEP2_RX_E  0x0
 348 #define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
 349 #define                 nEP3_RX_E  0x0
 350 #define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
 351 #define                 nEP4_RX_E  0x0
 352 #define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
 353 #define                 nEP5_RX_E  0x0
 354 #define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
 355 #define                 nEP6_RX_E  0x0
 356 #define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
 357 #define                 nEP7_RX_E  0x0
 358
 359 /* Bit masks for USB_INTRUSB */
 360
 361 #define                 SUSPEND_B  0x1        /* Suspend indicator */
 362 #define                nSUSPEND_B  0x0
 363 #define                  RESUME_B  0x2        /* Resume indicator */
 364 #define                 nRESUME_B  0x0
 365 #define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
 366 #define         nRESET_OR_BABLE_B  0x0
 367 #define                     SOF_B  0x8        /* Start of frame */
 368 #define                    nSOF_B  0x0
 369 #define                    CONN_B  0x10       /* Connection indicator */
 370 #define                   nCONN_B  0x0
 371 #define                  DISCON_B  0x20       /* Disconnect indicator */
 372 #define                 nDISCON_B  0x0
 373 #define             SESSION_REQ_B  0x40       /* Session Request */
 374 #define            nSESSION_REQ_B  0x0
 375 #define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
 376 #define             nVBUS_ERROR_B  0x0
 377
 378 /* Bit masks for USB_INTRUSBE */
 379
 380 #define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
 381 #define               nSUSPEND_BE  0x0
 382 #define                 RESUME_BE  0x2        /* Resume indicator int enable */
 383 #define                nRESUME_BE  0x0
 384 #define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
 385 #define        nRESET_OR_BABLE_BE  0x0
 386 #define                    SOF_BE  0x8        /* Start of frame int enable */
 387 #define                   nSOF_BE  0x0
 388 #define                   CONN_BE  0x10       /* Connection indicator int enable */
 389 #define                  nCONN_BE  0x0
 390 #define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
 391 #define                nDISCON_BE  0x0
 392 #define            SESSION_REQ_BE  0x40       /* Session Request int enable */
 393 #define           nSESSION_REQ_BE  0x0
 394 #define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
 395 #define            nVBUS_ERROR_BE  0x0
 396
 397 /* Bit masks for USB_FRAME */
 398
 399 #define              FRAME_NUMBER  0x7ff      /* Frame number */
 400
 401 /* Bit masks for USB_INDEX */
 402
 403 #define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
 404
 405 /* Bit masks for USB_GLOBAL_CTL */
 406
 407 #define                GLOBAL_ENA  0x1        /* enables USB module */
 408 #define               nGLOBAL_ENA  0x0
 409 #define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
 410 #define               nEP1_TX_ENA  0x0
 411 #define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
 412 #define               nEP2_TX_ENA  0x0
 413 #define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
 414 #define               nEP3_TX_ENA  0x0
 415 #define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
 416 #define               nEP4_TX_ENA  0x0
 417 #define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
 418 #define               nEP5_TX_ENA  0x0
 419 #define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
 420 #define               nEP6_TX_ENA  0x0
 421 #define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
 422 #define               nEP7_TX_ENA  0x0
 423 #define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
 424 #define               nEP1_RX_ENA  0x0
 425 #define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
 426 #define               nEP2_RX_ENA  0x0
 427 #define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
 428 #define               nEP3_RX_ENA  0x0
 429 #define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
 430 #define               nEP4_RX_ENA  0x0
 431 #define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
 432 #define               nEP5_RX_ENA  0x0
 433 #define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
 434 #define               nEP6_RX_ENA  0x0
 435 #define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
 436 #define               nEP7_RX_ENA  0x0
 437
 438 /* Bit masks for USB_OTG_DEV_CTL */
 439
 440 #define                   SESSION  0x1        /* session indicator */
 441 #define                  nSESSION  0x0
 442 #define                  HOST_REQ  0x2        /* Host negotiation request */
 443 #define                 nHOST_REQ  0x0
 444 #define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
 445 #define                nHOST_MODE  0x0
 446 #define                     VBUS0  0x8        /* Vbus level indicator[0] */
 447 #define                    nVBUS0  0x0
 448 #define                     VBUS1  0x10       /* Vbus level indicator[1] */
 449 #define                    nVBUS1  0x0
 450 #define                     LSDEV  0x20       /* Low-speed indicator */
 451 #define                    nLSDEV  0x0
 452 #define                     FSDEV  0x40       /* Full or High-speed indicator */
 453 #define                    nFSDEV  0x0
 454 #define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
 455 #define                 nB_DEVICE  0x0
 456
 457 /* Bit masks for USB_OTG_VBUS_IRQ */
 458
 459 #define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
 460 #define            nDRIVE_VBUS_ON  0x0
 461 #define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
 462 #define           nDRIVE_VBUS_OFF  0x0
 463 #define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
 464 #define          nCHRG_VBUS_START  0x0
 465 #define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
 466 #define            nCHRG_VBUS_END  0x0
 467 #define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
 468 #define       nDISCHRG_VBUS_START  0x0
 469 #define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
 470 #define         nDISCHRG_VBUS_END  0x0
 471
 472 /* Bit masks for USB_OTG_VBUS_MASK */
 473
 474 #define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
 475 #define        nDRIVE_VBUS_ON_ENA  0x0
 476 #define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
 477 #define       nDRIVE_VBUS_OFF_ENA  0x0
 478 #define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
 479 #define      nCHRG_VBUS_START_ENA  0x0
 480 #define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
 481 #define        nCHRG_VBUS_END_ENA  0x0
 482 #define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
 483 #define   nDISCHRG_VBUS_START_ENA  0x0
 484 #define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
 485 #define     nDISCHRG_VBUS_END_ENA  0x0
 486
 487 /* Bit masks for USB_CSR0 */
 488
 489 #define                  RXPKTRDY  0x1        /* data packet receive indicator */
 490 #define                 nRXPKTRDY  0x0
 491 #define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
 492 #define                 nTXPKTRDY  0x0
 493 #define                STALL_SENT  0x4        /* STALL handshake sent */
 494 #define               nSTALL_SENT  0x0
 495 #define                   DATAEND  0x8        /* Data end indicator */
 496 #define                  nDATAEND  0x0
 497 #define                  SETUPEND  0x10       /* Setup end */
 498 #define                 nSETUPEND  0x0
 499 #define                 SENDSTALL  0x20       /* Send STALL handshake */
 500 #define                nSENDSTALL  0x0
 501 #define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
 502 #define        nSERVICED_RXPKTRDY  0x0
 503 #define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
 504 #define        nSERVICED_SETUPEND  0x0
 505 #define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
 506 #define                nFLUSHFIFO  0x0
 507 #define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
 508 #define         nSTALL_RECEIVED_H  0x0
 509 #define                SETUPPKT_H  0x8        /* send Setup token host mode */
 510 #define               nSETUPPKT_H  0x0
 511 #define                   ERROR_H  0x10       /* timeout error indicator host mode */
 512 #define                  nERROR_H  0x0
 513 #define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
 514 #define                 nREQPKT_H  0x0
 515 #define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
 516 #define              nSTATUSPKT_H  0x0
 517 #define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
 518 #define            nNAK_TIMEOUT_H  0x0
 519
 520 /* Bit masks for USB_COUNT0 */
 521
 522 #define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
 523
 524 /* Bit masks for USB_NAKLIMIT0 */
 525
 526 #define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
 527
 528 /* Bit masks for USB_TX_MAX_PACKET */
 529
 530 #define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
 531
 532 /* Bit masks for USB_RX_MAX_PACKET */
 533
 534 #define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
 535
 536 /* Bit masks for USB_TXCSR */
 537
 538 #define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
 539 #define               nTXPKTRDY_T  0x0
 540 #define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
 541 #define         nFIFO_NOT_EMPTY_T  0x0
 542 #define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
 543 #define               nUNDERRUN_T  0x0
 544 #define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
 545 #define              nFLUSHFIFO_T  0x0
 546 #define              STALL_SEND_T  0x10       /* issue a Stall handshake */
 547 #define             nSTALL_SEND_T  0x0
 548 #define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
 549 #define             nSTALL_SENT_T  0x0
 550 #define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
 551 #define       nCLEAR_DATATOGGLE_T  0x0
 552 #define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
 553 #define               nINCOMPTX_T  0x0
 554 #define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
 555 #define             nDMAREQMODE_T  0x0
 556 #define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
 557 #define       nFORCE_DATATOGGLE_T  0x0
 558 #define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
 559 #define             nDMAREQ_ENA_T  0x0
 560 #define                     ISO_T  0x4000     /* enable Isochronous transfers */
 561 #define                    nISO_T  0x0
 562 #define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
 563 #define                nAUTOSET_T  0x0
 564 #define                  ERROR_TH  0x4        /* error condition host mode */
 565 #define                 nERROR_TH  0x0
 566 #define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
 567 #define        nSTALL_RECEIVED_TH  0x0
 568 #define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
 569 #define           nNAK_TIMEOUT_TH  0x0
 570
 571 /* Bit masks for USB_TXCOUNT */
 572
 573 #define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
 574
 575 /* Bit masks for USB_RXCSR */
 576
 577 #define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
 578 #define               nRXPKTRDY_R  0x0
 579 #define               FIFO_FULL_R  0x2        /* FIFO not empty */
 580 #define              nFIFO_FULL_R  0x0
 581 #define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
 582 #define                nOVERRUN_R  0x0
 583 #define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
 584 #define              nDATAERROR_R  0x0
 585 #define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
 586 #define              nFLUSHFIFO_R  0x0
 587 #define              STALL_SEND_R  0x20       /* issue a Stall handshake */
 588 #define             nSTALL_SEND_R  0x0
 589 #define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
 590 #define             nSTALL_SENT_R  0x0
 591 #define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
 592 #define       nCLEAR_DATATOGGLE_R  0x0
 593 #define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
 594 #define               nINCOMPRX_R  0x0
 595 #define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
 596 #define             nDMAREQMODE_R  0x0
 597 #define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
 598 #define                nDISNYET_R  0x0
 599 #define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
 600 #define             nDMAREQ_ENA_R  0x0
 601 #define                     ISO_R  0x4000     /* enable Isochronous transfers */
 602 #define                    nISO_R  0x0
 603 #define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
 604 #define              nAUTOCLEAR_R  0x0
 605 #define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
 606 #define                 nERROR_RH  0x0
 607 #define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
 608 #define                nREQPKT_RH  0x0
 609 #define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
 610 #define        nSTALL_RECEIVED_RH  0x0
 611 #define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
 612 #define              nINCOMPRX_RH  0x0
 613 #define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
 614 #define            nDMAREQMODE_RH  0x0
 615 #define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
 616 #define               nAUTOREQ_RH  0x0
 617
 618 /* Bit masks for USB_RXCOUNT */
 619
 620 #define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
 621
 622 /* Bit masks for USB_TXTYPE */
 623
 624 #define            TARGET_EP_NO_T  0xf        /* EP number */
 625 #define                PROTOCOL_T  0xc        /* transfer type */
 626
 627 /* Bit masks for USB_TXINTERVAL */
 628
 629 #define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
 630
 631 /* Bit masks for USB_RXTYPE */
 632
 633 #define            TARGET_EP_NO_R  0xf        /* EP number */
 634 #define                PROTOCOL_R  0xc        /* transfer type */
 635
 636 /* Bit masks for USB_RXINTERVAL */
 637
 638 #define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
 639
 640 /* Bit masks for USB_DMA_INTERRUPT */
 641
 642 #define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
 643 #define                 nDMA0_INT  0x0
 644 #define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
 645 #define                 nDMA1_INT  0x0
 646 #define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
 647 #define                 nDMA2_INT  0x0
 648 #define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
 649 #define                 nDMA3_INT  0x0
 650 #define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
 651 #define                 nDMA4_INT  0x0
 652 #define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
 653 #define                 nDMA5_INT  0x0
 654 #define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
 655 #define                 nDMA6_INT  0x0
 656 #define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
 657 #define                 nDMA7_INT  0x0
 658
 659 /* Bit masks for USB_DMAxCONTROL */
 660
 661 #define                   DMA_ENA  0x1        /* DMA enable */
 662 #define                  nDMA_ENA  0x0
 663 #define                 DIRECTION  0x2        /* direction of DMA transfer */
 664 #define                nDIRECTION  0x0
 665 #define                      MODE  0x4        /* DMA Bus error */
 666 #define                     nMODE  0x0
 667 #define                   INT_ENA  0x8        /* Interrupt enable */
 668 #define                  nINT_ENA  0x0
 669 #define                     EPNUM  0xf0       /* EP number */
 670 #define                  BUSERROR  0x100      /* DMA Bus error */
 671 #define                 nBUSERROR  0x0
 672
 673 /* Bit masks for USB_DMAxADDRHIGH */
 674
 675 #define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
 676
 677 /* Bit masks for USB_DMAxADDRLOW */
 678
 679 #define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
 680
 681 /* Bit masks for USB_DMAxCOUNTHIGH */
 682
 683 #define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
 684
 685 /* Bit masks for USB_DMAxCOUNTLOW */
 686
 687 #define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
 688
 689 #endif /* _DEF_BF525_H */