arch/blackfin/kernel/cplb-mpu/cplbinit.c

   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  *               Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see the file COPYING, or write
  20  * to the Free Software Foundation, Inc.,
  21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23 #include <linux/module.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/cplb.h>
  27 #include <asm/cplbinit.h>
  28 #include <asm/mem_map.h>
  29
  30 #if ANOMALY_05000263
  31 # error the MPU will not function safely while Anomaly 05000263 applies
  32 #endif
  33
  34 struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
  35 struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
  36
  37 int first_switched_icplb, first_switched_dcplb;
  38 int first_mask_dcplb;
  39
  40 void __init generate_cplb_tables_cpu(unsigned int cpu)
  41 {
  42         int i_d, i_i;
  43         unsigned long addr;
  44         unsigned long d_data, i_data;
  45         unsigned long d_cache = 0, i_cache = 0;
  46
  47         printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
  48
  49 #ifdef CONFIG_BFIN_ICACHE
  50         i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
  51 #endif
  52
  53 #ifdef CONFIG_BFIN_DCACHE
  54         d_cache = CPLB_L1_CHBL;
  55 #ifdef CONFIG_BFIN_WT
  56         d_cache |= CPLB_L1_AOW | CPLB_WT;
  57 #endif
  58 #endif
  59
  60         i_d = i_i = 0;
  61
  62         /* Set up the zero page.  */
  63         dcplb_tbl[cpu][i_d].addr = 0;
  64         dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
  65
  66         icplb_tbl[cpu][i_i].addr = 0;
  67         icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
  68
  69         /* Cover kernel memory with 4M pages.  */
  70         addr = 0;
  71         d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
  72         i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
  73
  74         for (; addr < memory_start; addr += 4 * 1024 * 1024) {
  75                 dcplb_tbl[cpu][i_d].addr = addr;
  76                 dcplb_tbl[cpu][i_d++].data = d_data;
  77                 icplb_tbl[cpu][i_i].addr = addr;
  78                 icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
  79         }
  80
  81         /* Cover L1 memory.  One 4M area for code and data each is enough.  */
  82 #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
  83         dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
  84         dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
  85 #endif
  86 #if L1_CODE_LENGTH > 0
  87         icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
  88         icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
  89 #endif
  90
  91         /* Cover L2 memory */
  92 #if L2_LENGTH > 0
  93         dcplb_tbl[cpu][i_d].addr = L2_START;
  94         dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
  95         icplb_tbl[cpu][i_i].addr = L2_START;
  96         icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
  97 #endif
  98
  99         first_mask_dcplb = i_d;
 100         first_switched_dcplb = i_d + (1 << page_mask_order);
 101         first_switched_icplb = i_i;
 102
 103         while (i_d < MAX_CPLBS)
 104                 dcplb_tbl[cpu][i_d++].data = 0;
 105         while (i_i < MAX_CPLBS)
 106                 icplb_tbl[cpu][i_i++].data = 0;
 107 }
 108
 109 void generate_cplb_tables_all(void)
 110 {
 111 }