2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/gpio.h>
16 #include <linux/spi/spi.h>
17 #include <linux/usb/atmel_usba_udc.h>
19 #include <asm/atmel-mci.h>
23 #include <mach/at32ap700x.h>
24 #include <mach/board.h>
25 #include <mach/hmatrix.h>
26 #include <mach/portmux.h>
27 #include <mach/sram.h>
29 #include <video/atmel_lcdc.h>
39 .end = base + 0x3ff, \
40 .flags = IORESOURCE_MEM, \
46 .flags = IORESOURCE_IRQ, \
48 #define NAMED_IRQ(num, _name) \
53 .flags = IORESOURCE_IRQ, \
56 /* REVISIT these assume *every* device supports DMA, but several
57 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
59 #define DEFINE_DEV(_name, _id) \
60 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
61 static struct platform_device _name##_id##_device = { \
65 .dma_mask = &_name##_id##_dma_mask, \
66 .coherent_dma_mask = DMA_32BIT_MASK, \
68 .resource = _name##_id##_resource, \
69 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
71 #define DEFINE_DEV_DATA(_name, _id) \
72 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
73 static struct platform_device _name##_id##_device = { \
77 .dma_mask = &_name##_id##_dma_mask, \
78 .platform_data = &_name##_id##_data, \
79 .coherent_dma_mask = DMA_32BIT_MASK, \
81 .resource = _name##_id##_resource, \
82 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
85 #define select_peripheral(port, pin_mask, periph, flags) \
86 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
89 #define DEV_CLK(_name, devname, bus, _index) \
90 static struct clk devname##_##_name = { \
92 .dev = &devname##_device.dev, \
93 .parent = &bus##_clk, \
94 .mode = bus##_clk_mode, \
95 .get_rate = bus##_clk_get_rate, \
99 static DEFINE_SPINLOCK(pm_lock
);
101 static struct clk osc0
;
102 static struct clk osc1
;
104 static unsigned long osc_get_rate(struct clk
*clk
)
106 return at32_board_osc_rates
[clk
->index
];
109 static unsigned long pll_get_rate(struct clk
*clk
, unsigned long control
)
111 unsigned long div
, mul
, rate
;
113 div
= PM_BFEXT(PLLDIV
, control
) + 1;
114 mul
= PM_BFEXT(PLLMUL
, control
) + 1;
116 rate
= clk
->parent
->get_rate(clk
->parent
);
117 rate
= (rate
+ div
/ 2) / div
;
123 static long pll_set_rate(struct clk
*clk
, unsigned long rate
,
127 unsigned long mul_best_fit
= 0;
129 unsigned long div_min
;
130 unsigned long div_max
;
131 unsigned long div_best_fit
= 0;
133 unsigned long pll_in
;
134 unsigned long actual
= 0;
135 unsigned long rate_error
;
136 unsigned long rate_error_prev
= ~0UL;
139 /* Rate must be between 80 MHz and 200 Mhz. */
140 if (rate
< 80000000UL || rate
> 200000000UL)
143 ctrl
= PM_BF(PLLOPT
, 4);
144 base
= clk
->parent
->get_rate(clk
->parent
);
146 /* PLL input frequency must be between 6 MHz and 32 MHz. */
147 div_min
= DIV_ROUND_UP(base
, 32000000UL);
148 div_max
= base
/ 6000000UL;
150 if (div_max
< div_min
)
153 for (div
= div_min
; div
<= div_max
; div
++) {
154 pll_in
= (base
+ div
/ 2) / div
;
155 mul
= (rate
+ pll_in
/ 2) / pll_in
;
160 actual
= pll_in
* mul
;
161 rate_error
= abs(actual
- rate
);
163 if (rate_error
< rate_error_prev
) {
166 rate_error_prev
= rate_error
;
173 if (div_best_fit
== 0)
176 ctrl
|= PM_BF(PLLMUL
, mul_best_fit
- 1);
177 ctrl
|= PM_BF(PLLDIV
, div_best_fit
- 1);
178 ctrl
|= PM_BF(PLLCOUNT
, 16);
180 if (clk
->parent
== &osc1
)
181 ctrl
|= PM_BIT(PLLOSC
);
188 static unsigned long pll0_get_rate(struct clk
*clk
)
192 control
= pm_readl(PLL0
);
194 return pll_get_rate(clk
, control
);
197 static void pll1_mode(struct clk
*clk
, int enabled
)
199 unsigned long timeout
;
203 ctrl
= pm_readl(PLL1
);
206 if (!PM_BFEXT(PLLMUL
, ctrl
) && !PM_BFEXT(PLLDIV
, ctrl
)) {
207 pr_debug("clk %s: failed to enable, rate not set\n",
212 ctrl
|= PM_BIT(PLLEN
);
213 pm_writel(PLL1
, ctrl
);
215 /* Wait for PLL lock. */
216 for (timeout
= 10000; timeout
; timeout
--) {
217 status
= pm_readl(ISR
);
218 if (status
& PM_BIT(LOCK1
))
223 if (!(status
& PM_BIT(LOCK1
)))
224 printk(KERN_ERR
"clk %s: timeout waiting for lock\n",
227 ctrl
&= ~PM_BIT(PLLEN
);
228 pm_writel(PLL1
, ctrl
);
232 static unsigned long pll1_get_rate(struct clk
*clk
)
236 control
= pm_readl(PLL1
);
238 return pll_get_rate(clk
, control
);
241 static long pll1_set_rate(struct clk
*clk
, unsigned long rate
, int apply
)
244 unsigned long actual_rate
;
246 actual_rate
= pll_set_rate(clk
, rate
, &ctrl
);
249 if (actual_rate
!= rate
)
253 pr_debug(KERN_INFO
"clk %s: new rate %lu (actual rate %lu)\n",
254 clk
->name
, rate
, actual_rate
);
255 pm_writel(PLL1
, ctrl
);
261 static int pll1_set_parent(struct clk
*clk
, struct clk
*parent
)
268 ctrl
= pm_readl(PLL1
);
269 WARN_ON(ctrl
& PM_BIT(PLLEN
));
272 ctrl
&= ~PM_BIT(PLLOSC
);
273 else if (parent
== &osc1
)
274 ctrl
|= PM_BIT(PLLOSC
);
278 pm_writel(PLL1
, ctrl
);
279 clk
->parent
= parent
;
285 * The AT32AP7000 has five primary clock sources: One 32kHz
286 * oscillator, two crystal oscillators and two PLLs.
288 static struct clk osc32k
= {
290 .get_rate
= osc_get_rate
,
294 static struct clk osc0
= {
296 .get_rate
= osc_get_rate
,
300 static struct clk osc1
= {
302 .get_rate
= osc_get_rate
,
305 static struct clk pll0
= {
307 .get_rate
= pll0_get_rate
,
310 static struct clk pll1
= {
313 .get_rate
= pll1_get_rate
,
314 .set_rate
= pll1_set_rate
,
315 .set_parent
= pll1_set_parent
,
320 * The main clock can be either osc0 or pll0. The boot loader may
321 * have chosen one for us, so we don't really know which one until we
322 * have a look at the SM.
324 static struct clk
*main_clock
;
327 * Synchronous clocks are generated from the main clock. The clocks
328 * must satisfy the constraint
329 * fCPU >= fHSB >= fPB
330 * i.e. each clock must not be faster than its parent.
332 static unsigned long bus_clk_get_rate(struct clk
*clk
, unsigned int shift
)
334 return main_clock
->get_rate(main_clock
) >> shift
;
337 static void cpu_clk_mode(struct clk
*clk
, int enabled
)
342 spin_lock_irqsave(&pm_lock
, flags
);
343 mask
= pm_readl(CPU_MASK
);
345 mask
|= 1 << clk
->index
;
347 mask
&= ~(1 << clk
->index
);
348 pm_writel(CPU_MASK
, mask
);
349 spin_unlock_irqrestore(&pm_lock
, flags
);
352 static unsigned long cpu_clk_get_rate(struct clk
*clk
)
354 unsigned long cksel
, shift
= 0;
356 cksel
= pm_readl(CKSEL
);
357 if (cksel
& PM_BIT(CPUDIV
))
358 shift
= PM_BFEXT(CPUSEL
, cksel
) + 1;
360 return bus_clk_get_rate(clk
, shift
);
363 static long cpu_clk_set_rate(struct clk
*clk
, unsigned long rate
, int apply
)
366 unsigned long parent_rate
, child_div
, actual_rate
, div
;
368 parent_rate
= clk
->parent
->get_rate(clk
->parent
);
369 control
= pm_readl(CKSEL
);
371 if (control
& PM_BIT(HSBDIV
))
372 child_div
= 1 << (PM_BFEXT(HSBSEL
, control
) + 1);
376 if (rate
> 3 * (parent_rate
/ 4) || child_div
== 1) {
377 actual_rate
= parent_rate
;
378 control
&= ~PM_BIT(CPUDIV
);
381 div
= (parent_rate
+ rate
/ 2) / rate
;
384 cpusel
= (div
> 1) ? (fls(div
) - 2) : 0;
385 control
= PM_BIT(CPUDIV
) | PM_BFINS(CPUSEL
, cpusel
, control
);
386 actual_rate
= parent_rate
/ (1 << (cpusel
+ 1));
389 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
390 clk
->name
, rate
, actual_rate
);
393 pm_writel(CKSEL
, control
);
398 static void hsb_clk_mode(struct clk
*clk
, int enabled
)
403 spin_lock_irqsave(&pm_lock
, flags
);
404 mask
= pm_readl(HSB_MASK
);
406 mask
|= 1 << clk
->index
;
408 mask
&= ~(1 << clk
->index
);
409 pm_writel(HSB_MASK
, mask
);
410 spin_unlock_irqrestore(&pm_lock
, flags
);
413 static unsigned long hsb_clk_get_rate(struct clk
*clk
)
415 unsigned long cksel
, shift
= 0;
417 cksel
= pm_readl(CKSEL
);
418 if (cksel
& PM_BIT(HSBDIV
))
419 shift
= PM_BFEXT(HSBSEL
, cksel
) + 1;
421 return bus_clk_get_rate(clk
, shift
);
424 static void pba_clk_mode(struct clk
*clk
, int enabled
)
429 spin_lock_irqsave(&pm_lock
, flags
);
430 mask
= pm_readl(PBA_MASK
);
432 mask
|= 1 << clk
->index
;
434 mask
&= ~(1 << clk
->index
);
435 pm_writel(PBA_MASK
, mask
);
436 spin_unlock_irqrestore(&pm_lock
, flags
);
439 static unsigned long pba_clk_get_rate(struct clk
*clk
)
441 unsigned long cksel
, shift
= 0;
443 cksel
= pm_readl(CKSEL
);
444 if (cksel
& PM_BIT(PBADIV
))
445 shift
= PM_BFEXT(PBASEL
, cksel
) + 1;
447 return bus_clk_get_rate(clk
, shift
);
450 static void pbb_clk_mode(struct clk
*clk
, int enabled
)
455 spin_lock_irqsave(&pm_lock
, flags
);
456 mask
= pm_readl(PBB_MASK
);
458 mask
|= 1 << clk
->index
;
460 mask
&= ~(1 << clk
->index
);
461 pm_writel(PBB_MASK
, mask
);
462 spin_unlock_irqrestore(&pm_lock
, flags
);
465 static unsigned long pbb_clk_get_rate(struct clk
*clk
)
467 unsigned long cksel
, shift
= 0;
469 cksel
= pm_readl(CKSEL
);
470 if (cksel
& PM_BIT(PBBDIV
))
471 shift
= PM_BFEXT(PBBSEL
, cksel
) + 1;
473 return bus_clk_get_rate(clk
, shift
);
476 static struct clk cpu_clk
= {
478 .get_rate
= cpu_clk_get_rate
,
479 .set_rate
= cpu_clk_set_rate
,
482 static struct clk hsb_clk
= {
485 .get_rate
= hsb_clk_get_rate
,
487 static struct clk pba_clk
= {
490 .mode
= hsb_clk_mode
,
491 .get_rate
= pba_clk_get_rate
,
494 static struct clk pbb_clk
= {
497 .mode
= hsb_clk_mode
,
498 .get_rate
= pbb_clk_get_rate
,
503 /* --------------------------------------------------------------------
504 * Generic Clock operations
505 * -------------------------------------------------------------------- */
507 static void genclk_mode(struct clk
*clk
, int enabled
)
511 control
= pm_readl(GCCTRL(clk
->index
));
513 control
|= PM_BIT(CEN
);
515 control
&= ~PM_BIT(CEN
);
516 pm_writel(GCCTRL(clk
->index
), control
);
519 static unsigned long genclk_get_rate(struct clk
*clk
)
522 unsigned long div
= 1;
524 control
= pm_readl(GCCTRL(clk
->index
));
525 if (control
& PM_BIT(DIVEN
))
526 div
= 2 * (PM_BFEXT(DIV
, control
) + 1);
528 return clk
->parent
->get_rate(clk
->parent
) / div
;
531 static long genclk_set_rate(struct clk
*clk
, unsigned long rate
, int apply
)
534 unsigned long parent_rate
, actual_rate
, div
;
536 parent_rate
= clk
->parent
->get_rate(clk
->parent
);
537 control
= pm_readl(GCCTRL(clk
->index
));
539 if (rate
> 3 * parent_rate
/ 4) {
540 actual_rate
= parent_rate
;
541 control
&= ~PM_BIT(DIVEN
);
543 div
= (parent_rate
+ rate
) / (2 * rate
) - 1;
544 control
= PM_BFINS(DIV
, div
, control
) | PM_BIT(DIVEN
);
545 actual_rate
= parent_rate
/ (2 * (div
+ 1));
548 dev_dbg(clk
->dev
, "clk %s: new rate %lu (actual rate %lu)\n",
549 clk
->name
, rate
, actual_rate
);
552 pm_writel(GCCTRL(clk
->index
), control
);
557 int genclk_set_parent(struct clk
*clk
, struct clk
*parent
)
561 dev_dbg(clk
->dev
, "clk %s: new parent %s (was %s)\n",
562 clk
->name
, parent
->name
, clk
->parent
->name
);
564 control
= pm_readl(GCCTRL(clk
->index
));
566 if (parent
== &osc1
|| parent
== &pll1
)
567 control
|= PM_BIT(OSCSEL
);
568 else if (parent
== &osc0
|| parent
== &pll0
)
569 control
&= ~PM_BIT(OSCSEL
);
573 if (parent
== &pll0
|| parent
== &pll1
)
574 control
|= PM_BIT(PLLSEL
);
576 control
&= ~PM_BIT(PLLSEL
);
578 pm_writel(GCCTRL(clk
->index
), control
);
579 clk
->parent
= parent
;
584 static void __init
genclk_init_parent(struct clk
*clk
)
589 BUG_ON(clk
->index
> 7);
591 control
= pm_readl(GCCTRL(clk
->index
));
592 if (control
& PM_BIT(OSCSEL
))
593 parent
= (control
& PM_BIT(PLLSEL
)) ? &pll1
: &osc1
;
595 parent
= (control
& PM_BIT(PLLSEL
)) ? &pll0
: &osc0
;
597 clk
->parent
= parent
;
600 static struct dw_dma_platform_data dw_dmac0_data
= {
604 static struct resource dw_dmac0_resource
[] = {
608 DEFINE_DEV_DATA(dw_dmac
, 0);
609 DEV_CLK(hclk
, dw_dmac0
, hsb
, 10);
611 /* --------------------------------------------------------------------
613 * -------------------------------------------------------------------- */
614 static struct resource at32_pm0_resource
[] = {
618 .flags
= IORESOURCE_MEM
,
623 static struct resource at32ap700x_rtc0_resource
[] = {
627 .flags
= IORESOURCE_MEM
,
632 static struct resource at32_wdt0_resource
[] = {
636 .flags
= IORESOURCE_MEM
,
640 static struct resource at32_eic0_resource
[] = {
644 .flags
= IORESOURCE_MEM
,
649 DEFINE_DEV(at32_pm
, 0);
650 DEFINE_DEV(at32ap700x_rtc
, 0);
651 DEFINE_DEV(at32_wdt
, 0);
652 DEFINE_DEV(at32_eic
, 0);
655 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
658 static struct clk at32_pm_pclk
= {
660 .dev
= &at32_pm0_device
.dev
,
662 .mode
= pbb_clk_mode
,
663 .get_rate
= pbb_clk_get_rate
,
668 static struct resource intc0_resource
[] = {
671 struct platform_device at32_intc0_device
= {
674 .resource
= intc0_resource
,
675 .num_resources
= ARRAY_SIZE(intc0_resource
),
677 DEV_CLK(pclk
, at32_intc0
, pbb
, 1);
679 static struct clk ebi_clk
= {
682 .mode
= hsb_clk_mode
,
683 .get_rate
= hsb_clk_get_rate
,
686 static struct clk hramc_clk
= {
689 .mode
= hsb_clk_mode
,
690 .get_rate
= hsb_clk_get_rate
,
694 static struct clk sdramc_clk
= {
695 .name
= "sdramc_clk",
697 .mode
= pbb_clk_mode
,
698 .get_rate
= pbb_clk_get_rate
,
703 static struct resource smc0_resource
[] = {
707 DEV_CLK(pclk
, smc0
, pbb
, 13);
708 DEV_CLK(mck
, smc0
, hsb
, 0);
710 static struct platform_device pdc_device
= {
714 DEV_CLK(hclk
, pdc
, hsb
, 4);
715 DEV_CLK(pclk
, pdc
, pba
, 16);
717 static struct clk pico_clk
= {
720 .mode
= cpu_clk_mode
,
721 .get_rate
= cpu_clk_get_rate
,
725 /* --------------------------------------------------------------------
727 * -------------------------------------------------------------------- */
729 struct clk at32_hmatrix_clk
= {
730 .name
= "hmatrix_clk",
732 .mode
= pbb_clk_mode
,
733 .get_rate
= pbb_clk_get_rate
,
739 * Set bits in the HMATRIX Special Function Register (SFR) used by the
740 * External Bus Interface (EBI). This can be used to enable special
741 * features like CompactFlash support, NAND Flash support, etc. on
742 * certain chipselects.
744 static inline void set_ebi_sfr_bits(u32 mask
)
746 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI
, mask
);
749 /* --------------------------------------------------------------------
751 * -------------------------------------------------------------------- */
753 static struct resource at32_tcb0_resource
[] = {
757 static struct platform_device at32_tcb0_device
= {
760 .resource
= at32_tcb0_resource
,
761 .num_resources
= ARRAY_SIZE(at32_tcb0_resource
),
763 DEV_CLK(t0_clk
, at32_tcb0
, pbb
, 3);
765 static struct resource at32_tcb1_resource
[] = {
769 static struct platform_device at32_tcb1_device
= {
772 .resource
= at32_tcb1_resource
,
773 .num_resources
= ARRAY_SIZE(at32_tcb1_resource
),
775 DEV_CLK(t0_clk
, at32_tcb1
, pbb
, 4);
777 /* --------------------------------------------------------------------
779 * -------------------------------------------------------------------- */
781 static struct resource pio0_resource
[] = {
786 DEV_CLK(mck
, pio0
, pba
, 10);
788 static struct resource pio1_resource
[] = {
793 DEV_CLK(mck
, pio1
, pba
, 11);
795 static struct resource pio2_resource
[] = {
800 DEV_CLK(mck
, pio2
, pba
, 12);
802 static struct resource pio3_resource
[] = {
807 DEV_CLK(mck
, pio3
, pba
, 13);
809 static struct resource pio4_resource
[] = {
814 DEV_CLK(mck
, pio4
, pba
, 14);
816 void __init
at32_add_system_devices(void)
818 platform_device_register(&at32_pm0_device
);
819 platform_device_register(&at32_intc0_device
);
820 platform_device_register(&at32ap700x_rtc0_device
);
821 platform_device_register(&at32_wdt0_device
);
822 platform_device_register(&at32_eic0_device
);
823 platform_device_register(&smc0_device
);
824 platform_device_register(&pdc_device
);
825 platform_device_register(&dw_dmac0_device
);
827 platform_device_register(&at32_tcb0_device
);
828 platform_device_register(&at32_tcb1_device
);
830 platform_device_register(&pio0_device
);
831 platform_device_register(&pio1_device
);
832 platform_device_register(&pio2_device
);
833 platform_device_register(&pio3_device
);
834 platform_device_register(&pio4_device
);
837 /* --------------------------------------------------------------------
839 * -------------------------------------------------------------------- */
840 static struct resource atmel_psif0_resource
[] __initdata
= {
844 .flags
= IORESOURCE_MEM
,
848 static struct clk atmel_psif0_pclk
= {
851 .mode
= pba_clk_mode
,
852 .get_rate
= pba_clk_get_rate
,
856 static struct resource atmel_psif1_resource
[] __initdata
= {
860 .flags
= IORESOURCE_MEM
,
864 static struct clk atmel_psif1_pclk
= {
867 .mode
= pba_clk_mode
,
868 .get_rate
= pba_clk_get_rate
,
872 struct platform_device
*__init
at32_add_device_psif(unsigned int id
)
874 struct platform_device
*pdev
;
877 if (!(id
== 0 || id
== 1))
880 pdev
= platform_device_alloc("atmel_psif", id
);
886 pin_mask
= (1 << 8) | (1 << 9); /* CLOCK & DATA */
888 if (platform_device_add_resources(pdev
, atmel_psif0_resource
,
889 ARRAY_SIZE(atmel_psif0_resource
)))
890 goto err_add_resources
;
891 atmel_psif0_pclk
.dev
= &pdev
->dev
;
892 select_peripheral(PIOA
, pin_mask
, PERIPH_A
, 0);
895 pin_mask
= (1 << 11) | (1 << 12); /* CLOCK & DATA */
897 if (platform_device_add_resources(pdev
, atmel_psif1_resource
,
898 ARRAY_SIZE(atmel_psif1_resource
)))
899 goto err_add_resources
;
900 atmel_psif1_pclk
.dev
= &pdev
->dev
;
901 select_peripheral(PIOB
, pin_mask
, PERIPH_A
, 0);
907 platform_device_add(pdev
);
911 platform_device_put(pdev
);
915 /* --------------------------------------------------------------------
917 * -------------------------------------------------------------------- */
919 static struct atmel_uart_data atmel_usart0_data
= {
923 static struct resource atmel_usart0_resource
[] = {
927 DEFINE_DEV_DATA(atmel_usart
, 0);
928 DEV_CLK(usart
, atmel_usart0
, pba
, 3);
930 static struct atmel_uart_data atmel_usart1_data
= {
934 static struct resource atmel_usart1_resource
[] = {
938 DEFINE_DEV_DATA(atmel_usart
, 1);
939 DEV_CLK(usart
, atmel_usart1
, pba
, 4);
941 static struct atmel_uart_data atmel_usart2_data
= {
945 static struct resource atmel_usart2_resource
[] = {
949 DEFINE_DEV_DATA(atmel_usart
, 2);
950 DEV_CLK(usart
, atmel_usart2
, pba
, 5);
952 static struct atmel_uart_data atmel_usart3_data
= {
956 static struct resource atmel_usart3_resource
[] = {
960 DEFINE_DEV_DATA(atmel_usart
, 3);
961 DEV_CLK(usart
, atmel_usart3
, pba
, 6);
963 static inline void configure_usart0_pins(void)
965 u32 pin_mask
= (1 << 8) | (1 << 9); /* RXD & TXD */
967 select_peripheral(PIOA
, pin_mask
, PERIPH_B
, 0);
970 static inline void configure_usart1_pins(void)
972 u32 pin_mask
= (1 << 17) | (1 << 18); /* RXD & TXD */
974 select_peripheral(PIOA
, pin_mask
, PERIPH_A
, 0);
977 static inline void configure_usart2_pins(void)
979 u32 pin_mask
= (1 << 26) | (1 << 27); /* RXD & TXD */
981 select_peripheral(PIOB
, pin_mask
, PERIPH_B
, 0);
984 static inline void configure_usart3_pins(void)
986 u32 pin_mask
= (1 << 18) | (1 << 17); /* RXD & TXD */
988 select_peripheral(PIOB
, pin_mask
, PERIPH_B
, 0);
991 static struct platform_device
*__initdata at32_usarts
[4];
993 void __init
at32_map_usart(unsigned int hw_id
, unsigned int line
)
995 struct platform_device
*pdev
;
999 pdev
= &atmel_usart0_device
;
1000 configure_usart0_pins();
1003 pdev
= &atmel_usart1_device
;
1004 configure_usart1_pins();
1007 pdev
= &atmel_usart2_device
;
1008 configure_usart2_pins();
1011 pdev
= &atmel_usart3_device
;
1012 configure_usart3_pins();
1018 if (PXSEG(pdev
->resource
[0].start
) == P4SEG
) {
1019 /* Addresses in the P4 segment are permanently mapped 1:1 */
1020 struct atmel_uart_data
*data
= pdev
->dev
.platform_data
;
1021 data
->regs
= (void __iomem
*)pdev
->resource
[0].start
;
1025 at32_usarts
[line
] = pdev
;
1028 struct platform_device
*__init
at32_add_device_usart(unsigned int id
)
1030 platform_device_register(at32_usarts
[id
]);
1031 return at32_usarts
[id
];
1034 struct platform_device
*atmel_default_console_device
;
1036 void __init
at32_setup_serial_console(unsigned int usart_id
)
1038 atmel_default_console_device
= at32_usarts
[usart_id
];
1041 /* --------------------------------------------------------------------
1043 * -------------------------------------------------------------------- */
1045 #ifdef CONFIG_CPU_AT32AP7000
1046 static struct eth_platform_data macb0_data
;
1047 static struct resource macb0_resource
[] = {
1051 DEFINE_DEV_DATA(macb
, 0);
1052 DEV_CLK(hclk
, macb0
, hsb
, 8);
1053 DEV_CLK(pclk
, macb0
, pbb
, 6);
1055 static struct eth_platform_data macb1_data
;
1056 static struct resource macb1_resource
[] = {
1060 DEFINE_DEV_DATA(macb
, 1);
1061 DEV_CLK(hclk
, macb1
, hsb
, 9);
1062 DEV_CLK(pclk
, macb1
, pbb
, 7);
1064 struct platform_device
*__init
1065 at32_add_device_eth(unsigned int id
, struct eth_platform_data
*data
)
1067 struct platform_device
*pdev
;
1072 pdev
= &macb0_device
;
1074 pin_mask
= (1 << 3); /* TXD0 */
1075 pin_mask
|= (1 << 4); /* TXD1 */
1076 pin_mask
|= (1 << 7); /* TXEN */
1077 pin_mask
|= (1 << 8); /* TXCK */
1078 pin_mask
|= (1 << 9); /* RXD0 */
1079 pin_mask
|= (1 << 10); /* RXD1 */
1080 pin_mask
|= (1 << 13); /* RXER */
1081 pin_mask
|= (1 << 15); /* RXDV */
1082 pin_mask
|= (1 << 16); /* MDC */
1083 pin_mask
|= (1 << 17); /* MDIO */
1085 if (!data
->is_rmii
) {
1086 pin_mask
|= (1 << 0); /* COL */
1087 pin_mask
|= (1 << 1); /* CRS */
1088 pin_mask
|= (1 << 2); /* TXER */
1089 pin_mask
|= (1 << 5); /* TXD2 */
1090 pin_mask
|= (1 << 6); /* TXD3 */
1091 pin_mask
|= (1 << 11); /* RXD2 */
1092 pin_mask
|= (1 << 12); /* RXD3 */
1093 pin_mask
|= (1 << 14); /* RXCK */
1094 pin_mask
|= (1 << 18); /* SPD */
1097 select_peripheral(PIOC
, pin_mask
, PERIPH_A
, 0);
1102 pdev
= &macb1_device
;
1104 pin_mask
= (1 << 13); /* TXD0 */
1105 pin_mask
|= (1 << 14); /* TXD1 */
1106 pin_mask
|= (1 << 11); /* TXEN */
1107 pin_mask
|= (1 << 12); /* TXCK */
1108 pin_mask
|= (1 << 10); /* RXD0 */
1109 pin_mask
|= (1 << 6); /* RXD1 */
1110 pin_mask
|= (1 << 5); /* RXER */
1111 pin_mask
|= (1 << 4); /* RXDV */
1112 pin_mask
|= (1 << 3); /* MDC */
1113 pin_mask
|= (1 << 2); /* MDIO */
1116 pin_mask
|= (1 << 15); /* SPD */
1118 select_peripheral(PIOD
, pin_mask
, PERIPH_B
, 0);
1120 if (!data
->is_rmii
) {
1121 pin_mask
= (1 << 19); /* COL */
1122 pin_mask
|= (1 << 23); /* CRS */
1123 pin_mask
|= (1 << 26); /* TXER */
1124 pin_mask
|= (1 << 27); /* TXD2 */
1125 pin_mask
|= (1 << 28); /* TXD3 */
1126 pin_mask
|= (1 << 29); /* RXD2 */
1127 pin_mask
|= (1 << 30); /* RXD3 */
1128 pin_mask
|= (1 << 24); /* RXCK */
1130 select_peripheral(PIOC
, pin_mask
, PERIPH_B
, 0);
1138 memcpy(pdev
->dev
.platform_data
, data
, sizeof(struct eth_platform_data
));
1139 platform_device_register(pdev
);
1145 /* --------------------------------------------------------------------
1147 * -------------------------------------------------------------------- */
1148 static struct resource atmel_spi0_resource
[] = {
1152 DEFINE_DEV(atmel_spi
, 0);
1153 DEV_CLK(spi_clk
, atmel_spi0
, pba
, 0);
1155 static struct resource atmel_spi1_resource
[] = {
1159 DEFINE_DEV(atmel_spi
, 1);
1160 DEV_CLK(spi_clk
, atmel_spi1
, pba
, 1);
1163 at32_spi_setup_slaves(unsigned int bus_num
, struct spi_board_info
*b
,
1164 unsigned int n
, const u8
*pins
)
1166 unsigned int pin
, mode
;
1168 for (; n
; n
--, b
++) {
1169 b
->bus_num
= bus_num
;
1170 if (b
->chip_select
>= 4)
1172 pin
= (unsigned)b
->controller_data
;
1174 pin
= pins
[b
->chip_select
];
1175 b
->controller_data
= (void *)pin
;
1177 mode
= AT32_GPIOF_OUTPUT
;
1178 if (!(b
->mode
& SPI_CS_HIGH
))
1179 mode
|= AT32_GPIOF_HIGH
;
1180 at32_select_gpio(pin
, mode
);
1184 struct platform_device
*__init
1185 at32_add_device_spi(unsigned int id
, struct spi_board_info
*b
, unsigned int n
)
1188 * Manage the chipselects as GPIOs, normally using the same pins
1189 * the SPI controller expects; but boards can use other pins.
1191 static u8 __initdata spi0_pins
[] =
1192 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1193 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1194 static u8 __initdata spi1_pins
[] =
1195 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1196 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1197 struct platform_device
*pdev
;
1202 pdev
= &atmel_spi0_device
;
1203 pin_mask
= (1 << 1) | (1 << 2); /* MOSI & SCK */
1205 /* pullup MISO so a level is always defined */
1206 select_peripheral(PIOA
, (1 << 0), PERIPH_A
, AT32_GPIOF_PULLUP
);
1207 select_peripheral(PIOA
, pin_mask
, PERIPH_A
, 0);
1209 at32_spi_setup_slaves(0, b
, n
, spi0_pins
);
1213 pdev
= &atmel_spi1_device
;
1214 pin_mask
= (1 << 1) | (1 << 5); /* MOSI */
1216 /* pullup MISO so a level is always defined */
1217 select_peripheral(PIOB
, (1 << 0), PERIPH_B
, AT32_GPIOF_PULLUP
);
1218 select_peripheral(PIOB
, pin_mask
, PERIPH_B
, 0);
1220 at32_spi_setup_slaves(1, b
, n
, spi1_pins
);
1227 spi_register_board_info(b
, n
);
1228 platform_device_register(pdev
);
1232 /* --------------------------------------------------------------------
1234 * -------------------------------------------------------------------- */
1235 static struct resource atmel_twi0_resource
[] __initdata
= {
1239 static struct clk atmel_twi0_pclk
= {
1242 .mode
= pba_clk_mode
,
1243 .get_rate
= pba_clk_get_rate
,
1247 struct platform_device
*__init
at32_add_device_twi(unsigned int id
,
1248 struct i2c_board_info
*b
,
1251 struct platform_device
*pdev
;
1257 pdev
= platform_device_alloc("atmel_twi", id
);
1261 if (platform_device_add_resources(pdev
, atmel_twi0_resource
,
1262 ARRAY_SIZE(atmel_twi0_resource
)))
1263 goto err_add_resources
;
1265 pin_mask
= (1 << 6) | (1 << 7); /* SDA & SDL */
1267 select_peripheral(PIOA
, pin_mask
, PERIPH_A
, 0);
1269 atmel_twi0_pclk
.dev
= &pdev
->dev
;
1272 i2c_register_board_info(id
, b
, n
);
1274 platform_device_add(pdev
);
1278 platform_device_put(pdev
);
1282 /* --------------------------------------------------------------------
1284 * -------------------------------------------------------------------- */
1285 static struct resource atmel_mci0_resource
[] __initdata
= {
1289 static struct clk atmel_mci0_pclk
= {
1292 .mode
= pbb_clk_mode
,
1293 .get_rate
= pbb_clk_get_rate
,
1297 struct platform_device
*__init
1298 at32_add_device_mci(unsigned int id
, struct mci_platform_data
*data
)
1300 struct platform_device
*pdev
;
1301 struct dw_dma_slave
*dws
;
1305 if (id
!= 0 || !data
)
1308 /* Must have at least one usable slot */
1309 if (!data
->slot
[0].bus_width
&& !data
->slot
[1].bus_width
)
1312 pdev
= platform_device_alloc("atmel_mci", id
);
1316 if (platform_device_add_resources(pdev
, atmel_mci0_resource
,
1317 ARRAY_SIZE(atmel_mci0_resource
)))
1320 if (data
->dma_slave
)
1321 dws
= kmemdup(to_dw_dma_slave(data
->dma_slave
),
1322 sizeof(struct dw_dma_slave
), GFP_KERNEL
);
1324 dws
= kzalloc(sizeof(struct dw_dma_slave
), GFP_KERNEL
);
1326 dws
->slave
.dev
= &pdev
->dev
;
1327 dws
->slave
.dma_dev
= &dw_dmac0_device
.dev
;
1328 dws
->slave
.reg_width
= DMA_SLAVE_WIDTH_32BIT
;
1329 dws
->cfg_hi
= (DWC_CFGH_SRC_PER(0)
1330 | DWC_CFGH_DST_PER(1));
1331 dws
->cfg_lo
&= ~(DWC_CFGL_HS_DST_POL
1332 | DWC_CFGL_HS_SRC_POL
);
1334 data
->dma_slave
= &dws
->slave
;
1336 if (platform_device_add_data(pdev
, data
,
1337 sizeof(struct mci_platform_data
)))
1340 /* CLK line is common to both slots */
1341 pioa_mask
= 1 << 10;
1343 switch (data
->slot
[0].bus_width
) {
1345 pioa_mask
|= 1 << 13; /* DATA1 */
1346 pioa_mask
|= 1 << 14; /* DATA2 */
1347 pioa_mask
|= 1 << 15; /* DATA3 */
1350 pioa_mask
|= 1 << 11; /* CMD */
1351 pioa_mask
|= 1 << 12; /* DATA0 */
1353 if (gpio_is_valid(data
->slot
[0].detect_pin
))
1354 at32_select_gpio(data
->slot
[0].detect_pin
, 0);
1355 if (gpio_is_valid(data
->slot
[0].wp_pin
))
1356 at32_select_gpio(data
->slot
[0].wp_pin
, 0);
1359 /* Slot is unused */
1365 select_peripheral(PIOA
, pioa_mask
, PERIPH_A
, 0);
1368 switch (data
->slot
[1].bus_width
) {
1370 piob_mask
|= 1 << 8; /* DATA1 */
1371 piob_mask
|= 1 << 9; /* DATA2 */
1372 piob_mask
|= 1 << 10; /* DATA3 */
1375 piob_mask
|= 1 << 6; /* CMD */
1376 piob_mask
|= 1 << 7; /* DATA0 */
1377 select_peripheral(PIOB
, piob_mask
, PERIPH_B
, 0);
1379 if (gpio_is_valid(data
->slot
[1].detect_pin
))
1380 at32_select_gpio(data
->slot
[1].detect_pin
, 0);
1381 if (gpio_is_valid(data
->slot
[1].wp_pin
))
1382 at32_select_gpio(data
->slot
[1].wp_pin
, 0);
1385 /* Slot is unused */
1388 if (!data
->slot
[0].bus_width
)
1391 data
->slot
[1].bus_width
= 0;
1395 atmel_mci0_pclk
.dev
= &pdev
->dev
;
1397 platform_device_add(pdev
);
1401 platform_device_put(pdev
);
1405 /* --------------------------------------------------------------------
1407 * -------------------------------------------------------------------- */
1408 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1409 static struct atmel_lcdfb_info atmel_lcdfb0_data
;
1410 static struct resource atmel_lcdfb0_resource
[] = {
1412 .start
= 0xff000000,
1414 .flags
= IORESOURCE_MEM
,
1418 /* Placeholder for pre-allocated fb memory */
1419 .start
= 0x00000000,
1424 DEFINE_DEV_DATA(atmel_lcdfb
, 0);
1425 DEV_CLK(hck1
, atmel_lcdfb0
, hsb
, 7);
1426 static struct clk atmel_lcdfb0_pixclk
= {
1428 .dev
= &atmel_lcdfb0_device
.dev
,
1429 .mode
= genclk_mode
,
1430 .get_rate
= genclk_get_rate
,
1431 .set_rate
= genclk_set_rate
,
1432 .set_parent
= genclk_set_parent
,
1436 struct platform_device
*__init
1437 at32_add_device_lcdc(unsigned int id
, struct atmel_lcdfb_info
*data
,
1438 unsigned long fbmem_start
, unsigned long fbmem_len
,
1441 struct platform_device
*pdev
;
1442 struct atmel_lcdfb_info
*info
;
1443 struct fb_monspecs
*monspecs
;
1444 struct fb_videomode
*modedb
;
1445 unsigned int modedb_size
;
1446 u32 portc_mask
, portd_mask
, porte_mask
;
1449 * Do a deep copy of the fb data, monspecs and modedb. Make
1450 * sure all allocations are done before setting up the
1453 monspecs
= kmemdup(data
->default_monspecs
,
1454 sizeof(struct fb_monspecs
), GFP_KERNEL
);
1458 modedb_size
= sizeof(struct fb_videomode
) * monspecs
->modedb_len
;
1459 modedb
= kmemdup(monspecs
->modedb
, modedb_size
, GFP_KERNEL
);
1461 goto err_dup_modedb
;
1462 monspecs
->modedb
= modedb
;
1466 pdev
= &atmel_lcdfb0_device
;
1468 if (pin_mask
== 0ULL)
1469 /* Default to "full" lcdc control signals and 24bit */
1470 pin_mask
= ATMEL_LCDC_PRI_24BIT
| ATMEL_LCDC_PRI_CONTROL
;
1472 /* LCDC on port C */
1473 portc_mask
= (pin_mask
& 0xfff80000) >> 19;
1474 select_peripheral(PIOC
, portc_mask
, PERIPH_A
, 0);
1476 /* LCDC on port D */
1477 portd_mask
= pin_mask
& 0x0003ffff;
1478 select_peripheral(PIOD
, portd_mask
, PERIPH_A
, 0);
1480 /* LCDC on port E */
1481 porte_mask
= (pin_mask
>> 32) & 0x0007ffff;
1482 select_peripheral(PIOE
, porte_mask
, PERIPH_B
, 0);
1484 clk_set_parent(&atmel_lcdfb0_pixclk
, &pll0
);
1485 clk_set_rate(&atmel_lcdfb0_pixclk
, clk_get_rate(&pll0
));
1489 goto err_invalid_id
;
1493 pdev
->resource
[2].start
= fbmem_start
;
1494 pdev
->resource
[2].end
= fbmem_start
+ fbmem_len
- 1;
1495 pdev
->resource
[2].flags
= IORESOURCE_MEM
;
1498 info
= pdev
->dev
.platform_data
;
1499 memcpy(info
, data
, sizeof(struct atmel_lcdfb_info
));
1500 info
->default_monspecs
= monspecs
;
1502 platform_device_register(pdev
);
1513 /* --------------------------------------------------------------------
1515 * -------------------------------------------------------------------- */
1516 static struct resource atmel_pwm0_resource
[] __initdata
= {
1520 static struct clk atmel_pwm0_mck
= {
1523 .mode
= pbb_clk_mode
,
1524 .get_rate
= pbb_clk_get_rate
,
1528 struct platform_device
*__init
at32_add_device_pwm(u32 mask
)
1530 struct platform_device
*pdev
;
1536 pdev
= platform_device_alloc("atmel_pwm", 0);
1540 if (platform_device_add_resources(pdev
, atmel_pwm0_resource
,
1541 ARRAY_SIZE(atmel_pwm0_resource
)))
1544 if (platform_device_add_data(pdev
, &mask
, sizeof(mask
)))
1548 if (mask
& (1 << 0))
1549 pin_mask
|= (1 << 28);
1550 if (mask
& (1 << 1))
1551 pin_mask
|= (1 << 29);
1553 select_peripheral(PIOA
, pin_mask
, PERIPH_A
, 0);
1556 if (mask
& (1 << 2))
1557 pin_mask
|= (1 << 21);
1558 if (mask
& (1 << 3))
1559 pin_mask
|= (1 << 22);
1561 select_peripheral(PIOA
, pin_mask
, PERIPH_B
, 0);
1563 atmel_pwm0_mck
.dev
= &pdev
->dev
;
1565 platform_device_add(pdev
);
1570 platform_device_put(pdev
);
1574 /* --------------------------------------------------------------------
1576 * -------------------------------------------------------------------- */
1577 static struct resource ssc0_resource
[] = {
1582 DEV_CLK(pclk
, ssc0
, pba
, 7);
1584 static struct resource ssc1_resource
[] = {
1589 DEV_CLK(pclk
, ssc1
, pba
, 8);
1591 static struct resource ssc2_resource
[] = {
1596 DEV_CLK(pclk
, ssc2
, pba
, 9);
1598 struct platform_device
*__init
1599 at32_add_device_ssc(unsigned int id
, unsigned int flags
)
1601 struct platform_device
*pdev
;
1606 pdev
= &ssc0_device
;
1607 if (flags
& ATMEL_SSC_RF
)
1608 pin_mask
|= (1 << 21); /* RF */
1609 if (flags
& ATMEL_SSC_RK
)
1610 pin_mask
|= (1 << 22); /* RK */
1611 if (flags
& ATMEL_SSC_TK
)
1612 pin_mask
|= (1 << 23); /* TK */
1613 if (flags
& ATMEL_SSC_TF
)
1614 pin_mask
|= (1 << 24); /* TF */
1615 if (flags
& ATMEL_SSC_TD
)
1616 pin_mask
|= (1 << 25); /* TD */
1617 if (flags
& ATMEL_SSC_RD
)
1618 pin_mask
|= (1 << 26); /* RD */
1621 select_peripheral(PIOA
, pin_mask
, PERIPH_A
, 0);
1625 pdev
= &ssc1_device
;
1626 if (flags
& ATMEL_SSC_RF
)
1627 pin_mask
|= (1 << 0); /* RF */
1628 if (flags
& ATMEL_SSC_RK
)
1629 pin_mask
|= (1 << 1); /* RK */
1630 if (flags
& ATMEL_SSC_TK
)
1631 pin_mask
|= (1 << 2); /* TK */
1632 if (flags
& ATMEL_SSC_TF
)
1633 pin_mask
|= (1 << 3); /* TF */
1634 if (flags
& ATMEL_SSC_TD
)
1635 pin_mask
|= (1 << 4); /* TD */
1636 if (flags
& ATMEL_SSC_RD
)
1637 pin_mask
|= (1 << 5); /* RD */
1640 select_peripheral(PIOA
, pin_mask
, PERIPH_B
, 0);
1644 pdev
= &ssc2_device
;
1645 if (flags
& ATMEL_SSC_TD
)
1646 pin_mask
|= (1 << 13); /* TD */
1647 if (flags
& ATMEL_SSC_RD
)
1648 pin_mask
|= (1 << 14); /* RD */
1649 if (flags
& ATMEL_SSC_TK
)
1650 pin_mask
|= (1 << 15); /* TK */
1651 if (flags
& ATMEL_SSC_TF
)
1652 pin_mask
|= (1 << 16); /* TF */
1653 if (flags
& ATMEL_SSC_RF
)
1654 pin_mask
|= (1 << 17); /* RF */
1655 if (flags
& ATMEL_SSC_RK
)
1656 pin_mask
|= (1 << 18); /* RK */
1659 select_peripheral(PIOB
, pin_mask
, PERIPH_A
, 0);
1666 platform_device_register(pdev
);
1670 /* --------------------------------------------------------------------
1671 * USB Device Controller
1672 * -------------------------------------------------------------------- */
1673 static struct resource usba0_resource
[] __initdata
= {
1675 .start
= 0xff300000,
1677 .flags
= IORESOURCE_MEM
,
1679 .start
= 0xfff03000,
1681 .flags
= IORESOURCE_MEM
,
1685 static struct clk usba0_pclk
= {
1688 .mode
= pbb_clk_mode
,
1689 .get_rate
= pbb_clk_get_rate
,
1692 static struct clk usba0_hclk
= {
1695 .mode
= hsb_clk_mode
,
1696 .get_rate
= hsb_clk_get_rate
,
1700 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1704 .fifo_size = maxpkt, \
1705 .nr_banks = maxbk, \
1710 static struct usba_ep_data at32_usba_ep
[] __initdata
= {
1711 EP("ep0", 0, 64, 1, 0, 0),
1712 EP("ep1", 1, 512, 2, 1, 1),
1713 EP("ep2", 2, 512, 2, 1, 1),
1714 EP("ep3-int", 3, 64, 3, 1, 0),
1715 EP("ep4-int", 4, 64, 3, 1, 0),
1716 EP("ep5", 5, 1024, 3, 1, 1),
1717 EP("ep6", 6, 1024, 3, 1, 1),
1722 struct platform_device
*__init
1723 at32_add_device_usba(unsigned int id
, struct usba_platform_data
*data
)
1726 * pdata doesn't have room for any endpoints, so we need to
1727 * append room for the ones we need right after it.
1730 struct usba_platform_data pdata
;
1731 struct usba_ep_data ep
[7];
1733 struct platform_device
*pdev
;
1738 pdev
= platform_device_alloc("atmel_usba_udc", 0);
1742 if (platform_device_add_resources(pdev
, usba0_resource
,
1743 ARRAY_SIZE(usba0_resource
)))
1747 usba_data
.pdata
.vbus_pin
= data
->vbus_pin
;
1749 usba_data
.pdata
.vbus_pin
= -EINVAL
;
1751 data
= &usba_data
.pdata
;
1752 data
->num_ep
= ARRAY_SIZE(at32_usba_ep
);
1753 memcpy(data
->ep
, at32_usba_ep
, sizeof(at32_usba_ep
));
1755 if (platform_device_add_data(pdev
, data
, sizeof(usba_data
)))
1758 if (data
->vbus_pin
>= 0)
1759 at32_select_gpio(data
->vbus_pin
, 0);
1761 usba0_pclk
.dev
= &pdev
->dev
;
1762 usba0_hclk
.dev
= &pdev
->dev
;
1764 platform_device_add(pdev
);
1769 platform_device_put(pdev
);
1773 /* --------------------------------------------------------------------
1774 * IDE / CompactFlash
1775 * -------------------------------------------------------------------- */
1776 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1777 static struct resource at32_smc_cs4_resource
[] __initdata
= {
1779 .start
= 0x04000000,
1781 .flags
= IORESOURCE_MEM
,
1783 IRQ(~0UL), /* Magic IRQ will be overridden */
1785 static struct resource at32_smc_cs5_resource
[] __initdata
= {
1787 .start
= 0x20000000,
1789 .flags
= IORESOURCE_MEM
,
1791 IRQ(~0UL), /* Magic IRQ will be overridden */
1794 static int __init
at32_init_ide_or_cf(struct platform_device
*pdev
,
1795 unsigned int cs
, unsigned int extint
)
1797 static unsigned int extint_pin_map
[4] __initdata
= {
1803 static bool common_pins_initialized __initdata
= false;
1804 unsigned int extint_pin
;
1808 if (extint
>= ARRAY_SIZE(extint_pin_map
))
1810 extint_pin
= extint_pin_map
[extint
];
1814 ret
= platform_device_add_resources(pdev
,
1815 at32_smc_cs4_resource
,
1816 ARRAY_SIZE(at32_smc_cs4_resource
));
1821 select_peripheral(PIOE
, (1 << 21), PERIPH_A
, 0);
1822 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI
, HMATRIX_EBI_CF0_ENABLE
);
1825 ret
= platform_device_add_resources(pdev
,
1826 at32_smc_cs5_resource
,
1827 ARRAY_SIZE(at32_smc_cs5_resource
));
1832 select_peripheral(PIOE
, (1 << 22), PERIPH_A
, 0);
1833 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI
, HMATRIX_EBI_CF1_ENABLE
);
1839 if (!common_pins_initialized
) {
1840 pin_mask
= (1 << 19); /* CFCE1 -> CS0_N */
1841 pin_mask
|= (1 << 20); /* CFCE2 -> CS1_N */
1842 pin_mask
|= (1 << 23); /* CFRNW -> DIR */
1843 pin_mask
|= (1 << 24); /* NWAIT <- IORDY */
1845 select_peripheral(PIOE
, pin_mask
, PERIPH_A
, 0);
1847 common_pins_initialized
= true;
1850 select_peripheral(PIOB
, extint_pin
, PERIPH_A
, AT32_GPIOF_DEGLITCH
);
1852 pdev
->resource
[1].start
= EIM_IRQ_BASE
+ extint
;
1853 pdev
->resource
[1].end
= pdev
->resource
[1].start
;
1858 struct platform_device
*__init
1859 at32_add_device_ide(unsigned int id
, unsigned int extint
,
1860 struct ide_platform_data
*data
)
1862 struct platform_device
*pdev
;
1864 pdev
= platform_device_alloc("at32_ide", id
);
1868 if (platform_device_add_data(pdev
, data
,
1869 sizeof(struct ide_platform_data
)))
1872 if (at32_init_ide_or_cf(pdev
, data
->cs
, extint
))
1875 platform_device_add(pdev
);
1879 platform_device_put(pdev
);
1883 struct platform_device
*__init
1884 at32_add_device_cf(unsigned int id
, unsigned int extint
,
1885 struct cf_platform_data
*data
)
1887 struct platform_device
*pdev
;
1889 pdev
= platform_device_alloc("at32_cf", id
);
1893 if (platform_device_add_data(pdev
, data
,
1894 sizeof(struct cf_platform_data
)))
1897 if (at32_init_ide_or_cf(pdev
, data
->cs
, extint
))
1900 if (gpio_is_valid(data
->detect_pin
))
1901 at32_select_gpio(data
->detect_pin
, AT32_GPIOF_DEGLITCH
);
1902 if (gpio_is_valid(data
->reset_pin
))
1903 at32_select_gpio(data
->reset_pin
, 0);
1904 if (gpio_is_valid(data
->vcc_pin
))
1905 at32_select_gpio(data
->vcc_pin
, 0);
1906 /* READY is used as extint, so we can't select it as gpio */
1908 platform_device_add(pdev
);
1912 platform_device_put(pdev
);
1917 /* --------------------------------------------------------------------
1918 * NAND Flash / SmartMedia
1919 * -------------------------------------------------------------------- */
1920 static struct resource smc_cs3_resource
[] __initdata
= {
1922 .start
= 0x0c000000,
1924 .flags
= IORESOURCE_MEM
,
1926 .start
= 0xfff03c00,
1928 .flags
= IORESOURCE_MEM
,
1932 struct platform_device
*__init
1933 at32_add_device_nand(unsigned int id
, struct atmel_nand_data
*data
)
1935 struct platform_device
*pdev
;
1937 if (id
!= 0 || !data
)
1940 pdev
= platform_device_alloc("atmel_nand", id
);
1944 if (platform_device_add_resources(pdev
, smc_cs3_resource
,
1945 ARRAY_SIZE(smc_cs3_resource
)))
1948 if (platform_device_add_data(pdev
, data
,
1949 sizeof(struct atmel_nand_data
)))
1952 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI
, HMATRIX_EBI_NAND_ENABLE
);
1953 if (data
->enable_pin
)
1954 at32_select_gpio(data
->enable_pin
,
1955 AT32_GPIOF_OUTPUT
| AT32_GPIOF_HIGH
);
1957 at32_select_gpio(data
->rdy_pin
, 0);
1959 at32_select_gpio(data
->det_pin
, 0);
1961 platform_device_add(pdev
);
1965 platform_device_put(pdev
);
1969 /* --------------------------------------------------------------------
1971 * -------------------------------------------------------------------- */
1972 static struct resource atmel_ac97c0_resource
[] __initdata
= {
1976 static struct clk atmel_ac97c0_pclk
= {
1979 .mode
= pbb_clk_mode
,
1980 .get_rate
= pbb_clk_get_rate
,
1984 struct platform_device
*__init
1985 at32_add_device_ac97c(unsigned int id
, struct ac97c_platform_data
*data
)
1987 struct platform_device
*pdev
;
1988 struct ac97c_platform_data _data
;
1994 pdev
= platform_device_alloc("atmel_ac97c", id
);
1998 if (platform_device_add_resources(pdev
, atmel_ac97c0_resource
,
1999 ARRAY_SIZE(atmel_ac97c0_resource
)))
2004 memset(data
, 0, sizeof(struct ac97c_platform_data
));
2005 data
->reset_pin
= GPIO_PIN_NONE
;
2008 data
->dma_rx_periph_id
= 3;
2009 data
->dma_tx_periph_id
= 4;
2010 data
->dma_controller_id
= 0;
2012 if (platform_device_add_data(pdev
, data
,
2013 sizeof(struct ac97c_platform_data
)))
2016 pin_mask
= (1 << 20) | (1 << 21); /* SDO & SYNC */
2017 pin_mask
|= (1 << 22) | (1 << 23); /* SCLK & SDI */
2019 select_peripheral(PIOB
, pin_mask
, PERIPH_B
, 0);
2021 /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
2022 if (data
->reset_pin
!= GPIO_PIN_NONE
)
2023 at32_select_gpio(data
->reset_pin
, 0);
2025 atmel_ac97c0_pclk
.dev
= &pdev
->dev
;
2027 platform_device_add(pdev
);
2031 platform_device_put(pdev
);
2035 /* --------------------------------------------------------------------
2037 * -------------------------------------------------------------------- */
2038 static struct resource abdac0_resource
[] __initdata
= {
2042 static struct clk abdac0_pclk
= {
2045 .mode
= pbb_clk_mode
,
2046 .get_rate
= pbb_clk_get_rate
,
2049 static struct clk abdac0_sample_clk
= {
2050 .name
= "sample_clk",
2051 .mode
= genclk_mode
,
2052 .get_rate
= genclk_get_rate
,
2053 .set_rate
= genclk_set_rate
,
2054 .set_parent
= genclk_set_parent
,
2058 struct platform_device
*__init
at32_add_device_abdac(unsigned int id
)
2060 struct platform_device
*pdev
;
2066 pdev
= platform_device_alloc("abdac", id
);
2070 if (platform_device_add_resources(pdev
, abdac0_resource
,
2071 ARRAY_SIZE(abdac0_resource
)))
2072 goto err_add_resources
;
2074 pin_mask
= (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2075 pin_mask
|= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2077 select_peripheral(PIOB
, pin_mask
, PERIPH_A
, 0);
2079 abdac0_pclk
.dev
= &pdev
->dev
;
2080 abdac0_sample_clk
.dev
= &pdev
->dev
;
2082 platform_device_add(pdev
);
2086 platform_device_put(pdev
);
2090 /* --------------------------------------------------------------------
2092 * -------------------------------------------------------------------- */
2093 static struct clk gclk0
= {
2095 .mode
= genclk_mode
,
2096 .get_rate
= genclk_get_rate
,
2097 .set_rate
= genclk_set_rate
,
2098 .set_parent
= genclk_set_parent
,
2101 static struct clk gclk1
= {
2103 .mode
= genclk_mode
,
2104 .get_rate
= genclk_get_rate
,
2105 .set_rate
= genclk_set_rate
,
2106 .set_parent
= genclk_set_parent
,
2109 static struct clk gclk2
= {
2111 .mode
= genclk_mode
,
2112 .get_rate
= genclk_get_rate
,
2113 .set_rate
= genclk_set_rate
,
2114 .set_parent
= genclk_set_parent
,
2117 static struct clk gclk3
= {
2119 .mode
= genclk_mode
,
2120 .get_rate
= genclk_get_rate
,
2121 .set_rate
= genclk_set_rate
,
2122 .set_parent
= genclk_set_parent
,
2125 static struct clk gclk4
= {
2127 .mode
= genclk_mode
,
2128 .get_rate
= genclk_get_rate
,
2129 .set_rate
= genclk_set_rate
,
2130 .set_parent
= genclk_set_parent
,
2134 static __initdata
struct clk
*init_clocks
[] = {
2165 &atmel_usart0_usart
,
2166 &atmel_usart1_usart
,
2167 &atmel_usart2_usart
,
2168 &atmel_usart3_usart
,
2170 #if defined(CONFIG_CPU_AT32AP7000)
2176 &atmel_spi0_spi_clk
,
2177 &atmel_spi1_spi_clk
,
2180 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2182 &atmel_lcdfb0_pixclk
,
2199 void __init
setup_platform(void)
2201 u32 cpu_mask
= 0, hsb_mask
= 0, pba_mask
= 0, pbb_mask
= 0;
2204 if (pm_readl(MCCTRL
) & PM_BIT(PLLSEL
)) {
2206 cpu_clk
.parent
= &pll0
;
2209 cpu_clk
.parent
= &osc0
;
2212 if (pm_readl(PLL0
) & PM_BIT(PLLOSC
))
2213 pll0
.parent
= &osc1
;
2214 if (pm_readl(PLL1
) & PM_BIT(PLLOSC
))
2215 pll1
.parent
= &osc1
;
2217 genclk_init_parent(&gclk0
);
2218 genclk_init_parent(&gclk1
);
2219 genclk_init_parent(&gclk2
);
2220 genclk_init_parent(&gclk3
);
2221 genclk_init_parent(&gclk4
);
2222 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2223 genclk_init_parent(&atmel_lcdfb0_pixclk
);
2225 genclk_init_parent(&abdac0_sample_clk
);
2228 * Build initial dynamic clock list by registering all clocks
2230 * At the same time, turn on all clocks that have at least one
2231 * user already, and turn off everything else. We only do this
2232 * for module clocks, and even though it isn't particularly
2233 * pretty to check the address of the mode function, it should
2236 for (i
= 0; i
< ARRAY_SIZE(init_clocks
); i
++) {
2237 struct clk
*clk
= init_clocks
[i
];
2239 /* first, register clock */
2240 at32_clk_register(clk
);
2242 if (clk
->users
== 0)
2245 if (clk
->mode
== &cpu_clk_mode
)
2246 cpu_mask
|= 1 << clk
->index
;
2247 else if (clk
->mode
== &hsb_clk_mode
)
2248 hsb_mask
|= 1 << clk
->index
;
2249 else if (clk
->mode
== &pba_clk_mode
)
2250 pba_mask
|= 1 << clk
->index
;
2251 else if (clk
->mode
== &pbb_clk_mode
)
2252 pbb_mask
|= 1 << clk
->index
;
2255 pm_writel(CPU_MASK
, cpu_mask
);
2256 pm_writel(HSB_MASK
, hsb_mask
);
2257 pm_writel(PBA_MASK
, pba_mask
);
2258 pm_writel(PBB_MASK
, pbb_mask
);
2260 /* Initialize the port muxes */
2261 at32_init_pio(&pio0_device
);
2262 at32_init_pio(&pio1_device
);
2263 at32_init_pio(&pio2_device
);
2264 at32_init_pio(&pio3_device
);
2265 at32_init_pio(&pio4_device
);
2268 struct gen_pool
*sram_pool
;
2270 static int __init
sram_init(void)
2272 struct gen_pool
*pool
;
2274 /* 1KiB granularity */
2275 pool
= gen_pool_create(10, -1);
2279 if (gen_pool_add(pool
, 0x24000000, 0x8000, -1))
2286 gen_pool_destroy(pool
);
2288 pr_err("Failed to create SRAM pool\n");
2291 core_initcall(sram_init
);