Merge branch 'e1000-fixes' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / avr32 / kernel / cpu.c
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/init.h>
9 #include <linux/sysdev.h>
10 #include <linux/seq_file.h>
11 #include <linux/cpu.h>
12 #include <linux/module.h>
13 #include <linux/percpu.h>
14 #include <linux/param.h>
15 #include <linux/errno.h>
16
17 #include <asm/setup.h>
18 #include <asm/sysreg.h>
19
20 static DEFINE_PER_CPU(struct cpu, cpu_devices);
21
22 #ifdef CONFIG_PERFORMANCE_COUNTERS
23
24 /*
25 * XXX: If/when a SMP-capable implementation of AVR32 will ever be
26 * made, we must make sure that the code executes on the correct CPU.
27 */
28 static ssize_t show_pc0event(struct sys_device *dev, char *buf)
29 {
30 unsigned long pccr;
31
32 pccr = sysreg_read(PCCR);
33 return sprintf(buf, "0x%lx\n", (pccr >> 12) & 0x3f);
34 }
35 static ssize_t store_pc0event(struct sys_device *dev, const char *buf,
36 size_t count)
37 {
38 unsigned long val;
39 char *endp;
40
41 val = simple_strtoul(buf, &endp, 0);
42 if (endp == buf || val > 0x3f)
43 return -EINVAL;
44 val = (val << 12) | (sysreg_read(PCCR) & 0xfffc0fff);
45 sysreg_write(PCCR, val);
46 return count;
47 }
48 static ssize_t show_pc0count(struct sys_device *dev, char *buf)
49 {
50 unsigned long pcnt0;
51
52 pcnt0 = sysreg_read(PCNT0);
53 return sprintf(buf, "%lu\n", pcnt0);
54 }
55 static ssize_t store_pc0count(struct sys_device *dev, const char *buf,
56 size_t count)
57 {
58 unsigned long val;
59 char *endp;
60
61 val = simple_strtoul(buf, &endp, 0);
62 if (endp == buf)
63 return -EINVAL;
64 sysreg_write(PCNT0, val);
65
66 return count;
67 }
68
69 static ssize_t show_pc1event(struct sys_device *dev, char *buf)
70 {
71 unsigned long pccr;
72
73 pccr = sysreg_read(PCCR);
74 return sprintf(buf, "0x%lx\n", (pccr >> 18) & 0x3f);
75 }
76 static ssize_t store_pc1event(struct sys_device *dev, const char *buf,
77 size_t count)
78 {
79 unsigned long val;
80 char *endp;
81
82 val = simple_strtoul(buf, &endp, 0);
83 if (endp == buf || val > 0x3f)
84 return -EINVAL;
85 val = (val << 18) | (sysreg_read(PCCR) & 0xff03ffff);
86 sysreg_write(PCCR, val);
87 return count;
88 }
89 static ssize_t show_pc1count(struct sys_device *dev, char *buf)
90 {
91 unsigned long pcnt1;
92
93 pcnt1 = sysreg_read(PCNT1);
94 return sprintf(buf, "%lu\n", pcnt1);
95 }
96 static ssize_t store_pc1count(struct sys_device *dev, const char *buf,
97 size_t count)
98 {
99 unsigned long val;
100 char *endp;
101
102 val = simple_strtoul(buf, &endp, 0);
103 if (endp == buf)
104 return -EINVAL;
105 sysreg_write(PCNT1, val);
106
107 return count;
108 }
109
110 static ssize_t show_pccycles(struct sys_device *dev, char *buf)
111 {
112 unsigned long pccnt;
113
114 pccnt = sysreg_read(PCCNT);
115 return sprintf(buf, "%lu\n", pccnt);
116 }
117 static ssize_t store_pccycles(struct sys_device *dev, const char *buf,
118 size_t count)
119 {
120 unsigned long val;
121 char *endp;
122
123 val = simple_strtoul(buf, &endp, 0);
124 if (endp == buf)
125 return -EINVAL;
126 sysreg_write(PCCNT, val);
127
128 return count;
129 }
130
131 static ssize_t show_pcenable(struct sys_device *dev, char *buf)
132 {
133 unsigned long pccr;
134
135 pccr = sysreg_read(PCCR);
136 return sprintf(buf, "%c\n", (pccr & 1)?'1':'0');
137 }
138 static ssize_t store_pcenable(struct sys_device *dev, const char *buf,
139 size_t count)
140 {
141 unsigned long pccr, val;
142 char *endp;
143
144 val = simple_strtoul(buf, &endp, 0);
145 if (endp == buf)
146 return -EINVAL;
147 if (val)
148 val = 1;
149
150 pccr = sysreg_read(PCCR);
151 pccr = (pccr & ~1UL) | val;
152 sysreg_write(PCCR, pccr);
153
154 return count;
155 }
156
157 static SYSDEV_ATTR(pc0event, 0600, show_pc0event, store_pc0event);
158 static SYSDEV_ATTR(pc0count, 0600, show_pc0count, store_pc0count);
159 static SYSDEV_ATTR(pc1event, 0600, show_pc1event, store_pc1event);
160 static SYSDEV_ATTR(pc1count, 0600, show_pc1count, store_pc1count);
161 static SYSDEV_ATTR(pccycles, 0600, show_pccycles, store_pccycles);
162 static SYSDEV_ATTR(pcenable, 0600, show_pcenable, store_pcenable);
163
164 #endif /* CONFIG_PERFORMANCE_COUNTERS */
165
166 static int __init topology_init(void)
167 {
168 int cpu;
169
170 for_each_possible_cpu(cpu) {
171 struct cpu *c = &per_cpu(cpu_devices, cpu);
172
173 register_cpu(c, cpu);
174
175 #ifdef CONFIG_PERFORMANCE_COUNTERS
176 sysdev_create_file(&c->sysdev, &attr_pc0event);
177 sysdev_create_file(&c->sysdev, &attr_pc0count);
178 sysdev_create_file(&c->sysdev, &attr_pc1event);
179 sysdev_create_file(&c->sysdev, &attr_pc1count);
180 sysdev_create_file(&c->sysdev, &attr_pccycles);
181 sysdev_create_file(&c->sysdev, &attr_pcenable);
182 #endif
183 }
184
185 return 0;
186 }
187
188 subsys_initcall(topology_init);
189
190 static const char *cpu_names[] = {
191 "Morgan",
192 "AP7000",
193 };
194 #define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
195
196 static const char *arch_names[] = {
197 "AVR32A",
198 "AVR32B",
199 };
200 #define NR_ARCH_NAMES ARRAY_SIZE(arch_names)
201
202 static const char *mmu_types[] = {
203 "No MMU",
204 "ITLB and DTLB",
205 "Shared TLB",
206 "MPU"
207 };
208
209 void __init setup_processor(void)
210 {
211 unsigned long config0, config1;
212 unsigned long features;
213 unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
214 unsigned tmp;
215
216 config0 = sysreg_read(CONFIG0);
217 config1 = sysreg_read(CONFIG1);
218 cpu_id = SYSREG_BFEXT(PROCESSORID, config0);
219 cpu_rev = SYSREG_BFEXT(PROCESSORREVISION, config0);
220 arch_id = SYSREG_BFEXT(AT, config0);
221 arch_rev = SYSREG_BFEXT(AR, config0);
222 mmu_type = SYSREG_BFEXT(MMUT, config0);
223
224 boot_cpu_data.arch_type = arch_id;
225 boot_cpu_data.cpu_type = cpu_id;
226 boot_cpu_data.arch_revision = arch_rev;
227 boot_cpu_data.cpu_revision = cpu_rev;
228 boot_cpu_data.tlb_config = mmu_type;
229
230 tmp = SYSREG_BFEXT(ILSZ, config1);
231 if (tmp) {
232 boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1);
233 boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1);
234 boot_cpu_data.icache.linesz = 1 << (tmp + 1);
235 }
236 tmp = SYSREG_BFEXT(DLSZ, config1);
237 if (tmp) {
238 boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1);
239 boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1);
240 boot_cpu_data.dcache.linesz = 1 << (tmp + 1);
241 }
242
243 if ((cpu_id >= NR_CPU_NAMES) || (arch_id >= NR_ARCH_NAMES)) {
244 printk ("Unknown CPU configuration (ID %02x, arch %02x), "
245 "continuing anyway...\n",
246 cpu_id, arch_id);
247 return;
248 }
249
250 printk ("CPU: %s [%02x] revision %d (%s revision %d)\n",
251 cpu_names[cpu_id], cpu_id, cpu_rev,
252 arch_names[arch_id], arch_rev);
253 printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
254
255 printk ("CPU: features:");
256 features = 0;
257 if (config0 & SYSREG_BIT(CONFIG0_R)) {
258 features |= AVR32_FEATURE_RMW;
259 printk(" rmw");
260 }
261 if (config0 & SYSREG_BIT(CONFIG0_D)) {
262 features |= AVR32_FEATURE_DSP;
263 printk(" dsp");
264 }
265 if (config0 & SYSREG_BIT(CONFIG0_S)) {
266 features |= AVR32_FEATURE_SIMD;
267 printk(" simd");
268 }
269 if (config0 & SYSREG_BIT(CONFIG0_O)) {
270 features |= AVR32_FEATURE_OCD;
271 printk(" ocd");
272 }
273 if (config0 & SYSREG_BIT(CONFIG0_P)) {
274 features |= AVR32_FEATURE_PCTR;
275 printk(" perfctr");
276 }
277 if (config0 & SYSREG_BIT(CONFIG0_J)) {
278 features |= AVR32_FEATURE_JAVA;
279 printk(" java");
280 }
281 if (config0 & SYSREG_BIT(CONFIG0_F)) {
282 features |= AVR32_FEATURE_FPU;
283 printk(" fpu");
284 }
285 printk("\n");
286 boot_cpu_data.features = features;
287 }
288
289 #ifdef CONFIG_PROC_FS
290 static int c_show(struct seq_file *m, void *v)
291 {
292 unsigned int icache_size, dcache_size;
293 unsigned int cpu = smp_processor_id();
294
295 icache_size = boot_cpu_data.icache.ways *
296 boot_cpu_data.icache.sets *
297 boot_cpu_data.icache.linesz;
298 dcache_size = boot_cpu_data.dcache.ways *
299 boot_cpu_data.dcache.sets *
300 boot_cpu_data.dcache.linesz;
301
302 seq_printf(m, "processor\t: %d\n", cpu);
303
304 if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
305 seq_printf(m, "cpu family\t: %s revision %d\n",
306 arch_names[boot_cpu_data.arch_type],
307 boot_cpu_data.arch_revision);
308 if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
309 seq_printf(m, "cpu type\t: %s revision %d\n",
310 cpu_names[boot_cpu_data.cpu_type],
311 boot_cpu_data.cpu_revision);
312
313 seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
314 icache_size >> 10,
315 boot_cpu_data.icache.ways,
316 boot_cpu_data.icache.sets,
317 boot_cpu_data.icache.linesz);
318 seq_printf(m, "d-cache\t\t: %dK (%u ways x %u sets x %u)\n",
319 dcache_size >> 10,
320 boot_cpu_data.dcache.ways,
321 boot_cpu_data.dcache.sets,
322 boot_cpu_data.dcache.linesz);
323 seq_printf(m, "bogomips\t: %lu.%02lu\n",
324 boot_cpu_data.loops_per_jiffy / (500000/HZ),
325 (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
326
327 return 0;
328 }
329
330 static void *c_start(struct seq_file *m, loff_t *pos)
331 {
332 return *pos < 1 ? (void *)1 : NULL;
333 }
334
335 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
336 {
337 ++*pos;
338 return NULL;
339 }
340
341 static void c_stop(struct seq_file *m, void *v)
342 {
343
344 }
345
346 struct seq_operations cpuinfo_op = {
347 .start = c_start,
348 .next = c_next,
349 .stop = c_stop,
350 .show = c_show
351 };
352 #endif /* CONFIG_PROC_FS */