arch/arm64/include/asm/cputype.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_CPUTYPE_H
  17 #define __ASM_CPUTYPE_H
  18
  19 #define INVALID_HWID            ULONG_MAX
  20
  21 #define MPIDR_UP_BITMASK        (0x1 << 30)
  22 #define MPIDR_MT_BITMASK        (0x1 << 24)
  23 #define MPIDR_HWID_BITMASK      0xff00ffffff
  24
  25 #define MPIDR_SMP_BITMASK       (0x3 << 30)
  26 #define MPIDR_SMP_VALUE         (0x2 << 30)
  27 #define MPIDR_MT_BITMASK        (0x1 << 24)
  28
  29 #define MPIDR_LEVEL_BITS_SHIFT  3
  30 #define MPIDR_LEVEL_BITS        (1 << MPIDR_LEVEL_BITS_SHIFT)
  31 #define MPIDR_LEVEL_MASK        ((1 << MPIDR_LEVEL_BITS) - 1)
  32
  33 #define MPIDR_LEVEL_SHIFT(level) \
  34         (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
  35
  36 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  37         ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
  38
  39 #define MIDR_REVISION_MASK      0xf
  40 #define MIDR_REVISION(midr)     ((midr) & MIDR_REVISION_MASK)
  41 #define MIDR_PARTNUM_SHIFT      4
  42 #define MIDR_PARTNUM_MASK       (0xfff << MIDR_PARTNUM_SHIFT)
  43 #define MIDR_PARTNUM(midr)      \
  44         (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
  45 #define MIDR_ARCHITECTURE_SHIFT 16
  46 #define MIDR_ARCHITECTURE_MASK  (0xf << MIDR_ARCHITECTURE_SHIFT)
  47 #define MIDR_ARCHITECTURE(midr) \
  48         (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
  49 #define MIDR_VARIANT_SHIFT      20
  50 #define MIDR_VARIANT_MASK       (0xf << MIDR_VARIANT_SHIFT)
  51 #define MIDR_VARIANT(midr)      \
  52         (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
  53 #define MIDR_IMPLEMENTOR_SHIFT  24
  54 #define MIDR_IMPLEMENTOR_MASK   (0xff << MIDR_IMPLEMENTOR_SHIFT)
  55 #define MIDR_IMPLEMENTOR(midr)  \
  56         (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
  57
  58 #define MIDR_CPU_MODEL(imp, partnum) \
  59         (((imp)                 << MIDR_IMPLEMENTOR_SHIFT) | \
  60         (0xf                    << MIDR_ARCHITECTURE_SHIFT) | \
  61         ((partnum)              << MIDR_PARTNUM_SHIFT))
  62
  63 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
  64                              MIDR_ARCHITECTURE_MASK)
  65
  66 #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max)            \
  67 ({                                                                      \
  68         u32 _model = (midr) & MIDR_CPU_MODEL_MASK;                      \
  69         u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);     \
  70                                                                         \
  71         _model == (model) && rv >= (rv_min) && rv <= (rv_max);          \
  72  })
  73
  74 #define ARM_CPU_IMP_ARM                 0x41
  75 #define ARM_CPU_IMP_APM                 0x50
  76 #define ARM_CPU_IMP_CAVIUM              0x43
  77 #define ARM_CPU_IMP_SEC                 0x53
  78
  79 #define ARM_CPU_PART_AEM_V8             0xD0F
  80 #define ARM_CPU_PART_FOUNDATION         0xD00
  81 #define ARM_CPU_PART_CORTEX_A57         0xD07
  82 #define ARM_CPU_PART_CORTEX_A53         0xD03
  83 #define ARM_CPU_PART_MONGOOSE           0x001
  84
  85 #define APM_CPU_PART_POTENZA            0x000
  86
  87 #define CAVIUM_CPU_PART_THUNDERX        0x0A1
  88
  89 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
  90 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
  91 #define MIDR_THUNDERX   MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
  92
  93 #ifndef __ASSEMBLY__
  94
  95 #include <asm/sysreg.h>
  96
  97 #define read_cpuid(reg) ({                                              \
  98         u64 __val;                                                      \
  99         asm("mrs_s      %0, " __stringify(reg) : "=r" (__val));         \
 100         __val;                                                          \
 101 })
 102
 103 /*
 104  * The CPU ID never changes at run time, so we might as well tell the
 105  * compiler that it's constant.  Use this function to read the CPU ID
 106  * rather than directly reading processor_id or read_cpuid() directly.
 107  */
 108 static inline u32 __attribute_const__ read_cpuid_id(void)
 109 {
 110         return read_cpuid(SYS_MIDR_EL1);
 111 }
 112
 113 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
 114 {
 115         return read_cpuid(SYS_MPIDR_EL1);
 116 }
 117
 118 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 119 {
 120         return MIDR_IMPLEMENTOR(read_cpuid_id());
 121 }
 122
 123 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
 124 {
 125         return MIDR_PARTNUM(read_cpuid_id());
 126 }
 127
 128 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
 129 {
 130         return read_cpuid(SYS_CTR_EL0);
 131 }
 132 #endif /* __ASSEMBLY__ */
 133
 134 #endif