arch/arm64/boot/dts/marvell/armada-37xx.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 37xx family of SoCs.
   3  *
   4  * Copyright (C) 2016 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPL or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This file is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This file is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 / {
  50         model = "Marvell Armada 37xx SoC";
  51         compatible = "marvell,armada3700";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 serial0 = &uart0;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 cpu@0 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53", "arm,armv8";
  66                         reg = <0>;
  67                         enable-method = "psci";
  68                 };
  69         };
  70
  71         psci {
  72                 compatible = "arm,psci-0.2";
  73                 method = "smc";
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv8-timer";
  78                 interrupts = <GIC_PPI 13
  79                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  80                              <GIC_PPI 14
  81                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  82                              <GIC_PPI 11
  83                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
  84                              <GIC_PPI 10
  85                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  86         };
  87
  88         soc {
  89                 compatible = "simple-bus";
  90                 #address-cells = <2>;
  91                 #size-cells = <2>;
  92                 ranges;
  93
  94                 internal-regs@d0000000 {
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         compatible = "simple-bus";
  98                         /* 32M internal register @ 0xd000_0000 */
  99                         ranges = <0x0 0x0 0xd0000000 0x2000000>;
 100
 101                         spi0: spi@10600 {
 102                                 compatible = "marvell,armada-3700-spi";
 103                                 #address-cells = <1>;
 104                                 #size-cells = <0>;
 105                                 reg = <0x10600 0xA00>;
 106                                 clocks = <&nb_periph_clk 7>;
 107                                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 108                                 num-cs = <4>;
 109                                 status = "disabled";
 110                         };
 111
 112                         i2c0: i2c@11000 {
 113                                 compatible = "marvell,armada-3700-i2c";
 114                                 reg = <0x11000 0x24>;
 115                                 clocks = <&nb_periph_clk 10>;
 116                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 117                                 mrvl,i2c-fast-mode;
 118                                 status = "disabled";
 119                         };
 120
 121                         i2c1: i2c@11080 {
 122                                 compatible = "marvell,armada-3700-i2c";
 123                                 reg = <0x11080 0x24>;
 124                                 clocks = <&nb_periph_clk 9>;
 125                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 126                                 mrvl,i2c-fast-mode;
 127                                 status = "disabled";
 128                         };
 129
 130                         uart0: serial@12000 {
 131                                 compatible = "marvell,armada-3700-uart";
 132                                 reg = <0x12000 0x400>;
 133                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 134                                 status = "disabled";
 135                         };
 136
 137                         nb_periph_clk: nb-periph-clk@13000 {
 138                                 compatible = "marvell,armada-3700-periph-clock-nb";
 139                                 reg = <0x13000 0x100>;
 140                                 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
 141                                 <&tbg 3>, <&xtalclk>;
 142                                 #clock-cells = <1>;
 143                         };
 144
 145                         sb_periph_clk: sb-periph-clk@18000 {
 146                                 compatible = "marvell,armada-3700-periph-clock-sb";
 147                                 reg = <0x18000 0x100>;
 148                                 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
 149                                 <&tbg 3>, <&xtalclk>;
 150                                 #clock-cells = <1>;
 151                         };
 152
 153                         tbg: tbg@13200 {
 154                                 compatible = "marvell,armada-3700-tbg-clock";
 155                                 reg = <0x13200 0x100>;
 156                                 clocks = <&xtalclk>;
 157                                 #clock-cells = <1>;
 158                         };
 159
 160                         gpio1: gpio@13800 {
 161                                 compatible = "marvell,mvebu-gpio-3700",
 162                                 "syscon", "simple-mfd";
 163                                 reg = <0x13800 0x500>;
 164
 165                                 xtalclk: xtal-clk {
 166                                         compatible = "marvell,armada-3700-xtal-clock";
 167                                         clock-output-names = "xtal";
 168                                         #clock-cells = <0>;
 169                                 };
 170                         };
 171
 172                         eth0: ethernet@30000 {
 173                                    compatible = "marvell,armada-3700-neta";
 174                                    reg = <0x30000 0x4000>;
 175                                    interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 176                                    clocks = <&sb_periph_clk 8>;
 177                                    status = "disabled";
 178                         };
 179
 180                         mdio: mdio@32004 {
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183                                 compatible = "marvell,orion-mdio";
 184                                 reg = <0x32004 0x4>;
 185                         };
 186
 187                         eth1: ethernet@40000 {
 188                                 compatible = "marvell,armada-3700-neta";
 189                                 reg = <0x40000 0x4000>;
 190                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 191                                 clocks = <&sb_periph_clk 7>;
 192                                 status = "disabled";
 193                         };
 194
 195                         usb3: usb@58000 {
 196                                 compatible = "marvell,armada3700-xhci",
 197                                 "generic-xhci";
 198                                 reg = <0x58000 0x4000>;
 199                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 200                                 status = "disabled";
 201                         };
 202
 203                         xor@60900 {
 204                                 compatible = "marvell,armada-3700-xor";
 205                                 reg = <0x60900 0x100
 206                                        0x60b00 0x100>;
 207
 208                                 xor10 {
 209                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 210                                 };
 211                                 xor11 {
 212                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 213                                 };
 214                         };
 215
 216                         sata: sata@e0000 {
 217                                 compatible = "marvell,armada-3700-ahci";
 218                                 reg = <0xe0000 0x2000>;
 219                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 220                                 status = "disabled";
 221                         };
 222
 223                         gic: interrupt-controller@1d00000 {
 224                                 compatible = "arm,gic-v3";
 225                                 #interrupt-cells = <3>;
 226                                 interrupt-controller;
 227                                 reg = <0x1d00000 0x10000>, /* GICD */
 228                                       <0x1d40000 0x40000>; /* GICR */
 229                         };
 230                 };
 231
 232                 pcie0: pcie@d0070000 {
 233                         compatible = "marvell,armada-3700-pcie";
 234                         device_type = "pci";
 235                         status = "disabled";
 236                         reg = <0 0xd0070000 0 0x20000>;
 237                         #address-cells = <3>;
 238                         #size-cells = <2>;
 239                         bus-range = <0x00 0xff>;
 240                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 241                         #interrupt-cells = <1>;
 242                         msi-parent = <&pcie0>;
 243                         msi-controller;
 244                         ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
 245                                   0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
 246                         interrupt-map-mask = <0 0 0 7>;
 247                         interrupt-map = <0 0 0 1 &pcie_intc 0>,
 248                                         <0 0 0 2 &pcie_intc 1>,
 249                                         <0 0 0 3 &pcie_intc 2>,
 250                                         <0 0 0 4 &pcie_intc 3>;
 251                         pcie_intc: interrupt-controller {
 252                                 interrupt-controller;
 253                                 #interrupt-cells = <1>;
 254                         };
 255                 };
 256         };
 257 };