arch/arm64/boot/dts/lg/lg1312.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for lg1312 SoC
   4  *
   5  * Copyright (C) 2016, LG Electronics
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         compatible = "lge,lg1312";
  16         interrupt-parent = <&gic>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a53", "arm,armv8";
  25                         reg = <0x0 0x0>;
  26                         next-level-cache = <&L2_0>;
  27                 };
  28                 cpu1: cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         reg = <0x0 0x1>;
  32                         enable-method = "psci";
  33                         next-level-cache = <&L2_0>;
  34                 };
  35                 cpu2: cpu@2 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53", "arm,armv8";
  38                         reg = <0x0 0x2>;
  39                         enable-method = "psci";
  40                         next-level-cache = <&L2_0>;
  41                 };
  42                 cpu3: cpu@3 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53", "arm,armv8";
  45                         reg = <0x0 0x3>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&L2_0>;
  48                 };
  49                 L2_0: l2-cache0 {
  50                         compatible = "cache";
  51                 };
  52         };
  53
  54         psci {
  55                 compatible  = "arm,psci-0.2", "arm,psci";
  56                 method = "smc";
  57                 cpu_suspend = <0x84000001>;
  58                 cpu_off = <0x84000002>;
  59                 cpu_on = <0x84000003>;
  60         };
  61
  62         gic: interrupt-controller@c0001000 {
  63                 #interrupt-cells = <3>;
  64                 compatible = "arm,gic-400";
  65                 interrupt-controller;
  66                 reg = <0x0 0xc0001000 0x1000>,
  67                       <0x0 0xc0002000 0x2000>,
  68                       <0x0 0xc0004000 0x2000>,
  69                       <0x0 0xc0006000 0x2000>;
  70         };
  71
  72         pmu {
  73                 compatible = "arm,cortex-a53-pmu";
  74                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  77                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
  78                 interrupt-affinity = <&cpu0>,
  79                                      <&cpu1>,
  80                                      <&cpu2>,
  81                                      <&cpu3>;
  82         };
  83
  84         timer {
  85                 compatible = "arm,armv8-timer";
  86                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
  87                               IRQ_TYPE_LEVEL_LOW)>,
  88                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
  89                               IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
  91                               IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
  93                               IRQ_TYPE_LEVEL_LOW)>;
  94         };
  95
  96         clk_bus: clk_bus {
  97                 #clock-cells = <0>;
  98
  99                 compatible = "fixed-clock";
 100                 clock-frequency = <198000000>;
 101                 clock-output-names = "BUSCLK";
 102         };
 103
 104         soc {
 105                 #address-cells = <2>;
 106                 #size-cells = <1>;
 107
 108                 compatible = "simple-bus";
 109                 interrupt-parent = <&gic>;
 110                 ranges;
 111
 112                 eth0: ethernet@c1b00000 {
 113                         compatible = "cdns,gem";
 114                         reg = <0x0 0xc1b00000 0x1000>;
 115                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 116                         clocks = <&clk_bus>, <&clk_bus>;
 117                         clock-names = "hclk", "pclk";
 118                         phy-mode = "rmii";
 119                         /* Filled in by boot */
 120                         mac-address = [ 00 00 00 00 00 00 ];
 121                 };
 122         };
 123
 124         amba {
 125                 #address-cells = <2>;
 126                 #size-cells = <1>;
 127                 #interrupts-cells = <3>;
 128
 129                 compatible = "simple-bus";
 130                 interrupt-parent = <&gic>;
 131                 ranges;
 132
 133                 timers: timer@fd100000 {
 134                         compatible = "arm,sp804";
 135                         reg = <0x0 0xfd100000 0x1000>;
 136                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&clk_bus>;
 138                         clock-names = "apb_pclk";
 139                 };
 140                 wdog: watchdog@fd200000 {
 141                         compatible = "arm,sp805", "arm,primecell";
 142                         reg = <0x0 0xfd200000 0x1000>;
 143                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 144                         clocks = <&clk_bus>;
 145                         clock-names = "apb_pclk";
 146                 };
 147                 uart0: serial@fe000000 {
 148                         compatible = "arm,pl011", "arm,primecell";
 149                         reg = <0x0 0xfe000000 0x1000>;
 150                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 151                         clocks = <&clk_bus>;
 152                         clock-names = "apb_pclk";
 153                         status="disabled";
 154                 };
 155                 uart1: serial@fe100000 {
 156                         compatible = "arm,pl011", "arm,primecell";
 157                         reg = <0x0 0xfe100000 0x1000>;
 158                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         clocks = <&clk_bus>;
 160                         clock-names = "apb_pclk";
 161                         status="disabled";
 162                 };
 163                 uart2: serial@fe200000 {
 164                         compatible = "arm,pl011", "arm,primecell";
 165                         reg = <0x0 0xfe200000 0x1000>;
 166                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 167                         clocks = <&clk_bus>;
 168                         clock-names = "apb_pclk";
 169                         status="disabled";
 170                 };
 171                 spi0: ssp@fe800000 {
 172                         compatible = "arm,pl022", "arm,primecell";
 173                         reg = <0x0 0xfe800000 0x1000>;
 174                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 175                         clocks = <&clk_bus>;
 176                         clock-names = "apb_pclk";
 177                 };
 178                 spi1: ssp@fe900000 {
 179                         compatible = "arm,pl022", "arm,primecell";
 180                         reg = <0x0 0xfe900000 0x1000>;
 181                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 182                         clocks = <&clk_bus>;
 183                         clock-names = "apb_pclk";
 184                 };
 185                 dmac0: dma@c1128000 {
 186                         compatible = "arm,pl330", "arm,primecell";
 187                         reg = <0x0 0xc1128000 0x1000>;
 188                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 189                         clocks = <&clk_bus>;
 190                         clock-names = "apb_pclk";
 191                 };
 192                 gpio0: gpio@fd400000 {
 193                         #gpio-cells = <2>;
 194                         compatible = "arm,pl061", "arm,primecell";
 195                         gpio-controller;
 196                         reg = <0x0 0xfd400000 0x1000>;
 197                         clocks = <&clk_bus>;
 198                         clock-names = "apb_pclk";
 199                         status="disabled";
 200                 };
 201                 gpio1: gpio@fd410000 {
 202                         #gpio-cells = <2>;
 203                         compatible = "arm,pl061", "arm,primecell";
 204                         gpio-controller;
 205                         reg = <0x0 0xfd410000 0x1000>;
 206                         clocks = <&clk_bus>;
 207                         clock-names = "apb_pclk";
 208                         status="disabled";
 209                 };
 210                 gpio2: gpio@fd420000 {
 211                         #gpio-cells = <2>;
 212                         compatible = "arm,pl061", "arm,primecell";
 213                         gpio-controller;
 214                         reg = <0x0 0xfd420000 0x1000>;
 215                         clocks = <&clk_bus>;
 216                         clock-names = "apb_pclk";
 217                         status="disabled";
 218                 };
 219                 gpio3: gpio@fd430000 {
 220                         #gpio-cells = <2>;
 221                         compatible = "arm,pl061", "arm,primecell";
 222                         gpio-controller;
 223                         reg = <0x0 0xfd430000 0x1000>;
 224                         clocks = <&clk_bus>;
 225                         clock-names = "apb_pclk";
 226                 };
 227                 gpio4: gpio@fd440000 {
 228                         #gpio-cells = <2>;
 229                         compatible = "arm,pl061", "arm,primecell";
 230                         gpio-controller;
 231                         reg = <0x0 0xfd440000 0x1000>;
 232                         clocks = <&clk_bus>;
 233                         clock-names = "apb_pclk";
 234                         status="disabled";
 235                 };
 236                 gpio5: gpio@fd450000 {
 237                         #gpio-cells = <2>;
 238                         compatible = "arm,pl061", "arm,primecell";
 239                         gpio-controller;
 240                         reg = <0x0 0xfd450000 0x1000>;
 241                         clocks = <&clk_bus>;
 242                         clock-names = "apb_pclk";
 243                         status="disabled";
 244                 };
 245                 gpio6: gpio@fd460000 {
 246                         #gpio-cells = <2>;
 247                         compatible = "arm,pl061", "arm,primecell";
 248                         gpio-controller;
 249                         reg = <0x0 0xfd460000 0x1000>;
 250                         clocks = <&clk_bus>;
 251                         clock-names = "apb_pclk";
 252                         status="disabled";
 253                 };
 254                 gpio7: gpio@fd470000 {
 255                         #gpio-cells = <2>;
 256                         compatible = "arm,pl061", "arm,primecell";
 257                         gpio-controller;
 258                         reg = <0x0 0xfd470000 0x1000>;
 259                         clocks = <&clk_bus>;
 260                         clock-names = "apb_pclk";
 261                         status="disabled";
 262                 };
 263                 gpio8: gpio@fd480000 {
 264                         #gpio-cells = <2>;
 265                         compatible = "arm,pl061", "arm,primecell";
 266                         gpio-controller;
 267                         reg = <0x0 0xfd480000 0x1000>;
 268                         clocks = <&clk_bus>;
 269                         clock-names = "apb_pclk";
 270                         status="disabled";
 271                 };
 272                 gpio9: gpio@fd490000 {
 273                         #gpio-cells = <2>;
 274                         compatible = "arm,pl061", "arm,primecell";
 275                         gpio-controller;
 276                         reg = <0x0 0xfd490000 0x1000>;
 277                         clocks = <&clk_bus>;
 278                         clock-names = "apb_pclk";
 279                         status="disabled";
 280                 };
 281                 gpio10: gpio@fd4a0000 {
 282                         #gpio-cells = <2>;
 283                         compatible = "arm,pl061", "arm,primecell";
 284                         gpio-controller;
 285                         reg = <0x0 0xfd4a0000 0x1000>;
 286                         clocks = <&clk_bus>;
 287                         clock-names = "apb_pclk";
 288                         status="disabled";
 289                 };
 290                 gpio11: gpio@fd4b0000 {
 291                         #gpio-cells = <2>;
 292                         compatible = "arm,pl061", "arm,primecell";
 293                         gpio-controller;
 294                         reg = <0x0 0xfd4b0000 0x1000>;
 295                         clocks = <&clk_bus>;
 296                         clock-names = "apb_pclk";
 297                 };
 298                 gpio12: gpio@fd4c0000 {
 299                         #gpio-cells = <2>;
 300                         compatible = "arm,pl061", "arm,primecell";
 301                         gpio-controller;
 302                         reg = <0x0 0xfd4c0000 0x1000>;
 303                         clocks = <&clk_bus>;
 304                         clock-names = "apb_pclk";
 305                         status="disabled";
 306                 };
 307                 gpio13: gpio@fd4d0000 {
 308                         #gpio-cells = <2>;
 309                         compatible = "arm,pl061", "arm,primecell";
 310                         gpio-controller;
 311                         reg = <0x0 0xfd4d0000 0x1000>;
 312                         clocks = <&clk_bus>;
 313                         clock-names = "apb_pclk";
 314                         status="disabled";
 315                 };
 316                 gpio14: gpio@fd4e0000 {
 317                         #gpio-cells = <2>;
 318                         compatible = "arm,pl061", "arm,primecell";
 319                         gpio-controller;
 320                         reg = <0x0 0xfd4e0000 0x1000>;
 321                         clocks = <&clk_bus>;
 322                         clock-names = "apb_pclk";
 323                         status="disabled";
 324                 };
 325                 gpio15: gpio@fd4f0000 {
 326                         #gpio-cells = <2>;
 327                         compatible = "arm,pl061", "arm,primecell";
 328                         gpio-controller;
 329                         reg = <0x0 0xfd4f0000 0x1000>;
 330                         clocks = <&clk_bus>;
 331                         clock-names = "apb_pclk";
 332                         status="disabled";
 333                 };
 334                 gpio16: gpio@fd500000 {
 335                         #gpio-cells = <2>;
 336                         compatible = "arm,pl061", "arm,primecell";
 337                         gpio-controller;
 338                         reg = <0x0 0xfd500000 0x1000>;
 339                         clocks = <&clk_bus>;
 340                         clock-names = "apb_pclk";
 341                         status="disabled";
 342                 };
 343                 gpio17: gpio@fd510000 {
 344                         #gpio-cells = <2>;
 345                         compatible = "arm,pl061", "arm,primecell";
 346                         gpio-controller;
 347                         reg = <0x0 0xfd510000 0x1000>;
 348                         clocks = <&clk_bus>;
 349                         clock-names = "apb_pclk";
 350                 };
 351         };
 352 };