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[9610] arm64: dtsi: add dts config define for FM Radio Initialization
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / arch / arm64 / boot / dts / exynos / exynos9610.dtsi
1 /*
2 * SAMSUNG EXYNOS9610 SoC device tree source
3 *
4 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS9610 SoC device nodes are listed in this file.
8 * EXYNOS9610 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <dt-bindings/clock/exynos9610.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "exynos9610-pinctrl.dtsi"
19 #include "exynos9610-display-lcd.dtsi"
20 #include <dt-bindings/thermal/thermal.h>
21 #include <dt-bindings/ufs/ufs.h>
22 #include "exynos9610-sysmmu.dtsi"
23 #include <dt-bindings/soc/samsung/exynos9610-dm.h>
24 #include "exynos9610-pm-domains.dtsi"
25 #include <dt-bindings/soc/samsung/exynos9610-devfreq.h>
26 #include "exynos9610-mfc.dtsi"
27
28 / {
29 compatible = "samsung,armv8", "samsung,exynos9610";
30 interrupt-parent = <&gic>;
31 #address-cells = <2>;
32 #size-cells = <1>;
33
34 aliases {
35 pinctrl0 = &pinctrl_0;
36 pinctrl1 = &pinctrl_1;
37 pinctrl2 = &pinctrl_2;
38 pinctrl3 = &pinctrl_3;
39 pinctrl4 = &pinctrl_4;
40 pinctrl5 = &pinctrl_5;
41 usi0 = &usi_0_shub;
42 usi1 = &usi_0_shub_i2c;
43 usi2 = &usi_0_cmgp;
44 usi3 = &usi_0_cmgp_i2c;
45 usi4 = &usi_1_cmgp;
46 usi5 = &usi_1_cmgp_i2c;
47 usi6 = &usi_2_cmgp;
48 usi7 = &usi_2_cmgp_i2c;
49 usi8 = &usi_3_cmgp;
50 usi9 = &usi_3_cmgp_i2c;
51 usi10 = &usi_4_cmgp;
52 usi11 = &usi_4_cmgp_i2c;
53 usi12 = &usi_peri_uart;
54 usi13 = &usi_peri_cami2c_0;
55 usi14 = &usi_peri_cami2c_1;
56 usi15 = &usi_peri_cami2c_2;
57 usi16 = &usi_peri_cami2c_3;
58 usi17 = &usi_peri_spi_0;
59 usi18 = &usi_peri_spi_1;
60 usi19 = &usi_peri_usi_0;
61 usi20 = &usi_peri_usi_0_i2c;
62 usi21 = &usi_peri_spi_2;
63 hsi2c0 = &hsi2c_0;
64 hsi2c1 = &hsi2c_1;
65 hsi2c2 = &hsi2c_2;
66 hsi2c3 = &hsi2c_3;
67 hsi2c4 = &hsi2c_4;
68 hsi2c5 = &hsi2c_5;
69 hsi2c6 = &hsi2c_6;
70 hsi2c7 = &hsi2c_7;
71 hsi2c8 = &hsi2c_8;
72 hsi2c9 = &hsi2c_9;
73 hsi2c10 = &hsi2c_10;
74 hsi2c11 = &hsi2c_11;
75 hsi2c12 = &hsi2c_12;
76 hsi2c13 = &hsi2c_13;
77 hsi2c14 = &hsi2c_14;
78 hsi2c15 = &hsi2c_15;
79 hsi2c16 = &hsi2c_16;
80 hsi2c17 = &hsi2c_17;
81 spi0 = &spi_0;
82 spi1 = &spi_1;
83 spi2 = &spi_2;
84 spi3 = &spi_3;
85 spi4 = &spi_4;
86 spi5 = &spi_5;
87 spi6 = &spi_6;
88 spi7 = &spi_7;
89 spi8 = &spi_8;
90 spi9 = &spi_9;
91 uart0 = &serial_0;
92 uart1 = &serial_1;
93 uart2 = &serial_2;
94 uart3 = &serial_3;
95 uart4 = &serial_4;
96 uart5 = &serial_5;
97 uart6 = &serial_6;
98 uart7 = &serial_7;
99 fmp0 = &fmp_0;
100 dpp0 = &dpp_0;
101 dpp1 = &dpp_1;
102 dpp2 = &dpp_2;
103 dpp3 = &dpp_3;
104 dsim0 = &dsim_0;
105 decon0 = &decon_f;
106 scaler0 = &scaler_0;
107 mfc0 = &mfc_0;
108 };
109
110 chipid@10000000 {
111 compatible = "samsung,exynos9-chipid";
112 reg = <0x0 0x10000000 0x100>;
113 };
114
115 cpus {
116 #address-cells = <2>;
117 #size-cells = <0>;
118
119 cpu-map {
120 cluster0 {
121 coregroup0 {
122 core0 {
123 cpu = <&cpu0>;
124 };
125 core1 {
126 cpu = <&cpu1>;
127 };
128 core2 {
129 cpu = <&cpu2>;
130 };
131 core3 {
132 cpu = <&cpu3>;
133 };
134 };
135 };
136
137 cluster1 {
138 coregroup0 {
139 core0 {
140 cpu = <&cpu4>;
141 };
142 core1 {
143 cpu = <&cpu5>;
144 };
145 core2 {
146 cpu = <&cpu6>;
147 };
148 core3 {
149 cpu = <&cpu7>;
150 };
151 };
152 };
153
154 };
155
156 cpu0: cpu@100 {
157 device_type = "cpu";
158 compatible = "arm,cortex-a53", "arm,armv8";
159 reg = <0x0 0x0>;
160 enable-method = "psci";
161 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
162 sched-energy-data = <&A53_ENERGY>;
163 };
164 cpu1: cpu@101 {
165 device_type = "cpu";
166 compatible = "arm,cortex-a53", "arm,armv8";
167 reg = <0x0 0x1>;
168 enable-method = "psci";
169 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
170 sched-energy-data = <&A53_ENERGY>;
171 };
172 cpu2: cpu@102 {
173 device_type = "cpu";
174 compatible = "arm,cortex-a53", "arm,armv8";
175 reg = <0x0 0x2>;
176 enable-method = "psci";
177 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
178 sched-energy-data = <&A53_ENERGY>;
179 };
180 cpu3: cpu@103 {
181 device_type = "cpu";
182 compatible = "arm,cortex-a53", "arm,armv8";
183 reg = <0x0 0x3>;
184 enable-method = "psci";
185 cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
186 sched-energy-data = <&A53_ENERGY>;
187 };
188 cpu4: cpu@0 {
189 device_type = "cpu";
190 compatible = "arm,cortex-a73", "arm,armv8";
191 reg = <0x0 0x100>;
192 enable-method = "psci";
193 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
194 sched-energy-data = <&A73_ENERGY>;
195 };
196 cpu5: cpu@1 {
197 device_type = "cpu";
198 compatible = "arm,cortex-a73", "arm,armv8";
199 reg = <0x0 0x101>;
200 enable-method = "psci";
201 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
202 sched-energy-data = <&A73_ENERGY>;
203 };
204 cpu6: cpu@2 {
205 device_type = "cpu";
206 compatible = "arm,cortex-a73", "arm,armv8";
207 reg = <0x0 0x102>;
208 enable-method = "psci";
209 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
210 sched-energy-data = <&A73_ENERGY>;
211 };
212 cpu7: cpu@3 {
213 device_type = "cpu";
214 compatible = "arm,cortex-a73", "arm,armv8";
215 reg = <0x0 0x103>;
216 enable-method = "psci";
217 cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
218 sched-energy-data = <&A73_ENERGY>;
219 };
220
221 idle-states {
222 entry-method = "arm,psci";
223
224 BOOTCL_CPU_SLEEP: bootcl-cpu-sleep {
225 idle-state-name = "c2";
226 compatible = "exynos,idle-state";
227 arm,psci-suspend-param = <0x0010000>;
228 entry-latency-us = <35>;
229 exit-latency-us = <90>;
230 min-residency-us = <750>;
231 status = "okay";
232 };
233
234 NONBOOTCL_CPU_SLEEP: nobootcl-cpu-sleep {
235 idle-state-name = "c2";
236 compatible = "exynos,idle-state";
237 arm,psci-suspend-param = <0x0010000>;
238 entry-latency-us = <30>;
239 exit-latency-us = <75>;
240 min-residency-us = <2000>;
241 status = "okay";
242 };
243 };
244
245 energy-data {
246 A53_ENERGY: a53-energy {
247 capacity-mips = <230>;
248 power-coefficient = <450>;
249 };
250 A73_ENERGY: a73-energy {
251 capacity-mips = <480>;
252 power-coefficient = <870>;
253 };
254 };
255
256 ems {
257 /* Ontime Migration */
258 ontime {
259 /* between little and middle */
260 step0 {
261 up-threshold = <215>;
262 down-threshold = <170>;
263 min-residency-us = <8192>;
264 };
265 };
266
267 /* Load Balance Trigger */
268 #define DEFAULT_RATIO 80
269 lbt {
270 overutil-level0 {
271 cpus = "0-3",
272 "4-7";
273 ratio = <35>,
274 <50>;
275 };
276 overutil-level1 {
277 cpus = "0-7";
278 ratio = <DEFAULT_RATIO>;
279 };
280 };
281 };
282 };
283
284 psci {
285 compatible = "arm,psci";
286 method = "smc";
287 cpu_suspend = <0xC4000001>;
288 cpu_off = <0x84000002>;
289 cpu_on = <0xC4000003>;
290 };
291
292 cpupm {
293 #define POWERMODE_TYPE_CLUSTER 0
294 #define POWERMODE_TYPE_SYSTEM 1
295
296 cpd_cl0 {
297 device_type = "cpupm";
298 target-residency = <10000>;
299 psci-index = <128>;
300 type = <POWERMODE_TYPE_CLUSTER>;
301 siblings = "0-3";
302 };
303
304 cpd_cl1 {
305 device_type = "cpupm";
306 target-residency = <3000>;
307 psci-index = <128>;
308 type = <POWERMODE_TYPE_CLUSTER>;
309 siblings = "4-7";
310 entry-allowed = "4-7";
311 };
312
313 sicd {
314 device_type = "cpupm";
315 target-residency = <3000>; /* us */
316 psci-index = <256>;
317 type = <POWERMODE_TYPE_SYSTEM>;
318 siblings = "0-7";
319 entry-allowed = "0-3";
320 system-idle;
321 };
322
323 idle-ip {
324 idle-ip-list =
325 "13970000.pwm", /* [ 0] pwm */
326 "11c30000.adc", /* [ 1] adc */
327 "110c0000.hsi2c", /* [ 2] hsi2c_0 */
328 "110d0000.hsi2c", /* [ 3] hsi2c_1 */
329 "11d00000.hsi2c", /* [ 4] hsi2c_2 */
330 "11d10000.hsi2c", /* [ 5] hsi2c_3 */
331 "11d20000.hsi2c", /* [ 6] hsi2c_4 */
332 "11d30000.hsi2c", /* [ 7] hsi2c_5 */
333 "11d40000.hsi2c", /* [ 8] hsi2c_6 */
334 "11d50000.hsi2c", /* [ 9] hsi2c_7 */
335 "11d60000.hsi2c", /* [10] hsi2c_8 */
336 "11d70000.hsi2c", /* [11] hsi2c_9 */
337 "11d80000.hsi2c", /* [12] hsi2c_10 */
338 "11d90000.hsi2c", /* [13] hsi2c_11 */
339 "138a0000.hsi2c", /* [14] hsi2c_12 */
340 "138b0000.hsi2c", /* [15] hsi2c_13 */
341 "138c0000.hsi2c", /* [16] hsi2c_14 */
342 "138d0000.hsi2c", /* [17] hsi2c_15 */
343 "13920000.hsi2c", /* [18] hsi2c_16 */
344 "13930000.hsi2c", /* [19] hsi2c_17 */
345 "13830000.i2c", /* [20] i2c_0 */
346 "13840000.i2c", /* [21] i2c_1 */
347 "13850000.i2c", /* [22] i2c_2 */
348 "13860000.i2c", /* [23] i2c_3 */
349 "13870000.i2c", /* [24] i2c_4 */
350 "13880000.i2c", /* [25] i2c_5 */
351 "13890000.i2c", /* [26] i2c_6 */
352 "110c0000.spi", /* [27] spi_0 */
353 "11d00000.spi", /* [28] spi_1 */
354 "11d20000.spi", /* [29] spi_2 */
355 "11d40000.spi", /* [30] spi_3 */
356 "11d60000.spi", /* [31] spi_4 */
357 "11d80000.spi", /* [32] spi_5 */
358 "13900000.spi", /* [33] spi_6 */
359 "13910000.spi", /* [34] spi_7 */
360 "13920000.spi", /* [35] spi_8 */
361 "13940000.spi", /* [36] spi_9 */
362 "13520000.ufs", /* [37] ufs */
363 "13500000.dwmmc0", /* [38] dwmmc0 */
364 "13550000.dwmmc2", /* [39] dwmmc2 */
365 "13200000.usb", /* [40] usb */
366 "pd-cam", /* [41] pd-cam */
367 "pd-isp", /* [42] pd-isp */
368 "pd-vipx1", /* [43] pd-vipx1 */
369 "pd-vipx2", /* [44] pd-vipx2 */
370 "pd-g2d", /* [45] pd-g2d */
371 "pd-g3d", /* [46] pd-g3d */
372 "pd-dispaud", /* [47] pd-dispaud */
373 "pd-mfc", /* [48] pd-mfc */
374 "148e0000.dsim"; /* [49] dsim_0 */
375
376 fix-idle-ip = "acpm_dvfs";
377 fix-idle-ip-index = <96>;
378
379 idle-ip-mask =
380 <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>,
381 <10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
382 <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>,
383 <30>, <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>,
384 <40>, <41>, <42>, <43>, <44>, <45>, <46>, <48>, <49>, <96>;
385 };
386 };
387
388 exynos-pm {
389 compatible = "samsung,exynos-pm";
390 reg = <0x0 0x11850000 0x1000>,
391 <0x0 0x12301200 0x100>;
392 reg-names = "gpio_alive_base",
393 "gicd_ispendrn_base";
394 num-eint = <24>;
395 num-gic = <16>;
396 suspend_mode_idx = <8>; /* SYS_SLEEP */
397 suspend_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */
398 cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */
399 cp_call_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */
400 usbl2_suspend_available = <1>;
401 usbl2_suspend_mode_idx = <12>; /* SYS_SLEEP_USB_ON */
402 extra_wakeup_stat = <0x60c>;
403 conn_req_offset = <0x00c0>; /* PMU_ALIVE__CONNECT_SLEEP_STATUS */
404 };
405
406 exynos-powermode {
407 wakeup-masks {
408 wakeup-mask {
409 /*
410 * wakeup_mask configuration
411 * SICD SICD_CPD AFTR STOP
412 * LPD LPA ALPA DSTOP
413 * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO
414 * SLEEP_USB_L2
415 */
416 wakeup-mask {
417 mask = <0x40000000>, <0x0>, <0x0>, <0x0>,
418 <0x0>, <0x0>, <0x0>, <0x0>,
419 <0xD00D7E7E>, <0x500D7E7E>, <0x500D7E7E>, <0x0>,
420 <0xD00D7E7E>;
421 mask-offset = <0x610>;
422 stat-offset = <0x600>;
423 };
424 wakeup-mask2 {
425 mask = <0x0>, <0x0>, <0x0>, <0x0>,
426 <0x0>, <0x0>, <0x0>, <0x0>,
427 <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
428 <0xFFFF00FF>;
429 mask-offset = <0x614>;
430 stat-offset = <0x604>;
431 };
432 wakeup-mask3 {
433 mask = <0x0>, <0x0>, <0x0>, <0x0>,
434 <0x0>, <0x0>, <0x0>, <0x0>,
435 <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>,
436 <0xFFFF00FF>;
437 mask-offset = <0x618>;
438 stat-offset = <0x608>;
439 };
440 wakeup-mask4 {
441 mask = <0x0>, <0x0>, <0x0>, <0x0>,
442 <0x0>, <0x0>, <0x0>, <0x0>,
443 <0x0>, <0x0>, <0x0>, <0x0>,
444 <0x0>;
445 mask-offset = <0x61c>;
446 stat-offset = <0x610>;
447 };
448 };
449 };
450 };
451
452 gic:interrupt-controller@12300000 {
453 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
454 #interrupt-cells = <3>;
455 #address-cells = <0>;
456 interrupt-controller;
457 reg = <0x0 0x12301000 0x1000>,
458 <0x0 0x12302000 0x1000>,
459 <0x0 0x12304000 0x2000>,
460 <0x0 0x12306000 0x2000>;
461 interrupts = <1 9 0xf04>;
462 };
463
464 timer {
465 compatible = "arm,armv8-timer";
466 interrupts = <GIC_PPI 13
467 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
468 <GIC_PPI 14
469 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
470 <GIC_PPI 11
471 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
472 <GIC_PPI 10
473 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
474 clock-frequency = <26000000>;
475 use-clocksource-only;
476 use-physical-timer;
477 };
478
479 clock: clock-controller@0x12100000 {
480 compatible = "samsung,exynos9610-clock";
481 reg = <0x0 0x12100000 0x8000>;
482 #clock-cells = <1>;
483 acpm-ipc-channel = <0>;
484 };
485
486 mct@10040000 {
487 compatible = "samsung,exynos4210-mct";
488 reg = <0x0 0x10040000 0x800>;
489 interrupt-controller;
490 #interrupt-cells = <1>;
491 interrupt-parent = <&mct_map>;
492 interrupts = <0>, <1>, <2>, <3>,
493 <4>, <5>, <6>, <7>,
494 <8>, <9>, <10>, <11>;
495 clocks = <&clock OSCCLK>, <&clock GATE_MCT_QCH>;
496 clock-names = "fin_pll", "mct";
497 use-clockevent-only;
498
499 mct_map: mct-map {
500 #interrupt-cells = <1>;
501 #address-cells = <0>;
502 #size-cells = <0>;
503 interrupt-map = <0 &gic 0 234 0>,
504 <1 &gic 0 235 0>,
505 <2 &gic 0 236 0>,
506 <3 &gic 0 237 0>,
507 <4 &gic 0 238 0>,
508 <5 &gic 0 239 0>,
509 <6 &gic 0 240 0>,
510 <7 &gic 0 241 0>,
511 <8 &gic 0 242 0>,
512 <9 &gic 0 243 0>,
513 <10 &gic 0 244 0>,
514 <11 &gic 0 245 0>;
515 };
516 };
517
518 speedy@11a10000 {
519 compatible = "samsung,exynos-speedy";
520 reg = <0x0 0x11a10000 0x2000>;
521 interrupts = <0 37 0>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&speedy_bus>;
526 status = "disabled";
527 };
528
529 acpm {
530 compatible = "samsung,exynos-acpm";
531 #address-cells = <2>;
532 #size-cells = <1>;
533 acpm-ipc-channel = <4>;
534 fvmap_offset = <0x6000>;
535 reg = <0x0 0x11820000 0x1000>; /* TIMER_APM */
536 reg-names = "timer_apm";
537 peritimer-cnt = <0xFFFF>;
538 };
539
540 acpm_ipc {
541 compatible = "samsung,exynos-acpm-ipc";
542 #address-cells = <2>;
543 #size-cells = <1>;
544 interrupts = <0 38 0>; /* AP2APM MAILBOX SPI NUM*/
545 reg = <0x0 0x11900000 0x1000>, /* AP2APM MAILBOX */
546 <0x0 0x2039000 0x15000>; /* APM SRAM */
547 initdata-base = <0x6F00>;
548 num-timestamps = <32>;
549 debug-log-level = <0>;
550 logging-period = <500>;
551 dump-base = <0x203C000>;
552 dump-size = <0x12000>; /* 72KB */
553 };
554
555 acpm_dvfs {
556 compatible = "samsung,exynos-acpm-dvfs";
557 acpm-ipc-channel = <5>;
558 };
559
560 /* ALIVE */
561 pinctrl_0: pinctrl@11850000 {
562 compatible = "samsung,exynos9610-pinctrl";
563 reg = <0x0 0x11850000 0x1000>;
564 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
565 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
566 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
567 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
568 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
569 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
570
571 wakeup-interrupt-controller {
572 compatible = "samsung,exynos7-wakeup-eint";
573 };
574 };
575
576 /* CMGP */
577 pinctrl_1: pinctrl@11C20000{
578 compatible = "samsung,exynos9610-pinctrl";
579 reg = <0x0 0x11C20000 0x1000>;
580 interrupts = <0 142 0>, <0 143 0>, <0 144 0>, <0 145 0>,
581 <0 158 0>, <0 159 0>, <0 160 0>, <0 161 0>,
582 <0 162 0>, <0 170 0>, <0 171 0>, <0 172 0>,
583 <0 173 0>, <0 174 0>, <0 185 0>, <0 196 0>,
584 <0 197 0>, <0 226 0>, <0 227 0>, <0 228 0>,
585 <0 269 0>, <0 270 0>, <0 272 0>, <0 278 0>,
586 <0 318 0>, <0 319 0>;
587
588 wakeup-interrupt-controller {
589 compatible = "samsung,exynos7-wakeup-eint";
590 };
591 };
592
593 /* DISPAUD */
594 pinctrl_2: pinctrl@14A60000{
595 compatible = "samsung,exynos9610-pinctrl";
596 reg = <0x0 0x14A60000 0x1000>;
597 };
598
599 /* FSYS */
600 pinctrl_3: pinctrl@13490000 {
601 compatible = "samsung,exynos9610-pinctrl";
602 reg = <0x0 0x13490000 0x1000>;
603 interrupts = <0 150 0>;
604 };
605
606 /* TOP */
607 pinctrl_4: pinctrl@139B0000 {
608 compatible = "samsung,exynos9610-pinctrl";
609 reg = <0x0 0x139B0000 0x1000>;
610 interrupts = <0 266 0>;
611 };
612
613 /* SHUB */
614 pinctrl_5: pinctrl@11080000{
615 compatible = "samsung,exynos9610-pinctrl";
616 reg = <0x0 0x11080000 0x1000>;
617 interrupts = <0 116 0>;
618 };
619
620 /* USI_SHUB_0 */
621 usi_0_shub: usi@11013000 {
622 compatible = "samsung,exynos-usi-v2";
623 reg = <0x0 0x11013000 0x4>;
624 /* usi_v2_mode = "i2c" or "spi" or "uart" */
625 status = "disabled";
626 };
627
628 /* USI_SHUB_0_I2C */
629 usi_0_shub_i2c: usi@11013004 {
630 compatible = "samsung,exynos-usi-v2";
631 reg = <0x0 0x11013004 0x4>;
632 /* usi_v2_mode = "i2c" or "spi" or "uart" */
633 status = "disabled";
634 };
635
636 /* USI_0_CMGP */
637 usi_0_cmgp: usi@11C12000 {
638 compatible = "samsung,exynos-usi-v2";
639 reg = <0x0 0x11C12000 0x4>;
640 /* usi_v2_mode = "i2c" or "spi" or "uart" */
641 status = "disabled";
642 };
643
644 /* USI_0_CMGP_I2C */
645 usi_0_cmgp_i2c: usi@11C12004 {
646 compatible = "samsung,exynos-usi-v2";
647 reg = <0x0 0x11C12004 0x4>;
648 /* usi_v2_mode = "i2c" or "spi" or "uart" */
649 status = "disabled";
650 };
651
652 /* USI_1_CMGP */
653 usi_1_cmgp: usi@11C12010 {
654 compatible = "samsung,exynos-usi-v2";
655 reg = <0x0 0x11C12010 0x4>;
656 /* usi_v2_mode = "i2c" or "spi" or "uart" */
657 status = "disabled";
658 };
659
660 /* USI_1_CMGP_I2C */
661 usi_1_cmgp_i2c: usi@11C12014 {
662 compatible = "samsung,exynos-usi-v2";
663 reg = <0x0 0x11C12014 0x4>;
664 /* usi_v2_mode = "i2c" or "spi" or "uart" */
665 status = "disabled";
666 };
667
668 /* USI_2_CMGP */
669 usi_2_cmgp: usi@11C12020 {
670 compatible = "samsung,exynos-usi-v2";
671 reg = <0x0 0x11C12020 0x4>;
672 /* usi_v2_mode = "i2c" or "spi" or "uart" */
673 status = "disabled";
674 };
675
676 /* USI_2_CMGP_I2C */
677 usi_2_cmgp_i2c: usi@11C12024 {
678 compatible = "samsung,exynos-usi-v2";
679 reg = <0x0 0x11C12024 0x4>;
680 /* usi_v2_mode = "i2c" or "spi" or "uart" */
681 status = "disabled";
682 };
683
684 /* USI_3_CMGP */
685 usi_3_cmgp: usi@11C12030 {
686 compatible = "samsung,exynos-usi-v2";
687 reg = <0x0 0x11C12030 0x4>;
688 /* usi_v2_mode = "i2c" or "spi" or "uart" */
689 status = "disabled";
690 };
691
692 /* USI_3_CMGP_I2C */
693 usi_3_cmgp_i2c: usi@11C12034 {
694 compatible = "samsung,exynos-usi-v2";
695 reg = <0x0 0x11C12034 0x4>;
696 /* usi_v2_mode = "i2c" or "spi" or "uart" */
697 status = "disabled";
698 };
699
700 /* USI_4_CMGP */
701 usi_4_cmgp: usi@11C12040 {
702 compatible = "samsung,exynos-usi-v2";
703 reg = <0x0 0x11C12040 0x4>;
704 /* usi_v2_mode = "i2c" or "spi" or "uart" */
705 status = "disabled";
706 };
707
708 /* USI_4_CMGP_I2C */
709 usi_4_cmgp_i2c: usi@11C12044 {
710 compatible = "samsung,exynos-usi-v2";
711 reg = <0x0 0x11C12044 0x4>;
712 /* usi_v2_mode = "i2c" or "spi" or "uart" */
713 status = "disabled";
714 };
715
716 /* USI_PERI_UART */
717 usi_peri_uart: usi@10011010 {
718 compatible = "samsung,exynos-usi-v2";
719 reg = <0x0 0x10011010 0x4>;
720 /* usi_v2_mode = "i2c" or "spi" or "uart" */
721 status = "disabled";
722 };
723
724 /* USI_PERI_CAMI2C_0 */
725 usi_peri_cami2c_0: usi@10011020 {
726 compatible = "samsung,exynos-usi-v2";
727 reg = <0x0 0x10011020 0x4>;
728 /* usi_v2_mode = "i2c" or "spi" or "uart" */
729 status = "disabled";
730 };
731
732 /* USI_PERI_CAMI2C_1 */
733 usi_peri_cami2c_1: usi@10011024 {
734 compatible = "samsung,exynos-usi-v2";
735 reg = <0x0 0x10011024 0x4>;
736 /* usi_v2_mode = "i2c" or "spi" or "uart" */
737 status = "disabled";
738 };
739
740 /* USI_PERI_CAMI2C_2 */
741 usi_peri_cami2c_2: usi@10011028 {
742 compatible = "samsung,exynos-usi-v2";
743 reg = <0x0 0x10011028 0x4>;
744 /* usi_v2_mode = "i2c" or "spi" or "uart" */
745 status = "disabled";
746 };
747
748 /* USI_PERI_CAMI2C_3 */
749 usi_peri_cami2c_3: usi@1001102C {
750 compatible = "samsung,exynos-usi-v2";
751 reg = <0x0 0x1001102C 0x4>;
752 /* usi_v2_mode = "i2c" or "spi" or "uart" */
753 status = "disabled";
754 };
755
756 /* USI_PERI_SPI_0 */
757 usi_peri_spi_0: usi@10011030 {
758 compatible = "samsung,exynos-usi-v2";
759 reg = <0x0 0x10011030 0x4>;
760 /* usi_v2_mode = "i2c" or "spi" or "uart" */
761 status = "disabled";
762 };
763
764 /* USI_PERI_SPI_1 */
765 usi_peri_spi_1: usi@10011034 {
766 compatible = "samsung,exynos-usi-v2";
767 reg = <0x0 0x10011034 0x4>;
768 /* usi_v2_mode = "i2c" or "spi" or "uart" */
769 status = "disabled";
770 };
771
772 /* USI_PERI_USI_0 */
773 usi_peri_usi_0: usi@1001103C {
774 compatible = "samsung,exynos-usi-v2";
775 reg = <0x0 0x1001103C 0x4>;
776 /* usi_v2_mode = "i2c" or "spi" or "uart" */
777 status = "disabled";
778 };
779
780 /* USI_PERI_USI_0_I2C */
781 usi_peri_usi_0_i2c: usi@10011040 {
782 compatible = "samsung,exynos-usi-v2";
783 reg = <0x0 0x10011040 0x4>;
784 /* usi_v2_mode = "i2c" or "spi" or "uart" */
785 status = "disabled";
786 };
787
788 /* USI_PERI_SPI_2 */
789 usi_peri_spi_2: usi@10011038 {
790 compatible = "samsung,exynos-usi-v2";
791 reg = <0x0 0x10011038 0x4>;
792 /* usi_v2_mode = "i2c" or "spi" or "uart" */
793 status = "disabled";
794 };
795
796 /* USI_0_SHUB */
797 hsi2c_0: hsi2c@110C0000 {
798 compatible = "samsung,exynos5-hsi2c";
799 samsung,check-transdone-int;
800 default-clk = <200000000>;
801 reg = <0x0 0x110C0000 0x1000>;
802 interrupts = <0 112 0>;
803 #address-cells = <1>;
804 #size-cells = <0>;
805 pinctrl-names = "default";
806 pinctrl-0 = <&hsi2c0_bus>;
807 clocks = <&clock MUX_SHUB_USI00>, <&clock GATE_USI_SHUB00_QCH>;
808 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
809 samsung,scl-clk-stretching;
810 samsung,usi-i2c-v2;
811 gpio_scl= <&gph0 0 0x1>;
812 gpio_sda= <&gph0 1 0x1>;
813 status = "disabled";
814 };
815
816 /* USI_0_SHUB_I2C */
817 hsi2c_1: hsi2c@110D0000 {
818 compatible = "samsung,exynos5-hsi2c";
819 samsung,check-transdone-int;
820 default-clk = <200000000>;
821 reg = <0x0 0x110D0000 0x1000>;
822 interrupts = <0 117 0>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 pinctrl-names = "default";
826 pinctrl-0 = <&hsi2c1_bus>;
827 clocks = <&clock MUX_SHUB_I2C>, <&clock GATE_I2C_SHUB00_QCH>;
828 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
829 samsung,scl-clk-stretching;
830 samsung,usi-i2c-v2;
831 gpio_scl= <&gph0 2 0x1>;
832 gpio_sda= <&gph0 3 0x1>;
833 status = "disabled";
834 };
835
836 /* USI_0_CMGP */
837 hsi2c_2: hsi2c@11D00000 {
838 compatible = "samsung,exynos5-hsi2c";
839 samsung,check-transdone-int;
840 default-clk = <200000000>;
841 reg = <0x0 0x11D00000 0x1000>;
842 interrupts = <0 311 0>;
843 #address-cells = <1>;
844 #size-cells = <0>;
845 pinctrl-names = "default";
846 pinctrl-0 = <&hsi2c2_bus>;
847 clocks = <&clock CMGP00_USI>, <&clock GATE_USI_CMGP00_QCH>;
848 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
849 samsung,scl-clk-stretching;
850 samsung,usi-i2c-v2;
851 gpio_scl= <&gpm0 0 0x1>;
852 gpio_sda= <&gpm1 0 0x1>;
853 status = "disabled";
854 };
855
856 /* USI_0_CMGP_I2C */
857 hsi2c_3: hsi2c@11D10000 {
858 compatible = "samsung,exynos5-hsi2c";
859 samsung,check-transdone-int;
860 default-clk = <200000000>;
861 reg = <0x0 0x11D10000 0x1000>;
862 interrupts = <0 273 0>;
863 #address-cells = <1>;
864 #size-cells = <0>;
865 pinctrl-names = "default";
866 pinctrl-0 = <&hsi2c3_bus>;
867 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP00_QCH>;
868 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
869 samsung,scl-clk-stretching;
870 samsung,usi-i2c-v2;
871 gpio_scl= <&gpm2 0 0x1>;
872 gpio_sda= <&gpm3 0 0x1>;
873 status = "disabled";
874 };
875
876 /* USI_1_CMGP */
877 hsi2c_4: hsi2c@11D20000 {
878 compatible = "samsung,exynos5-hsi2c";
879 samsung,check-transdone-int;
880 default-clk = <200000000>;
881 reg = <0x0 0x11D20000 0x1000>;
882 interrupts = <0 312 0>;
883 #address-cells = <1>;
884 #size-cells = <0>;
885 pinctrl-names = "default";
886 pinctrl-0 = <&hsi2c4_bus>;
887 clocks = <&clock CMGP01_USI>, <&clock GATE_USI_CMGP01_QCH>;
888 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
889 samsung,scl-clk-stretching;
890 samsung,usi-i2c-v2;
891 gpio_scl= <&gpm4 0 0x1>;
892 gpio_sda= <&gpm5 0 0x1>;
893 status = "disabled";
894 };
895
896 /* USI_1_CMGP_I2C */
897 hsi2c_5: hsi2c@11D30000 {
898 compatible = "samsung,exynos5-hsi2c";
899 samsung,check-transdone-int;
900 default-clk = <200000000>;
901 reg = <0x0 0x11D30000 0x1000>;
902 interrupts = <0 274 0>;
903 #address-cells = <1>;
904 #size-cells = <0>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&hsi2c5_bus>;
907 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP01_QCH>;
908 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
909 samsung,scl-clk-stretching;
910 samsung,usi-i2c-v2;
911 gpio_scl= <&gpm6 0 0x1>;
912 gpio_sda= <&gpm7 0 0x1>;
913 status = "disabled";
914 };
915
916 /* USI_2_CMGP */
917 hsi2c_6: hsi2c@11D40000 {
918 compatible = "samsung,exynos5-hsi2c";
919 samsung,check-transdone-int;
920 default-clk = <200000000>;
921 reg = <0x0 0x11D40000 0x1000>;
922 interrupts = <0 313 0>;
923 #address-cells = <1>;
924 #size-cells = <0>;
925 pinctrl-names = "default";
926 pinctrl-0 = <&hsi2c6_bus>;
927 clocks = <&clock CMGP02_USI>, <&clock GATE_USI_CMGP02_QCH>;
928 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
929 samsung,scl-clk-stretching;
930 samsung,usi-i2c-v2;
931 gpio_scl= <&gpm8 0 0x1>;
932 gpio_sda= <&gpm9 0 0x1>;
933 status = "disabled";
934 };
935
936 /* USI_2_CMGP_I2C */
937 hsi2c_7: hsi2c@11D50000 {
938 compatible = "samsung,exynos5-hsi2c";
939 samsung,check-transdone-int;
940 default-clk = <200000000>;
941 reg = <0x0 0x11D50000 0x1000>;
942 interrupts = <0 275 0>;
943 #address-cells = <1>;
944 #size-cells = <0>;
945 pinctrl-names = "default";
946 pinctrl-0 = <&hsi2c7_bus>;
947 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP02_QCH>;
948 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
949 samsung,scl-clk-stretching;
950 samsung,usi-i2c-v2;
951 gpio_scl= <&gpm10 0 0x1>;
952 gpio_sda= <&gpm11 0 0x1>;
953 status = "disabled";
954 };
955
956 /* USI_3_CMGP */
957 hsi2c_8: hsi2c@11D60000 {
958 compatible = "samsung,exynos5-hsi2c";
959 samsung,check-transdone-int;
960 default-clk = <200000000>;
961 reg = <0x0 0x11D60000 0x1000>;
962 interrupts = <0 314 0>;
963 #address-cells = <1>;
964 #size-cells = <0>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&hsi2c8_bus>;
967 clocks = <&clock CMGP03_USI>, <&clock GATE_USI_CMGP03_QCH>;
968 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
969 samsung,scl-clk-stretching;
970 samsung,usi-i2c-v2;
971 gpio_scl= <&gpm12 0 0x1>;
972 gpio_sda= <&gpm13 0 0x1>;
973 status = "disabled";
974 };
975
976 /* USI_3_CMGP_I2C */
977 hsi2c_9: hsi2c@11D70000 {
978 compatible = "samsung,exynos5-hsi2c";
979 samsung,check-transdone-int;
980 default-clk = <200000000>;
981 reg = <0x0 0x11D70000 0x1000>;
982 interrupts = <0 276 0>;
983 #address-cells = <1>;
984 #size-cells = <0>;
985 pinctrl-names = "default";
986 pinctrl-0 = <&hsi2c9_bus>;
987 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP03_QCH>;
988 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
989 samsung,scl-clk-stretching;
990 samsung,usi-i2c-v2;
991 gpio_scl= <&gpm14 0 0x1>;
992 gpio_sda= <&gpm15 0 0x1>;
993 status = "disabled";
994 };
995
996 /* USI_4_CMGP */
997 hsi2c_10: hsi2c@11D80000 {
998 compatible = "samsung,exynos5-hsi2c";
999 samsung,check-transdone-int;
1000 default-clk = <200000000>;
1001 reg = <0x0 0x11D80000 0x1000>;
1002 interrupts = <0 315 0>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&hsi2c10_bus>;
1007 clocks = <&clock CMGP04_USI>, <&clock GATE_USI_CMGP04_QCH>;
1008 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1009 samsung,scl-clk-stretching;
1010 samsung,usi-i2c-v2;
1011 gpio_scl= <&gpm16 0 0x1>;
1012 gpio_sda= <&gpm17 0 0x1>;
1013 status = "disabled";
1014 };
1015
1016 /* USI_4_CMGP_I2C */
1017 hsi2c_11: hsi2c@11D90000 {
1018 compatible = "samsung,exynos5-hsi2c";
1019 samsung,check-transdone-int;
1020 default-clk = <200000000>;
1021 reg = <0x0 0x11D90000 0x1000>;
1022 interrupts = <0 277 0>;
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&hsi2c11_bus>;
1027 clocks = <&clock CMGP_I2C>, <&clock GATE_I2C_CMGP04_QCH>;
1028 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1029 samsung,scl-clk-stretching;
1030 samsung,usi-i2c-v2;
1031 gpio_scl= <&gpm18 0 0x1>;
1032 gpio_sda= <&gpm19 0 0x1>;
1033 status = "disabled";
1034 };
1035
1036 /* USI_PERI_CAMI2C_0 */
1037 hsi2c_12: hsi2c@138A0000 {
1038 compatible = "samsung,exynos5-hsi2c";
1039 samsung,check-transdone-int;
1040 default-clk = <200000000>;
1041 reg = <0x0 0x138A0000 0x1000>;
1042 interrupts = <0 257 0>;
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&hsi2c12_bus>;
1047 clocks = <&clock I2C>, <&clock GATE_CAMI2C_0_QCH>;
1048 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1049 samsung,scl-clk-stretching;
1050 samsung,usi-i2c-v2;
1051 gpio_scl= <&gpc0 1 0x1>;
1052 gpio_sda= <&gpc0 0 0x1>;
1053 status = "disabled";
1054 };
1055
1056 /* USI_PERI_CAMI2C_1 */
1057 hsi2c_13: hsi2c@138B0000 {
1058 compatible = "samsung,exynos5-hsi2c";
1059 samsung,check-transdone-int;
1060 default-clk = <200000000>;
1061 reg = <0x0 0x138B0000 0x1000>;
1062 interrupts = <0 258 0>;
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 pinctrl-names = "default";
1066 pinctrl-0 = <&hsi2c13_bus>;
1067 clocks = <&clock I2C>, <&clock GATE_CAMI2C_1_QCH>;
1068 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1069 samsung,scl-clk-stretching;
1070 samsung,usi-i2c-v2;
1071 gpio_scl= <&gpc0 3 0x1>;
1072 gpio_sda= <&gpc0 2 0x1>;
1073 status = "disabled";
1074 };
1075
1076 /* USI_PERI_CAMI2C_2 */
1077 hsi2c_14: hsi2c@138C0000 {
1078 compatible = "samsung,exynos5-hsi2c";
1079 samsung,check-transdone-int;
1080 default-clk = <200000000>;
1081 reg = <0x0 0x138C0000 0x1000>;
1082 interrupts = <0 259 0>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&hsi2c14_bus>;
1087 clocks = <&clock I2C>, <&clock GATE_CAMI2C_2_QCH>;
1088 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1089 samsung,scl-clk-stretching;
1090 samsung,usi-i2c-v2;
1091 gpio_scl= <&gpc0 5 0x1>;
1092 gpio_sda= <&gpc0 4 0x1>;
1093 status = "disabled";
1094 };
1095
1096 /* USI_PERI_CAMI2C_3 */
1097 hsi2c_15: hsi2c@138D0000 {
1098 compatible = "samsung,exynos5-hsi2c";
1099 samsung,check-transdone-int;
1100 default-clk = <200000000>;
1101 reg = <0x0 0x138D0000 0x1000>;
1102 interrupts = <0 260 0>;
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&hsi2c15_bus>;
1107 clocks = <&clock I2C>, <&clock GATE_CAMI2C_3_QCH>;
1108 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1109 samsung,scl-clk-stretching;
1110 samsung,usi-i2c-v2;
1111 gpio_scl= <&gpc0 7 0x1>;
1112 gpio_sda= <&gpc0 6 0x1>;
1113 status = "disabled";
1114 };
1115
1116 /* USI_PERI_USI_0 */
1117 hsi2c_16: hsi2c@13920000 {
1118 compatible = "samsung,exynos5-hsi2c";
1119 samsung,check-transdone-int;
1120 default-clk = <200000000>;
1121 reg = <0x0 0x13920000 0x1000>;
1122 interrupts = <0 267 0>;
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125 pinctrl-names = "default";
1126 pinctrl-0 = <&hsi2c16_bus>;
1127 clocks = <&clock USI_USI>, <&clock GATE_USI00_USI_QCH>;
1128 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1129 samsung,scl-clk-stretching;
1130 samsung,usi-i2c-v2;
1131 gpio_scl= <&gpc1 0 0x1>;
1132 gpio_sda= <&gpc1 1 0x1>;
1133 status = "disabled";
1134 };
1135
1136 /* USI_PERI_USI_0_I2C */
1137 hsi2c_17: hsi2c@13930000 {
1138 compatible = "samsung,exynos5-hsi2c";
1139 samsung,check-transdone-int;
1140 default-clk = <200000000>;
1141 reg = <0x0 0x13930000 0x1000>;
1142 interrupts = <0 268 0>;
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 pinctrl-names = "default";
1146 pinctrl-0 = <&hsi2c17_bus>;
1147 clocks = <&clock USI_I2C>, <&clock GATE_USI00_I2C_QCH>;
1148 clock-names = "ipclk_hsi2c", "gate_hsi2c_clk";
1149 samsung,scl-clk-stretching;
1150 samsung,usi-i2c-v2;
1151 gpio_scl= <&gpc1 2 0x1>;
1152 gpio_sda= <&gpc1 3 0x1>;
1153 status = "disabled";
1154 };
1155
1156 /* USI_0_SHUB */
1157 spi_0: spi@110C0000 {
1158 compatible = "samsung,exynos-spi";
1159 reg = <0x0 0x110C0000 0x100>;
1160 samsung,spi-fifosize = <64>;
1161 interrupts = <0 112 0>;
1162 swap-mode;
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1165 clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>;
1166 clock-names = "gate_spi_clk", "ipclk_spi";
1167 pinctrl-names = "default";
1168 pinctrl-0 = <&spi0_bus>;
1169 status = "disabled";
1170 };
1171
1172 /* USI_0_CMGP */
1173 spi_1: spi@11D00000 {
1174 compatible = "samsung,exynos-spi";
1175 reg = <0x0 0x11D00000 0x100>;
1176 samsung,spi-fifosize = <64>;
1177 interrupts = <0 311 0>;
1178 swap-mode;
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1181 clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>;
1182 clock-names = "gate_spi_clk", "ipclk_spi";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&spi1_bus>;
1185 status = "disabled";
1186 };
1187
1188 /* USI_1_CMGP */
1189 spi_2: spi@11D20000 {
1190 compatible = "samsung,exynos-spi";
1191 reg = <0x0 0x11D20000 0x100>;
1192 samsung,spi-fifosize = <64>;
1193 interrupts = <0 312 0>;
1194 swap-mode;
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1197 clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>;
1198 clock-names = "gate_spi_clk", "ipclk_spi";
1199 pinctrl-names = "default";
1200 pinctrl-0 = <&spi2_bus>;
1201 status = "disabled";
1202 };
1203
1204 /* USI_2_CMGP */
1205 spi_3: spi@11D40000 {
1206 compatible = "samsung,exynos-spi";
1207 reg = <0x0 0x11D40000 0x100>;
1208 samsung,spi-fifosize = <64>;
1209 interrupts = <0 313 0>;
1210 swap-mode;
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213 clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>;
1214 clock-names = "gate_spi_clk", "ipclk_spi";
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&spi3_bus>;
1217 status = "disabled";
1218 };
1219
1220 /* USI_3_CMGP */
1221 spi_4: spi@11D60000 {
1222 compatible = "samsung,exynos-spi";
1223 reg = <0x0 0x11D60000 0x100>;
1224 samsung,spi-fifosize = <64>;
1225 interrupts = <0 314 0>;
1226 swap-mode;
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229 clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>;
1230 clock-names = "gate_spi_clk", "ipclk_spi";
1231 pinctrl-names = "default";
1232 pinctrl-0 = <&spi4_bus>;
1233 status = "disabled";
1234 };
1235
1236 /* USI_4_CMGP */
1237 spi_5: spi@11D80000 {
1238 compatible = "samsung,exynos-spi";
1239 reg = <0x0 0x11D80000 0x100>;
1240 samsung,spi-fifosize = <64>;
1241 interrupts = <0 315 0>;
1242 swap-mode;
1243 #address-cells = <1>;
1244 #size-cells = <0>;
1245 clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>;
1246 clock-names = "gate_spi_clk", "ipclk_spi";
1247 pinctrl-names = "default";
1248 pinctrl-0 = <&spi5_bus>;
1249 status = "disabled";
1250 };
1251
1252 /* USI_PERI_SPI_0 */
1253 spi_6: spi@13900000 {
1254 compatible = "samsung,exynos-spi";
1255 reg = <0x0 0x13900000 0x100>;
1256 samsung,spi-fifosize = <64>;
1257 interrupts = <0 254 0>;
1258 /*
1259 dma-mode;
1260 dmas = <&pdma0 19 &pdma0 18>;
1261 */
1262 dma-names = "tx", "rx";
1263 swap-mode;
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1266 clocks = <&clock GATE_SPI_0_QCH>, <&clock SPI0>;
1267 clock-names = "gate_spi_clk", "ipclk_spi";
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&spi6_bus>;
1270 status = "disabled";
1271 };
1272
1273 /* USI_PERI_SPI_1 */
1274 spi_7: spi@13910000 {
1275 compatible = "samsung,exynos-spi";
1276 reg = <0x0 0x13910000 0x100>;
1277 samsung,spi-fifosize = <64>;
1278 interrupts = <0 255 0>;
1279 /*
1280 dma-mode;
1281 dmas = <&pdma0 21 &pdma0 20>;
1282 */
1283 dma-names = "tx", "rx";
1284 swap-mode;
1285 #address-cells = <1>;
1286 #size-cells = <0>;
1287 clocks = <&clock GATE_SPI_1_QCH>, <&clock SPI1>;
1288 clock-names = "gate_spi_clk", "ipclk_spi";
1289 pinctrl-names = "default";
1290 pinctrl-0 = <&spi7_bus>;
1291 status = "disabled";
1292 };
1293
1294 /* USI_PERI_USI_0 */
1295 spi_8: spi@13920000 {
1296 compatible = "samsung,exynos-spi";
1297 reg = <0x0 0x13920000 0x100>;
1298 samsung,spi-fifosize = <64>;
1299 interrupts = <0 267 0>;
1300 /*
1301 dma-mode;
1302 dmas = <&pdma0 25 &pdma0 24>;
1303 */
1304 dma-names = "tx", "rx";
1305 swap-mode;
1306 #address-cells = <1>;
1307 #size-cells = <0>;
1308 clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>;
1309 clock-names = "gate_spi_clk", "ipclk_spi";
1310 pinctrl-names = "default";
1311 pinctrl-0 = <&spi8_bus>;
1312 status = "disabled";
1313 };
1314
1315 /* SPI USI_PERI_SPI_2 */
1316 spi_9: spi@13940000 {
1317 compatible = "samsung,exynos-spi";
1318 reg = <0x0 0x13940000 0x100>;
1319 samsung,spi-fifosize = <256>;
1320 interrupts = <0 256 0>;
1321 /*
1322 dma-mode;
1323 dmas = <&pdma0 23 &pdma0 22>;
1324 */
1325 dma-names = "tx", "rx";
1326 swap-mode;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1329 clocks = <&clock GATE_SPI_2_QCH>, <&clock SPI2>;
1330 clock-names = "gate_spi_clk", "ipclk_spi";
1331 pinctrl-names = "default";
1332 pinctrl-0 = <&spi9_bus>;
1333 status = "disabled";
1334 };
1335
1336 /* USI_PERI_UART */
1337 serial_0: uart@13820000 {
1338 compatible = "samsung,exynos-uart";
1339 samsung,separate-uart-clk;
1340 reg = <0x0 0x13820000 0x100>;
1341 samsung,fifo-size = <256>;
1342 interrupts = <0 246 0>;
1343 pinctrl-names = "default";
1344 pinctrl-0 = <&uart0_bus>; /* or _bus_dual */
1345 samsung,usi-serial-v2;
1346 clocks = <&clock GATE_UART_QCH>, <&clock UART>;
1347 clock-names = "gate_uart_clk0", "ipclk_uart0";
1348 status = "disabled";
1349 };
1350
1351 /* USI_0_SHUB */
1352 serial_1: uart@110C0000 {
1353 compatible = "samsung,exynos-uart";
1354 samsung,separate-uart-clk;
1355 reg = <0x0 0x110C0000 0x100>;
1356 samsung,fifo-size = <64>;
1357 interrupts = <0 112 0>;
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&uart1_bus_single>; /* or _bus_dual */
1360 samsung,usi-serial-v2;
1361 clocks = <&clock GATE_USI_SHUB00_QCH>, <&clock MUX_SHUB_USI00>;
1362 clock-names = "gate_uart_clk1", "ipclk_uart1";
1363 status = "disabled";
1364 };
1365
1366 /* USI_0_CMGP */
1367 serial_2: uart@11D00000 {
1368 compatible = "samsung,exynos-uart";
1369 samsung,separate-uart-clk;
1370 reg = <0x0 0x11D00000 0x100>;
1371 samsung,fifo-size = <64>;
1372 interrupts = <0 311 0>;
1373 pinctrl-names = "default";
1374 pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */
1375 samsung,usi-serial-v2;
1376 clocks = <&clock GATE_USI_CMGP00_QCH>, <&clock CMGP00_USI>;
1377 clock-names = "gate_uart_clk2", "ipclk_uart2";
1378 status = "disabled";
1379 };
1380
1381 /* USI_1_CMGP */
1382 serial_3: uart@11D20000 {
1383 compatible = "samsung,exynos-uart";
1384 samsung,separate-uart-clk;
1385 reg = <0x0 0x11D20000 0x100>;
1386 samsung,fifo-size = <64>;
1387 interrupts = <0 312 0>;
1388 pinctrl-names = "default";
1389 pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */
1390 samsung,usi-serial-v2;
1391 clocks = <&clock GATE_USI_CMGP01_QCH>, <&clock CMGP01_USI>;
1392 clock-names = "gate_uart_clk3", "ipclk_uart3";
1393 status = "disabled";
1394 };
1395
1396 /* USI_2_CMGP */
1397 serial_4: uart@11D40000 {
1398 compatible = "samsung,exynos-uart";
1399 samsung,separate-uart-clk;
1400 reg = <0x0 0x11D40000 0x100>;
1401 samsung,fifo-size = <64>;
1402 interrupts = <0 313 0>;
1403 pinctrl-names = "default";
1404 pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */
1405 samsung,usi-serial-v2;
1406 clocks = <&clock GATE_USI_CMGP02_QCH>, <&clock CMGP02_USI>;
1407 clock-names = "gate_uart_clk4", "ipclk_uart4";
1408 status = "disabled";
1409 };
1410
1411 /* USI_3_CMGP */
1412 serial_5: uart@11D60000 {
1413 compatible = "samsung,exynos-uart";
1414 samsung,separate-uart-clk;
1415 reg = <0x0 0x11D60000 0x100>;
1416 samsung,fifo-size = <64>;
1417 interrupts = <0 314 0>;
1418 pinctrl-names = "default";
1419 pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */
1420 samsung,usi-serial-v2;
1421 clocks = <&clock GATE_USI_CMGP03_QCH>, <&clock CMGP03_USI>;
1422 clock-names = "gate_uart_clk5", "ipclk_uart5";
1423 status = "disabled";
1424 };
1425
1426 /* USI_4_CMGP */
1427 serial_6: uart@11D80000 {
1428 compatible = "samsung,exynos-uart";
1429 samsung,separate-uart-clk;
1430 reg = <0x0 0x11D80000 0x100>;
1431 samsung,fifo-size = <64>;
1432 interrupts = <0 315 0>;
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */
1435 samsung,usi-serial-v2;
1436 clocks = <&clock GATE_USI_CMGP04_QCH>, <&clock CMGP04_USI>;
1437 clock-names = "gate_uart_clk6", "ipclk_uart6";
1438 status = "disabled";
1439 };
1440
1441 /* USI_PERI_USI_0 */
1442 serial_7: uart@13920000 {
1443 compatible = "samsung,exynos-uart";
1444 samsung,separate-uart-clk;
1445 reg = <0x0 0x13920000 0x100>;
1446 samsung,fifo-size = <64>;
1447 interrupts = <0 267 0>;
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */
1450 samsung,usi-serial-v2;
1451 clocks = <&clock GATE_USI00_USI_QCH>, <&clock USI_USI>;
1452 clock-names = "gate_uart_clk7", "ipclk_uart7";
1453 status = "disabled";
1454 };
1455
1456 /* I2C_0 */
1457 i2c_0: i2c@13830000 {
1458 compatible = "samsung,s3c2440-i2c";
1459 reg = <0x0 0x13830000 0x100>;
1460 interrupts = <0 247 0>;
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 pinctrl-names = "default";
1464 pinctrl-0 = <&i2c0_bus>;
1465 clocks = <&clock GATE_I2C_0_QCH>, <&clock GATE_I2C_0_QCH>;
1466 clock-names = "rate_i2c", "gate_i2c";
1467 status = "disabled";
1468 };
1469
1470 /* I2C_1 */
1471 i2c_1: i2c@13840000 {
1472 compatible = "samsung,s3c2440-i2c";
1473 reg = <0x0 0x13840000 0x100>;
1474 interrupts = <0 248 0>;
1475 #address-cells = <1>;
1476 #size-cells = <0>;
1477 pinctrl-names = "default";
1478 pinctrl-0 = <&i2c1_bus>;
1479 clocks = <&clock GATE_I2C_1_QCH>, <&clock GATE_I2C_1_QCH>;
1480 clock-names = "rate_i2c", "gate_i2c";
1481 status = "disabled";
1482 };
1483
1484 /* I2C_2 */
1485 i2c_2: i2c@13850000 {
1486 compatible = "samsung,s3c2440-i2c";
1487 reg = <0x0 0x13850000 0x100>;
1488 interrupts = <0 249 0>;
1489 #address-cells = <1>;
1490 #size-cells = <0>;
1491 pinctrl-names = "default";
1492 pinctrl-0 = <&i2c2_bus>;
1493 clocks = <&clock GATE_I2C_2_QCH>, <&clock GATE_I2C_2_QCH>;
1494 clock-names = "rate_i2c", "gate_i2c";
1495 status = "disabled";
1496 };
1497
1498 /* I2C_3 */
1499 i2c_3: i2c@13860000 {
1500 compatible = "samsung,s3c2440-i2c";
1501 reg = <0x0 0x13860000 0x100>;
1502 interrupts = <0 250 0>;
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1505 pinctrl-names = "default";
1506 pinctrl-0 = <&i2c3_bus>;
1507 clocks = <&clock GATE_I2C_3_QCH>, <&clock GATE_I2C_3_QCH>;
1508 clock-names = "rate_i2c", "gate_i2c";
1509 status = "disabled";
1510 };
1511
1512 /* I2C_4 */
1513 i2c_4: i2c@13870000 {
1514 compatible = "samsung,s3c2440-i2c";
1515 reg = <0x0 0x13870000 0x100>;
1516 interrupts = <0 251 0>;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 pinctrl-names = "default";
1520 pinctrl-0 = <&i2c4_bus>;
1521 clocks = <&clock GATE_I2C_4_QCH>, <&clock GATE_I2C_4_QCH>;
1522 clock-names = "rate_i2c", "gate_i2c";
1523 status = "disabled";
1524 };
1525
1526 /* I2C_5 */
1527 i2c_5: i2c@13880000 {
1528 compatible = "samsung,s3c2440-i2c";
1529 reg = <0x0 0x13880000 0x100>;
1530 interrupts = <0 252 0>;
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1533 pinctrl-names = "default";
1534 pinctrl-0 = <&i2c5_bus>;
1535 clocks = <&clock GATE_I2C_5_QCH>, <&clock GATE_I2C_5_QCH>;
1536 clock-names = "rate_i2c", "gate_i2c";
1537 status = "disabled";
1538 };
1539
1540 /* I2C_6 */
1541 i2c_6: i2c@13890000 {
1542 compatible = "samsung,s3c2440-i2c";
1543 reg = <0x0 0x13890000 0x100>;
1544 interrupts = <0 253 0>;
1545 #address-cells = <1>;
1546 #size-cells = <0>;
1547 pinctrl-names = "default";
1548 pinctrl-0 = <&i2c6_bus>;
1549 clocks = <&clock GATE_I2C_6_QCH>, <&clock GATE_I2C_6_QCH>;
1550 clock-names = "rate_i2c", "gate_i2c";
1551 status = "disabled";
1552 };
1553
1554 exynos_dm: exynos-dm@17000000 {
1555 compatible = "samsung,exynos-dvfs-manager";
1556 reg = <0x0 0x17000000 0x0>;
1557 acpm-ipc-channel = <1>;
1558 dm_domains {
1559 cpufreq_cl0 {
1560 dm-index = <DM_CPU_CL0>;
1561 available = "true";
1562 cal_id = <ACPM_DVFS_CPUCL0>;
1563 dm_type_name = "dm_cpu_cl0";
1564 };
1565 cpufreq_cl1 {
1566 dm-index = <DM_CPU_CL1>;
1567 available = "true";
1568 cal_id = <ACPM_DVFS_CPUCL1>;
1569 dm_type_name = "dm_cpu_cl1";
1570 };
1571 devfreq_mif {
1572 dm-index = <DM_MIF>;
1573 available = "true";
1574 policy_use = "true";
1575 cal_id = <ACPM_DVFS_MIF>;
1576 dm_type_name = "dm_mif";
1577 };
1578 devfreq_int {
1579 dm-index = <DM_INT>;
1580 available = "true";
1581 policy_use = "true";
1582 cal_id = <ACPM_DVFS_INT>;
1583 dm_type_name = "dm_int";
1584 };
1585 devfreq_intcam {
1586 dm-index = <DM_INTCAM>;
1587 available = "true";
1588 cal_id = <ACPM_DVFS_INTCAM>;
1589 dm_type_name = "dm_intcam";
1590 };
1591 devfreq_cam {
1592 dm-index = <DM_CAM>;
1593 available = "true";
1594 cal_id = <ACPM_DVFS_CAM>;
1595 dm_type_name = "dm_cam";
1596 };
1597 devfreq_disp {
1598 dm-index = <DM_DISP>;
1599 available = "true";
1600 cal_id = <ACPM_DVFS_DISP>;
1601 dm_type_name = "dm_disp";
1602 };
1603 devfreq_aud {
1604 dm-index = <DM_AUD>;
1605 available = "true";
1606 cal_id = <ACPM_DVFS_AUD>;
1607 dm_type_name = "dm_aud";
1608 };
1609 dvfs_gpu {
1610 dm-index = <DM_GPU>;
1611 available = "false";
1612 cal_id = <ACPM_DVFS_G3D>;
1613 dm_type_name = "dm_gpu";
1614 };
1615 };
1616 };
1617
1618 exynos_devfreq {
1619 compatible = "samsung,exynos-devfreq-root";
1620 #address-cells = <2>;
1621 #size-cells = <1>;
1622 ranges;
1623 devfreq_0: devfreq_mif@17000010 {
1624 compatible = "samsung,exynos-devfreq";
1625 reg = <0x0 0x17000010 0x0>;
1626 devfreq_type = <DEVFREQ_MIF>;
1627 devfreq_domain_name = "dvfs_mif";
1628 pm_qos_class = <13>; /* PM_QOS_BUS_THROUGHPUT */
1629 pm_qos_class_max = <14>; /* PM_QOS_BUS_THROUGHPUT_MAX */
1630 ess_flag = <ESS_FLAG_MIF>;
1631 dm-index = <DM_MIF>;
1632
1633 /* Delay time */
1634 use_delay_time = "true";
1635 delay_time_list = "20";
1636
1637 freq_info = <2093000 546000 419000 419000 2093000 419000>;
1638 /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */
1639
1640 /* Booting value */
1641 boot_info = <40 2093000>;
1642 /* boot_qos_timeout, boot_freq */
1643
1644 /* governor data */
1645 governor = <SIMPLE_INTERACTIVE>;
1646
1647 bts_update = "false";
1648 dfs_id = <ACPM_DVFS_MIF>;
1649 acpm-ipc-channel = <1>;
1650 use_acpm = "true";
1651 update_fvp = "true";
1652 };
1653
1654 devfreq_1: devfreq_int@17000020 {
1655 compatible = "samsung,exynos-devfreq";
1656 reg = <0x0 0x17000020 0x0>;
1657 devfreq_type = <DEVFREQ_INT>;
1658 devfreq_domain_name = "dvfs_int";
1659 pm_qos_class = <9>; /* PM_QOS_DEVICE_THROUGHPUT */
1660 pm_qos_class_max = <11>; /* PM_QOS_DEVICE_THROUGHPUT_MAX */
1661 ess_flag = <ESS_FLAG_INT>;
1662 dm-index = <DM_INT>;
1663
1664 /* Delay time */
1665 use_delay_time = "false";
1666
1667 freq_info = <667000 100000 667000 100000 667000 100000>;
1668 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
1669
1670 /* Booting value */
1671 boot_info = <40 667000>;
1672 /* boot_qos_timeout, boot_freq */
1673
1674 /* governor data */
1675 governor = <SIMPLE_INTERACTIVE>;
1676
1677 bts_update = "false";
1678 dfs_id = <ACPM_DVFS_INT>;
1679 acpm-ipc-channel = <1>;
1680 use_acpm = "true";
1681 skew {
1682 skew_0 {
1683 constraint_dm_type = <DM_MIF>;
1684 constraint_type = <CONSTRAINT_MIN>;
1685 };
1686 };
1687 };
1688
1689 devfreq_2: devfreq_intcam@17000030 {
1690 compatible = "samsung,exynos-devfreq";
1691 reg = <0x0 0x17000030 0x0>;
1692 devfreq_type = <DEVFREQ_INTCAM>;
1693 devfreq_domain_name = "dvfs_intcam";
1694 pm_qos_class = <10>; /* PM_QOS_INTCAM_THROUGHPUT */
1695 pm_qos_class_max = <12>; /* PM_QOS_INTCAM_THROUGHPUT_MAX */
1696 ess_flag = <ESS_FLAG_INTCAM>;
1697 dm-index = <DM_INTCAM>;
1698
1699 /* Delay time */
1700 use_delay_time = "false";
1701
1702 freq_info = <690000 650000 690000 650000 690000 650000>;
1703 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
1704
1705 /* Booting value */
1706 boot_info = <40 640000>;
1707 /* boot_qos_timeout, boot_freq */
1708
1709 /* governor data */
1710 governor = <SIMPLE_INTERACTIVE>;
1711
1712 bts_update = "false";
1713 dfs_id = <ACPM_DVFS_INTCAM>;
1714 };
1715
1716 devfreq_3: devfreq_disp@17000040 {
1717 compatible = "samsung,exynos-devfreq";
1718 reg = <0x0 0x17000040 0x0>;
1719 devfreq_type = <DEVFREQ_DISP>;
1720 devfreq_domain_name = "dvfs_disp";
1721 pm_qos_class = <17>; /* PM_QOS_DISPLAY_THROUGHPUT */
1722 pm_qos_class_max = <18>; /* PM_QOS_DISPLAY_THROUGHPUT_MAX */
1723 ess_flag = <ESS_FLAG_DISP>;
1724 dm-index = <DM_DISP>;
1725
1726 /* Delay time */
1727 use_delay_time = "false";
1728
1729 freq_info = <533000 167000 533000 167000 533000 533000>;
1730 /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
1731
1732 /* Booting value */
1733 boot_info = <40 533000>;
1734 /* boot_qos_timeout, boot_freq */
1735
1736 /* governor data */
1737 governor = <SIMPLE_INTERACTIVE>;
1738
1739 bts_update = "false";
1740 dfs_id = <ACPM_DVFS_DISP>;
1741 };
1742
1743 devfreq_4: devfreq_cam@17000050 {
1744 compatible = "samsung,exynos-devfreq";
1745 reg = <0x0 0x17000050 0x0>;
1746 devfreq_type = <DEVFREQ_CAM>;
1747 devfreq_domain_name = "dvfs_cam";
1748 pm_qos_class = <19>; /* PM_QOS_CAM_THROUGHPUT */
1749 pm_qos_class_max = <21>; /* PM_QOS_CAM_THROUGHPUT_MAX */
1750 ess_flag = <ESS_FLAG_ISP>;
1751 dm-index = <DM_CAM>;
1752
1753 /* Delay time */
1754 use_delay_time = "false";
1755
1756 freq_info = <690000 640000 690000 640000 690000 640000>;
1757 /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
1758
1759 /* Booting value */
1760 boot_info = <40 690000>;
1761 /* boot_qos_timeout, boot_freq */
1762
1763 /* governor data */
1764 governor = <SIMPLE_INTERACTIVE>;
1765
1766 bts_update = "false";
1767
1768 dfs_id = <ACPM_DVFS_CAM>;
1769 };
1770
1771 devfreq_5: devfreq_aud@17000060 {
1772 compatible = "samsung,exynos-devfreq";
1773 reg = <0x0 0x17000060 0x0>;
1774 devfreq_type = <DEVFREQ_AUD>;
1775 devfreq_domain_name = "dvfs_aud";
1776 pm_qos_class = <20>; /* PM_QOS_AUD_THROUGHPUT */
1777 pm_qos_class_max = <22>; /* PM_QOS_AUD_THROUGHPUT_MAX */
1778 ess_flag = <ESS_FLAG_AUD>;
1779 dm-index = <DM_AUD>;
1780
1781 /* Delay time */
1782 use_delay_time = "false";
1783
1784 freq_info = <393000 393000 393000 393000 1180000 393000>;
1785 /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
1786
1787 /* Booting value */
1788 boot_info = <40 393000>;
1789 /* boot_qos_timeout, boot_freq */
1790
1791 /* governor data */
1792 governor = <SIMPLE_INTERACTIVE>;
1793
1794 bts_update = "false";
1795 dfs_id = <ACPM_DVFS_AUD>;
1796
1797 samsung,power-domain = <&pd_dispaud>;
1798 pd_name = "pd-dispaud";
1799 };
1800 };
1801
1802 tmuctrl_0: BIG@10070000 {
1803 compatible = "samsung,exynos9610-tmu";
1804 reg = <0x0 0x10070000 0x700>;
1805 interrupts = <0 231 0>;
1806 tmu_name = "BIG";
1807 id = <0>;
1808 sensors = <4>; /* P2 */
1809 sensing_mode = "max";
1810 hotplug_enable = <1>;
1811 hotplug_in_threshold = <91>;
1812 hotplug_out_threshold = <96>;
1813 #include "exynos9610-tmu-sensor-conf.dtsi"
1814 };
1815
1816 tmuctrl_1: LITTLE@10070000 {
1817 compatible = "samsung,exynos9610-tmu";
1818 reg = <0x0 0x10070000 0x700>;
1819 interrupts = <0 231 0>;
1820 tmu_name = "LITTLE";
1821 id = <1>;
1822 sensors = <2>; /* P1 */
1823 sensing_mode = "max";
1824 #include "exynos9610-tmu-sensor-conf.dtsi"
1825 };
1826
1827 tmuctrl_2: G3D@10070000 {
1828 compatible = "samsung,exynos9610-tmu";
1829 reg = <0x0 0x10070000 0x700>;
1830 interrupts = <0 231 0>;
1831 tmu_name = "G3D";
1832 id = <2>;
1833 sensors = <1>; /* P0 */
1834 sensing_mode = "max";
1835 #include "exynos9610-tmu-sensor-conf.dtsi"
1836 };
1837
1838 tmuctrl_3: ISP@10070000 {
1839 compatible = "samsung,exynos9610-tmu";
1840 reg = <0x0 0x10070000 0x700>;
1841 interrupts = <0 231 0>;
1842 tmu_name = "ISP";
1843 id = <3>;
1844 sensors = <2>; /* P1 */
1845 sensing_mode = "max";
1846 #include "exynos9610-tmu-sensor-conf.dtsi"
1847 };
1848
1849 fimc_is: dummy@1A000000 {
1850 };
1851
1852 acpm_tmu {
1853 acpm-ipc-channel = <7>;
1854 };
1855
1856 thermal-zones {
1857 big_thermal: BIG {
1858 zone_name = "BIG_THERMAL";
1859 polling-delay-passive = <50>;
1860 polling-delay = <1000>;
1861 thermal-sensors = <&tmuctrl_0>;
1862 governor = "power_allocator";
1863 sustainable-power = <0>;
1864 k_po = <0>;
1865 k_pu = <0>;
1866 k_i = <0>;
1867 i_max = <0>;
1868 integral_cutoff = <0>;
1869
1870 trips {
1871 big_cold: big-cold {
1872 temperature = <20000>;
1873 hysteresis = <5000>; /* millicelsius */
1874 type = "active";
1875 };
1876 big_switch_on: big-switch-on {
1877 temperature = <63000>; /* millicelsius */
1878 hysteresis = <2000>; /* millicelsius */
1879 type = "active";
1880 };
1881 big_control_temp: big-control-temp {
1882 temperature = <83000>; /* millicelsius */
1883 hysteresis = <5000>; /* millicelsius */
1884 type = "passive";
1885 };
1886 big_alert0: big-alert0 {
1887 temperature = <95000>; /* millicelsius */
1888 hysteresis = <5000>; /* millicelsius */
1889 type = "active";
1890 };
1891 big_alert1: big-alert1 {
1892 temperature = <100000>; /* millicelsius */
1893 hysteresis = <5000>; /* millicelsius */
1894 type = "active";
1895 };
1896 big_alert2: big-alert2 {
1897 temperature = <105000>; /* millicelsius */
1898 hysteresis = <5000>; /* millicelsius */
1899 type = "active";
1900 };
1901 big_alert3: big-alert3 {
1902 temperature = <110000>; /* millicelsius */
1903 hysteresis = <5000>; /* millicelsius */
1904 type = "active";
1905 };
1906 big_hot: big-hot {
1907 temperature = <115000>; /* millicelsius */
1908 hysteresis = <5000>; /* millicelsius */
1909 type = "hot";
1910 };
1911 };
1912
1913 cooling-maps {
1914 map0 {
1915 trip = <&big_control_temp>;
1916 cooling-device = <&cpufreq_domain1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1917 };
1918 };
1919 };
1920
1921 little_thermal: LITTLE {
1922 zone_name = "LITTLE_THERMAL";
1923 polling-delay-passive = <0>;
1924 polling-delay = <0>;
1925 thermal-sensors = <&tmuctrl_1>;
1926
1927 trips {
1928 little_alert0: little-alert0 {
1929 temperature = <20000>; /* millicelsius */
1930 hysteresis = <5000>; /* millicelsius */
1931 type = "active";
1932 };
1933 little_alert1: little-alert1 {
1934 temperature = <76000>; /* millicelsius */
1935 hysteresis = <5000>; /* millicelsius */
1936 type = "active";
1937 };
1938 little_alert2: little-alert2 {
1939 temperature = <81000>; /* millicelsius */
1940 hysteresis = <5000>; /* millicelsius */
1941 type = "active";
1942 };
1943 little_alert3: little-alert3 {
1944 temperature = <91000>; /* millicelsius */
1945 hysteresis = <5000>; /* millicelsius */
1946 type = "active";
1947 };
1948 little_alert4: little-alert4 {
1949 temperature = <96000>; /* millicelsius */
1950 hysteresis = <5000>; /* millicelsius */
1951 type = "active";
1952 };
1953 little_alert5: little-alert5 {
1954 temperature = <101000>; /* millicelsius */
1955 hysteresis = <5000>; /* millicelsius */
1956 type = "active";
1957 };
1958 little_alert6: little-alert6 {
1959 temperature = <106000>; /* millicelsius */
1960 hysteresis = <5000>; /* millicelsius */
1961 type = "active";
1962 };
1963 little_hot: little-hot {
1964 temperature = <115000>; /* millicelsius */
1965 hysteresis = <5000>; /* millicelsius */
1966 type = "hot";
1967 };
1968 };
1969
1970 cooling-maps {
1971 map0 {
1972 trip = <&little_alert0>;
1973 /* Corresponds to 1534MHz at freq_table */
1974 cooling-device = <&cpufreq_domain0 0 0>;
1975 };
1976 map1 {
1977 trip = <&little_alert1>;
1978 /* Corresponds to 1326MHz at freq_table */
1979 cooling-device = <&cpufreq_domain0 0 0>;
1980 };
1981 map2 {
1982 trip = <&little_alert2>;
1983 /* Corresponds to 1118MHz at freq_table */
1984 cooling-device = <&cpufreq_domain0 0 0>;
1985 };
1986 map3 {
1987 trip = <&little_alert3>;
1988 /* Corresponds to 910MHz at freq_table */
1989 cooling-device = <&cpufreq_domain0 0 0>;
1990 };
1991 map4 {
1992 trip = <&little_alert4>;
1993 /* Corresponds to 702MHz at freq_table */
1994 cooling-device = <&cpufreq_domain0 0 0>;
1995 };
1996 map5 {
1997 trip = <&little_alert5>;
1998 /* Corresponds to 403MHz at freq_table */
1999 cooling-device = <&cpufreq_domain0 0 0>;
2000 };
2001 map6 {
2002 trip = <&little_alert6>;
2003 /* Corresponds to 403MHz at freq_table */
2004 cooling-device = <&cpufreq_domain0 0 0>;
2005 };
2006 map7 {
2007 trip = <&little_hot>;
2008 /* Corresponds to 403MHz at freq_table */
2009 cooling-device = <&cpufreq_domain0 0 0>;
2010 };
2011 };
2012 };
2013
2014 gpu_thermal: G3D {
2015 zone_name = "G3D_THERMAL";
2016 polling-delay-passive = <100>;
2017 polling-delay = <0>;
2018 thermal-sensors = <&tmuctrl_2>;
2019 governor = "power_allocator";
2020 sustainable-power = <0>;
2021 k_po = <0>;
2022 k_pu = <0>;
2023 k_i = <0>;
2024 i_max = <0>;
2025 integral_cutoff = <0>;
2026
2027 trips {
2028 gpu_cold: gpu-cold {
2029 temperature = <20000>;
2030 hysteresis = <5000>; /* millicelsius */
2031 type = "active";
2032 };
2033 gpu_switch_on: gpu-switch-on {
2034 temperature = <80000>; /* millicelsius */
2035 hysteresis = <2000>; /* millicelsius */
2036 type = "active";
2037 };
2038 gpu_control_temp: gpu-control-temp {
2039 temperature = <88000>; /* millicelsius */
2040 hysteresis = <5000>; /* millicelsius */
2041 type = "passive";
2042 };
2043 gpu_alert0: gpu-alert0 {
2044 temperature = <95000>; /* millicelsius */
2045 hysteresis = <5000>; /* millicelsius */
2046 type = "active";
2047 };
2048 gpu_alert1: gpu-alert1 {
2049 temperature = <100000>; /* millicelsius */
2050 hysteresis = <5000>; /* millicelsius */
2051 type = "active";
2052 };
2053 gpu_alert2: gpu-alert2 {
2054 temperature = <105000>; /* millicelsius */
2055 hysteresis = <5000>; /* millicelsius */
2056 type = "active";
2057 };
2058 gpu_alert3: gpu-alert3 {
2059 temperature = <110000>; /* millicelsius */
2060 hysteresis = <5000>; /* millicelsius */
2061 type = "active";
2062 };
2063 gpu_hot: gpu-hot {
2064 temperature = <115000>; /* millicelsius */
2065 hysteresis = <5000>; /* millicelsius */
2066 type = "hot";
2067 };
2068 };
2069
2070 cooling-maps {
2071 map0 {
2072 trip = <&gpu_control_temp>;
2073 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2074 };
2075 };
2076 };
2077
2078 isp_thermal: ISP {
2079 zone_name = "ISP_THERMAL";
2080 polling-delay-passive = <0>;
2081 polling-delay = <0>;
2082 thermal-sensors = <&tmuctrl_3>;
2083
2084 trips {
2085 isp_alert0: isp-alert0 {
2086 temperature = <20000>; /* millicelsius */
2087 hysteresis = <5000>; /* millicelsius */
2088 type = "active";
2089 };
2090 isp_alert1: isp-alert1 {
2091 temperature = <76000>; /* millicelsius */
2092 hysteresis = <5000>; /* millicelsius */
2093 type = "active";
2094 };
2095 isp_alert2: isp-alert2 {
2096 temperature = <81000>; /* millicelsius */
2097 hysteresis = <5000>; /* millicelsius */
2098 type = "active";
2099 };
2100 isp_alert3: isp-alert3 {
2101 temperature = <91000>; /* millicelsius */
2102 hysteresis = <5000>; /* millicelsius */
2103 type = "active";
2104 };
2105 isp_alert4: isp-alert4 {
2106 temperature = <96000>; /* millicelsius */
2107 hysteresis = <5000>; /* millicelsius */
2108 type = "active";
2109 };
2110 isp_alert5: isp-alert5 {
2111 temperature = <101000>; /* millicelsius */
2112 hysteresis = <5000>; /* millicelsius */
2113 type = "active";
2114 };
2115 isp_alert6: isp-alert6 {
2116 temperature = <106000>; /* millicelsius */
2117 hysteresis = <5000>; /* millicelsius */
2118 type = "active";
2119 };
2120 isp_hot: isp-hot {
2121 temperature = <115000>; /* millicelsius */
2122 hysteresis = <5000>; /* millicelsius */
2123 type = "hot";
2124 };
2125 };
2126
2127 cooling-maps {
2128 map0 {
2129 trip = <&isp_alert0>;
2130 /* Corresponds to No limit */
2131 cooling-device = <&fimc_is 0 0>;
2132 };
2133 map1 {
2134 trip = <&isp_alert1>;
2135 /* Corresponds to No limit */
2136 cooling-device = <&fimc_is 0 0>;
2137 };
2138 map2 {
2139 trip = <&isp_alert2>;
2140 /* Corresponds to 15fps at freq_table */
2141 cooling-device = <&fimc_is 0 0>;
2142 };
2143 map3 {
2144 trip = <&isp_alert3>;
2145 /* Corresponds to 5fps at freq_table */
2146 cooling-device = <&fimc_is 0 0>;
2147 };
2148 map4 {
2149 trip = <&isp_alert4>;
2150 /* Corresponds to 5fps at freq_table */
2151 cooling-device = <&fimc_is 0 0>;
2152 };
2153 map5 {
2154 trip = <&isp_alert5>;
2155 /* Corresponds to 5fps at freq_table */
2156 cooling-device = <&fimc_is 0 0>;
2157 };
2158 map6 {
2159 trip = <&isp_alert6>;
2160 /* Corresponds to 5fps at freq_table */
2161 cooling-device = <&fimc_is 0 0>;
2162 };
2163 map7 {
2164 trip = <&isp_hot>;
2165 /* Corresponds to HW trip */
2166 cooling-device = <&fimc_is 0 0>;
2167 };
2168 };
2169 };
2170 };
2171
2172 fmp_0: fmp {
2173 compatible = "samsung,exynos-fmp";
2174 };
2175
2176 ufs: ufs@0x13520000 {
2177 /* ----------------------- */
2178 /* 1. SYSTEM CONFIGURATION */
2179 /* ----------------------- */
2180 compatible ="samsung,exynos-ufs";
2181 #address-cells = <2>;
2182 #size-cells = <1>;
2183 ranges;
2184 reg =
2185 <0x0 0x13520000 0x200>, /* 0: HCI standard */
2186 <0x0 0x13521100 0x200>, /* 1: Vendor specificed */
2187 <0x0 0x13510000 0x8000>, /* 2: UNIPRO */
2188 <0x0 0x13530000 0x100>; /* 3: UFS protector */
2189 interrupts = <0 157 0>;
2190 pinctrl-names = "default";
2191 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
2192 clocks =
2193 /* aclk clock */
2194 <&clock GATE_UFS_EMBD_QCH_UFS>,
2195 /* unipro clocks */
2196 <&clock UFS_EMBD>;
2197
2198 clock-names =
2199 /* aclk clocks */
2200 "GATE_UFS_EMBD_QCH_UFS",
2201 /* unipro clocks */
2202 "UFS_EMBD";
2203
2204 /* PM QoS for INT power domain */
2205 /* ufs-pm-qos-int = <400000>;*/
2206
2207 /* DMA coherent callback, should be coupled with 'ufs-sys' */
2208 dma-coherent;
2209
2210 /* UFS PHY isolation and TCXO control */
2211 samsung,pmu-phandle = <&pmu_system_controller>;
2212
2213 /* TCXO exclusive control */
2214 tcxo-ex-ctrl = <0>;
2215
2216 /* UFS IO coherency */
2217 samsung,sysreg-fsys-phandle = <&sysreg_fsys_system_controller>;
2218
2219 /* ----------------------- */
2220 /* 2. UFS COMMON */
2221 /* ----------------------- */
2222 freq-table-hz = <0 0>, <0 0>;
2223
2224 vcc-supply = <&ufs_fixed_vcc>;
2225 vcc-fixed-regulator;
2226
2227
2228 /* ----------------------- */
2229 /* 3. UFS EXYNOS */
2230 /* ----------------------- */
2231 hw-rev = <UFS_VER_0005>;
2232
2233 /* power mode change */
2234 ufs,pmd-attr-lane = /bits/ 8 <1>;
2235 ufs,pmd-attr-gear = /bits/ 8 <3>;
2236
2237 /* hiberantion */
2238 ufs-rx-min-activate-time-cap = <3>;
2239 ufs-rx-hibern8-time-cap = <2>;
2240 ufs-tx-hibern8-time-cap = <2>;
2241
2242 /* board type for UFS CAL */
2243 brd-for-cal = <0>;
2244
2245 fmp-id = <0>;
2246 smu-id = <0>;
2247
2248 /* ----------------------- */
2249 /* 4. ADDITIONAL NODES */
2250 /* ----------------------- */
2251 ufs-phy {
2252 #address-cells = <2>;
2253 #size-cells = <1>;
2254 ranges;
2255 reg = <0x0 0x13524000 0x800>;
2256 };
2257
2258 ufs-dma-coherency {
2259 #address-cells = <2>;
2260 #size-cells = <1>;
2261
2262 offset = <0x1010>;
2263 mask = <(BIT_8 | BIT_9)>;
2264 val = <(BIT_8 | BIT_9)>;
2265 };
2266 };
2267
2268 ufs_fixed_vcc: fixedregulator@0 {
2269 compatible = "regulator-fixed";
2270 regulator-name = "ufs-vcc";
2271 gpio = <&gpg4 0 0>;
2272 regulator-boot-on;
2273 enable-active-high;
2274 };
2275
2276 exynos-pmu {
2277 compatible = "samsung,exynos-pmu";
2278 samsung,syscon-phandle = <&pmu_system_controller>;
2279 };
2280
2281 pmu_system_controller: system-controller@11860000 {
2282 compatible = "samsung,exynos9610-pmu", "syscon";
2283 reg = <0x0 0x11860000 0x10000>;
2284 };
2285
2286 exynos-sysreg-fsys {
2287 compatible = "samsung,exynos-sysreg-fsys";
2288 samsung,syscon-phandle = <&sysreg_fsys_system_controller>;
2289 };
2290
2291 sysreg_fsys_system_controller: system-controller@13410000 {
2292 compatible = "samsung,exynos9610-sysreg-fsys", "syscon";
2293 reg = <0x0 0x13410000 0x1020>;
2294 };
2295
2296 /* DMA */
2297 amba {
2298 #address-cells = <2>;
2299 #size-cells = <1>;
2300 compatible = "arm,amba-bus";
2301 interrupt-parent = <&gic>;
2302 ranges;
2303
2304 pdma0: pdma0@120C0000 {
2305 compatible = "arm,pl330", "arm,primecell";
2306 reg = <0x0 0x120C0000 0x1000>;
2307 interrupts = <0 294 0>;
2308 clocks = <&clock GATE_PDMA_CORE_QCH>;
2309 clock-names = "apb_pclk";
2310 #dma-cells = <1>;
2311 #dma-channels = <8>;
2312 #dma-requests = <32>;
2313 #dma-multi-irq = <1>;
2314 dma-arwrapper = <0x120C4400>,
2315 <0x120C4420>,
2316 <0x120C4440>,
2317 <0x120C4460>,
2318 <0x120C4480>,
2319 <0x120C44A0>,
2320 <0x120C44C0>,
2321 <0x120C44E0>;
2322 dma-awwrapper = <0x120C4404>,
2323 <0x120C4424>,
2324 <0x120C4444>,
2325 <0x120C4464>,
2326 <0x120C4484>,
2327 <0x120C44A4>,
2328 <0x120C44C4>,
2329 <0x120C44E4>;
2330 dma-instwrapper = <0x120C4500>;
2331 dma-mask-bit = <36>;
2332 coherent-mask-bit = <36>;
2333 };
2334 };
2335
2336 watchdog_cl0@10050000 {
2337 compatible = "samsung,exynos7-wdt";
2338 reg = <0x0 0x10050000 0x100>;
2339 interrupts = <0 232 0>;
2340 clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER0_QCH>;
2341 clock-names = "rate_watchdog", "gate_watchdog";
2342 timeout-sec = <30>;
2343 samsung,syscon-phandle = <&pmu_system_controller>;
2344 index = <0>; /* if little cluster then index is 0*/
2345 };
2346
2347 exynos_adc: adc@11C30000 {
2348 compatible = "samsung,exynos-adc-v3";
2349 reg = <0x0 0x11C30000 0x100>;
2350 sysreg = <0x11C10000>;
2351 interrupts = <0 271 0>;
2352 #io-channel-cells = <1>;
2353 io-channel-ranges;
2354 clocks = <&clock GATE_ADC_CMGP_QCH_S0>;
2355 clock-names = "gate_adcif";
2356 };
2357
2358 rtc@11A20000 {
2359 compatible = "samsung,exynos8-rtc";
2360 reg = <0x0 0x11A20000 0x100>;
2361 interrupts = <0 29 0>, <0 30 0>;
2362 use-chub-only;
2363 };
2364
2365 sec_pwm: pwm@13970000 {
2366 compatible = "samsung,s3c6400-pwm";
2367 reg = <0x0 0x13970000 0x1000>;
2368 samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
2369 #pwm-cells = <3>;
2370 clocks = <&clock GATE_PWM_MOTOR_QCH>, <&clock OSCCLK>;
2371 clock-names = "pwm_pclk", "pwm_sclk";
2372 status = "ok";
2373 };
2374
2375 dpp_0: dpp@0x14884000 { /* GF */
2376 compatible = "samsung,exynos9-dpp";
2377 #pb-id-cells = <3>;
2378 /* DPP, DPU_DMA, DPU_DMA_COMMON */
2379 reg = <0x0 0x14884000 0x1000>, <0x0 0x14895000 0x1000>, <0x0 0x14880000 0x110>;
2380 /* DPU_DMA IRQ, DPP IRQ */
2381 interrupts = <0 210 0>, <0 214 0>;
2382 attr = <0x50087>; /* DPP/IDMA/HDR10/FLIP/BLOCK/AFBC */
2383 port = <0>; /* AXI port number */
2384 };
2385
2386 dpp_1: dpp@0x14883000 { /* VG0 */
2387 compatible = "samsung,exynos9-dpp";
2388 #pb-id-cells = <3>;
2389 reg = <0x0 0x14883000 0x1000>, <0x0 0x14896000 0x1000>;
2390 interrupts = <0 211 0>, <0 215 0>;
2391 attr = <0x500B6>; /* DPP/IDMA/HDR10/SCALE/CSC/FLIP/BLOCK */
2392 port = <0>; /* AXI port number */
2393 };
2394
2395 dpp_2: dpp@0x14881000 { /* G0 */
2396 compatible = "samsung,exynos9-dpp";
2397 #pb-id-cells = <3>;
2398 reg = <0x0 0x14881000 0x1000>, <0x0 0x14891000 0x1000>;
2399 interrupts = <0 208 0>, <0 212 0>;
2400 attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */
2401 port = <0>; /* AXI port number */
2402 };
2403
2404 dpp_3: dpp@0x14882000 { /* G1 */
2405 compatible = "samsung,exynos9-dpp";
2406 #pb-id-cells = <3>;
2407 reg = <0x0 0x14882000 0x1000>, <0x0 0x14892000 0x1000>;
2408 interrupts = <0 209 0>, <0 213 0>;
2409 attr = <0x50006>; /* DPP/IDMA/FLIP/BLOCK */
2410 port = <0>; /* AXI port number */
2411 };
2412
2413 disp_ss: disp_ss@0x14810000 { /* SYSREG_DISPAUD */
2414 compatible = "samsung,exynos9-disp_ss";
2415 reg = <0x0 0x14811000 0x10>;
2416 };
2417
2418 mipi_phy_dsim: phy_m4s4top_dsi0@0x11860000 {
2419 compatible = "samsung,mipi-phy-m4s4-top";
2420 samsung,pmu-syscon = <&pmu_system_controller>;
2421 isolation = <0x070C>;
2422 /* PHY reset be controlled from DSIM */
2423 /* reg = <0x0 0x14811008 0x4>; */
2424 /* reset = <0 1>; */
2425 /* init = <4 5>; */ /* PHY reset control path bit of SYSREG */
2426 owner = <0>; /* 0: DSI, 1: CSI */
2427 #phy-cells = <1>;
2428 };
2429
2430 dsim_0: dsim@0x148E0000 {
2431 compatible = "samsung,exynos9-dsim";
2432 reg = <0x0 0x148E0000 0x100>;
2433 interrupts = <0 204 0>;
2434 iommus = <&sysmmu_dpu>;
2435 phys = <&mipi_phy_dsim 0>;
2436 phy-names = "dsim_dphy";
2437
2438 /* clock */
2439 clock-names = "aclk";
2440 clocks = <&clock UMUX_CLKCMU_DISPAUD_BUS>;
2441 };
2442
2443 decon_f: decon_f@0x148B0000 {
2444 compatible = "samsung,exynos9-decon"; /* exynos9810 */
2445 #pb-id-cells = <4>;
2446 reg = <0x0 0x148B0000 0x10000>;
2447
2448 /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA, GPIO_PERIC1(EXT_INT_TE: GPD0[0]) */
2449 interrupts = <0 199 0>,
2450 <0 200 0>,
2451 <0 203 0>,
2452 <0 266 0>;
2453
2454 /* pinctrl */
2455 pinctrl-names = "hw_te_on", "hw_te_off";
2456 pinctrl-0 = <&decon_f_te_on>;
2457 pinctrl-1 = <&decon_f_te_off>;
2458
2459 max_win = <4>;
2460 default_win = <0>;
2461 default_idma = <0>;
2462 psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
2463 trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
2464 dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
2465
2466 /* 0: DSI, 1: eDP, 2:HDMI, 3: WB */
2467 out_type = <0>;
2468 /* 0: DSI0, 1: DSI1, 2: DSI2 */
2469 out_idx = <0>;
2470
2471 /* power domain */
2472 pd_name = "pd-dispaud";
2473
2474 /* pixel per clock */
2475 ppc = <1>;
2476
2477 #address-cells = <2>;
2478 #size-cells = <1>;
2479 ranges;
2480
2481 /* EINT for TE */
2482 gpios = <&gpc2 3 0xf>;
2483 /* sw te pending register */
2484 te_eint {
2485 /* NWEINT_GPD0_PEND */
2486 reg = <0x0 0x139B0a14 0x4>;
2487 };
2488
2489 cam-stat {
2490 /* ISPPRE_STATUS(0x1406404C), ISPHQ_STATUS(0x14064054), ISPLP_STATUS(0x1406405C) */
2491 reg = <0x0 0x11864024 0x4>;
2492 };
2493 };
2494
2495 udc: usb@13200000 {
2496 compatible = "samsung,exynos-dwusb";
2497 clocks = <&clock GATE_USB30DRD_QCH_USB30>;
2498 clock-names = "hsdrd";
2499 reg = <0x0 0x13200000 0x10000>;
2500 #address-cells = <2>;
2501 #size-cells = <1>;
2502 ranges;
2503 status = "disabled";
2504
2505 usbdrd_dwc3: dwc3 {
2506 compatible = "synopsys,dwc3";
2507 reg = <0x0 0x13200000 0x10000>;
2508 interrupts = <0 186 0>;
2509 //suspend_clk_freq = <66000000>;
2510 tx-fifo-resize = <0>;
2511 adj-sof-accuracy = <0>;
2512 is_not_vbus_pad = <1>;
2513 enable_sprs_transfer = <1>;
2514 qos_int_level = <100000 200000>;
2515 phys = <&usbdrd_phy 0>, <&usbdrd3_phy 1>;
2516 phy-names = "usb2-phy", "usb3-phy";
2517 /* check susphy support */
2518 xhci_l2_support = <0>;
2519 /* support usb audio offloading: 1, if not: 0 */
2520 usb_audio_offloading = <0>;
2521 /* don't support USB L2 sleep */
2522 ldos = <0>;
2523 /*
2524 * dis-u2-freeclk-exists-quirk, dis_u2_susphy_quirk are alternative.
2525 * One of them should be selected
2526 */
2527 snps,dis-u2-freeclk-exists-quirk;
2528 /* snps,dis_u2_susphy_quirk; */
2529 };
2530 };
2531
2532 usbdrd_phy: phy@131D0000 {
2533 compatible = "samsung,exynos-usbdrd-phy";
2534 reg = <0x0 0x131D0000 0x200>;
2535 clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>,
2536 <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>,
2537 <&clock OSCCLK>;
2538 clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk";
2539 samsung,pmu-syscon = <&pmu_system_controller>;
2540 pmu_mask = <0x3>;
2541 pmu_offset = <0x704>;
2542 //pmu_offset_dp = <0x66c>;
2543
2544 /* USBDP combo phy version - 0x200 */
2545 phy_version = <0x300>;
2546 /* if it doesn't need phy user mux, */
2547 /* you should write "none" */
2548 /* but refclk shouldn't be omitted */
2549 phyclk_mux = "none";
2550 phy_refclk = "oscclk";
2551
2552 /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */
2553 has_other_phy = <0>;
2554 /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */
2555 has_combo_phy = <0>;
2556 sub_phy_version = <0x300>;
2557
2558 /* ip type */
2559 /* USB3DRD = 0 */
2560 /* USB3HOST = 1 */
2561 /* USB2DRD = 2 */
2562 /* USB2HOST = 3 */
2563 ip_type = <0x2>;
2564
2565 /* for PHY CAL */
2566 /* choice only one item */
2567 phy_refsel_clockcore = <1>;
2568 phy_refsel_ext_osc = <0>;
2569 phy_refsel_xtal = <0>;
2570 phy_refsel_diff_pad = <0>;
2571 phy_refsel_diff_internal = <0>;
2572 phy_refsel_diff_single = <0>;
2573
2574 /* true : 1 , false : 0 */
2575 use_io_for_ovc = <0>;
2576 common_block_disable = <1>;
2577 is_not_vbus_pad = <1>;
2578 used_phy_port = <0>;
2579
2580 status = "disabled";
2581
2582 #phy-cells = <1>;
2583 ranges;
2584 };
2585
2586 usbdrd3_phy: phy@131F0000 {
2587 compatible = "samsung,exynos-usbdrd-phy";
2588 reg = <0x0 0x131F0000 0x1000>,
2589 <0x0 0x131E0000 0x800>;
2590 clocks = <&clock GATE_USB30DRD_QCH_USB30>, <&clock GATE_USB30DRD_QCH_USBPHY_20CTRL>,
2591 <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_0>, <&clock GATE_USB30DRD_QCH_USBPHY_30CTRL_1>,
2592 <&clock OSCCLK>;
2593 clock-names = "hsdrd", "usb20", "usb30_0", "usb30_1", "oscclk";
2594 samsung,pmu-syscon = <&pmu_system_controller>;
2595 pmu_mask = <0x3>;
2596 pmu_offset = <0x704>;
2597 //pmu_offset_dp = <0x66c>;
2598
2599 /* USBDP combo phy version - 0x200 */
2600 phy_version = <0x530>;
2601 /* if it doesn't need phy user mux, */
2602 /* you should write "none" */
2603 /* but refclk shouldn't be omitted */
2604 phyclk_mux = "none";
2605 phy_refclk = "oscclk";
2606
2607 /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */
2608 has_other_phy = <1>;
2609 /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */
2610 has_combo_phy = <0>;
2611 sub_phy_version = <0x300>;
2612
2613 /* ip type */
2614 /* USB3DRD = 0 */
2615 /* USB3HOST = 1 */
2616 /* USB2DRD = 2 */
2617 /* USB2HOST = 3 */
2618 ip_type = <0x0>;
2619
2620 /* for PHY CAL */
2621 /* choice only one item */
2622 phy_refsel_clockcore = <1>;
2623 phy_refsel_ext_osc = <0>;
2624 phy_refsel_xtal = <0>;
2625 phy_refsel_diff_pad = <0>;
2626 phy_refsel_diff_internal = <0>;
2627 phy_refsel_diff_single = <0>;
2628
2629 /* true : 1 , false : 0 */
2630 use_io_for_ovc = <0>;
2631 common_block_disable = <1>;
2632 is_not_vbus_pad = <1>;
2633 used_phy_port = <0>;
2634
2635 status = "disabled";
2636
2637 #phy-cells = <1>;
2638 ranges;
2639 };
2640
2641
2642 iommu-domain_dpu {
2643 compatible = "samsung,exynos-iommu-bus";
2644 #address-cells = <2>;
2645 #size-cells = <1>;
2646 ranges;
2647
2648 domain-clients = <&dsim_0>;
2649 };
2650
2651 iommu-domain_vipx {
2652 compatible = "samsung,exynos-iommu-bus";
2653 #address-cells = <2>;
2654 #size-cells = <1>;
2655 ranges;
2656
2657 domain-clients = <>;
2658 };
2659
2660 iommu-domain_abox {
2661 compatible = "samsung,exynos-iommu-bus";
2662 #address-cells = <2>;
2663 #size-cells = <1>;
2664 ranges;
2665
2666 domain-clients = <>;
2667 };
2668
2669 iommu-domain_isp {
2670 compatible = "samsung,exynos-iommu-bus";
2671 #address-cells = <2>;
2672 #size-cells = <1>;
2673 ranges;
2674
2675 domain-clients = <>;
2676 };
2677
2678 iommu-domain_mfc {
2679 compatible = "samsung,exynos-iommu-bus";
2680 #address-cells = <2>;
2681 #size-cells = <1>;
2682 ranges;
2683
2684 domain-clients = <&mfc_0>;
2685 };
2686
2687 iommu-domain_g2dmscljpeg {
2688 compatible = "samsung,exynos-iommu-bus";
2689 #address-cells = <2>;
2690 #size-cells = <1>;
2691 ranges;
2692
2693 domain-clients = <&fimg2d>, <&scaler_0>, <&smfc>;
2694 };
2695
2696 fimg2d: g2d@12E40000 {
2697 compatible = "samsung,exynos9610-g2d";
2698 reg = <0x0 0x12E40000 0x9000>;
2699 interrupts = <0 165 0>;
2700 clock-names = "gate";
2701 clocks = <&clock GATE_G2D_QCH>;
2702 iommus = <&sysmmu_g2d>;
2703 hw_ppc =
2704 /* sc_up none x1 x1/4 x1/9 x1/16 */
2705 <1700 1550 1100 1800 2550 3500 /* rgb32 non-rotated */
2706 1650 1350 1000 1500 2600 3250 /* rgb32 rotated */
2707 1500 1450 1300 1700 2550 5950 /* yuv2p non-rotated */
2708 1600 1000 950 1650 2600 3500 /* yuv2p rotated */
2709 1200 950 950 1350 1550 2050 /* 8+2 non-rotated */
2710 1250 450 450 1100 1450 1850 /* 8+2 rotated */
2711 1900>; /* colorfill */
2712
2713 g2d_dvfs_table = <667000 667000
2714 533000 533000
2715 400000 400000
2716 200000 200000
2717 100000 100000
2718 >;
2719 dma-coherent;
2720 };
2721
2722 scaler_0: scaler@12E60000 {
2723 compatible = "samsung,exynos5-scaler";
2724 reg = <0x0 0x12E60000 0x3000>;
2725 interrupts = <0 164 0>;
2726 clocks = <&clock GATE_MSCL_QCH>;
2727 clock-names = "gate";
2728 iommus = <&sysmmu_g2d>;
2729 };
2730
2731 smfc: smfc@12E30000 {
2732 compatible = "samsung,exynos7870-jpeg";
2733 dma-coherent;
2734 reg = <0x0 0x12E30000 0x1000>;
2735 interrupts = <0 163 0>;
2736 clocks = <&clock GATE_JPEG_QCH>;
2737 clock-names = "gate";
2738 iommus = <&sysmmu_g2d>;
2739 smfc,int_qos_minlock = <534000>;
2740 };
2741
2742 /* G3D */
2743 mali: mali@11500000 {
2744 compatible = "arm,mali";
2745 reg = <0x0 0x11500000 0x5000>;
2746 interrupts = <0 66 0>, <0 67 0>, <0 65 0>;
2747 interrupt-names = "JOB", "MMU", "GPU";
2748 g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
2749 samsung,power-domain = <&pd_g3d>;
2750 #cooling-cells = <2>; /* min followed by max */
2751 };
2752
2753 reboot {
2754 compatible = "exynos,reboot";
2755 pmu_base = <0x11860000>;
2756 };
2757
2758 schedutil_gov {
2759 schedutil_domain0: domain@0 {
2760 device_type = "schedutil-domain";
2761 shared-cpus = "0-3";
2762 enabled = <0>; /* Disabled */
2763 qos_min_class = <3>;
2764 };
2765
2766 schedutil_domain1: domain@1 {
2767 device_type = "schedutil-domain";
2768 shared-cpus = "4-7";
2769 enabled = <1>; /* Enabled */
2770 expired_time = <80>; /* 80ms */
2771 qos_min_class = <5>;
2772 };
2773 };
2774
2775 schedutil {
2776 domain@0 {
2777 device_type = "freqvar-tune";
2778 shared-cpus = "0-3";
2779
2780 boost_table = < 0 >;
2781 up_rate_limit_table = < 5 >;
2782 down_rate_limit_table = < 5 >;
2783 upscale_ratio_table = < 80 >;
2784 };
2785
2786 domain@1 {
2787 device_type = "freqvar-tune";
2788 shared-cpus = "4-7";
2789
2790 boost_table = < 0 >;
2791 up_rate_limit_table = < 5 >;
2792 down_rate_limit_table = < 5 >;
2793 upscale_ratio_table = < 80 >;
2794 };
2795 };
2796
2797 cpufreq {
2798 cpufreq_domain0: domain@0 {
2799 device_type = "cpufreq-domain";
2800 sibling-cpus = "0-3";
2801 cal-id = <ACPM_DVFS_CPUCL0>;
2802 dm-type = <DM_CPU_CL0>;
2803
2804 min-freq = <403000>;
2805
2806 /* PM QoS Class ID */
2807 pm_qos-min-class = <3>;
2808 pm_qos-max-class = <4>;
2809
2810 #cooling-cells = <2>; /* min followed by max */
2811
2812 dm-constraints {
2813 mif-perf {
2814 const-type = <CONSTRAINT_MIN>;
2815 dm-type = <DM_MIF>;
2816 /* cpu mif */
2817 table = < 1534000 845000
2818 1456000 845000
2819 1326000 845000
2820 1222000 676000
2821 1118000 676000
2822 1053000 676000
2823 910000 676000
2824 806000 546000
2825 702000 546000
2826 598000 419000
2827 403000 0
2828 >;
2829 };
2830 };
2831 };
2832
2833 cpufreq_domain1: domain@1 {
2834 device_type = "cpufreq-domain";
2835 sibling-cpus = "4-7";
2836 cal-id = <ACPM_DVFS_CPUCL1>;
2837 dm-type = <DM_CPU_CL1>;
2838
2839 min-freq = <936000>;
2840 max-freq = <2288000>;
2841
2842 /* PM QoS Class ID */
2843 pm_qos-min-class = <5>;
2844 pm_qos-max-class = <6>;
2845
2846 #cooling-cells = <2>; /* min followed by max */
2847
2848 dm-constraints {
2849 mif-perf {
2850 const-type = <CONSTRAINT_MIN>;
2851 dm-type = <DM_MIF>;
2852 /* cpu mif */
2853 table = < 2392000 1794000
2854 2288000 1794000
2855 2184000 1794000
2856 2080000 1539000
2857 1976000 1539000
2858 1898000 1539000
2859 1768000 1352000
2860 1664000 1014000
2861 1508000 1014000
2862 1456000 845000
2863 1352000 845000
2864 1248000 676000
2865 1144000 676000
2866 1040000 546000
2867 936000 546000
2868 832000 546000
2869 728000 546000 >;
2870 };
2871 };
2872 };
2873 };
2874
2875 /* Secure log */
2876 seclog {
2877 compatible = "samsung,exynos-seclog";
2878 interrupts = <0 455 0>;
2879 };
2880
2881 /* tbase */
2882 tee {
2883 compatible = "samsung,exynos-tee";
2884 interrupts = <0 454 0>;
2885 };
2886 baaw_p_wlbt: syscon@12050000 {
2887 compatible = "baaw_p_wlbt", "syscon";
2888 reg = <0x0 0x12050000 0xff>;
2889 };
2890
2891 dbus_baaw: syscon@14C20000 {
2892 compatible = "dbus_baaw", "syscon";
2893 reg = <0x0 0x14C20000 0x300>;
2894 };
2895
2896 pbus_baaw: syscon@14C30000 {
2897 compatible = "pbus_baaw", "syscon";
2898 reg = <0x0 0x14C30000 0x300>;
2899 };
2900
2901 wlbt_remap_base: syscon@14C50000 {
2902 compatible = "wlbt_remap", "syscon";
2903 reg = <0x0 0x14C50000 0x300>;
2904 };
2905
2906 boot_cfg: syscon@14C60000 {
2907 compatible = "boot_cfg", "syscon";
2908 reg = <0x0 0x14C60000 0x1100>;
2909 };
2910
2911 /* MAILBOX_AP2WLBT */
2912 scsc_wifibt: scsc_wifibt@119c0000 {
2913 compatible = "samsung,scsc_wifibt";
2914 /* Mailbox Registers */
2915 reg = <0x0 0x119c0000 0x180>;
2916 /* 10.3.2 External GIC IRQ table */
2917 //SPI[42] 74 BLK_ALIVE INTREQ__MAILBOX_WLBT2AP
2918 //SPI[28] 60 BLK_ALIVE INTREQ__ALIVE_WLBT_ACTIVE
2919 //SPI[72] 104 BLK_WLBT WB2AP_WDOG_RESET_REQ__ALV
2920 //SPI[73] 105 BLK_WLBT WB2AP_CFG_REQ__ALV
2921 interrupts = <0 42 4>, <0 28 4>, <0 72 4>, <0 73 4>;
2922 interrupt-names = "MBOX","ALIVE","WDOG","CFG_REQ";
2923 /* PMU alive handle */
2924 samsung,syscon-phandle = <&pmu_system_controller>;
2925 samsung,baaw_p_wlbt-syscon-phandle = <&baaw_p_wlbt>;
2926 samsung,dbus_baaw-syscon-phandle = <&dbus_baaw>;
2927 samsung,pbus_baaw-syscon-phandle = <&pbus_baaw>;
2928 samsung,wlbt_remap-syscon-phandle = <&wlbt_remap_base>;
2929 samsung,boot_cfg-syscon-phandle = <&boot_cfg>;
2930 /* MIF / INT / CL0 / CL1 */
2931 /* this qos_table should be per-platform. Leave it here until we have multiple platfrom support */
2932 qos_table = <
2933 419000 100000 403000 728000 /* SCSC_QOS_MIN */
2934 1014000 533000 910000 1664000 /* SCSC_QOS_MED */
2935 2093000 667000 1534000 2392000 /* SCSC_QOS_MAX */
2936 >;
2937 /* SMAPPER */
2938 smapper_num_banks = <11>;
2939 smapper_reg = <0x14c40000 0x10000>;
2940 smapper_bank_table {
2941 smapper_bank_0 {
2942 bank_num = <0x0>;
2943 fw_window_start = <0x82000000>;
2944 fw_window_size = <0x100000>;
2945 num_entries = <160>;
2946 is_large = <1>;
2947 };
2948 smapper_bank_1 {
2949 bank_num = <0x1>;
2950 fw_window_start = <0x82100000>;
2951 fw_window_size = <0x100000>;
2952 num_entries = <160>;
2953 is_large = <1>;
2954 };
2955 smapper_bank_2 {
2956 bank_num = <0x2>;
2957 fw_window_start = <0x82200000>;
2958 fw_window_size = <0x100000>;
2959 num_entries = <160>;
2960 is_large = <1>;
2961 };
2962 smapper_bank_3 {
2963 bank_num = <0x3>;
2964 fw_window_start = <0x82300000>;
2965 fw_window_size = <0x100000>;
2966 num_entries = <160>;
2967 is_large = <1>;
2968 };
2969 smapper_bank_4 {
2970 bank_num = <0x4>;
2971 fw_window_start = <0x83000000>;
2972 fw_window_size = <0x100000>;
2973 num_entries = <64>;
2974 is_large = <0>;
2975 };
2976 smapper_bank_5 {
2977 bank_num = <0x5>;
2978 fw_window_start = <0x83100000>;
2979 fw_window_size = <0x100000>;
2980 num_entries = <64>;
2981 is_large = <0>;
2982 };
2983 smapper_bank_6 {
2984 bank_num = <0x6>;
2985 fw_window_start = <0x83200000>;
2986 fw_window_size = <0x100000>;
2987 num_entries = <64>;
2988 is_large = <0>;
2989 };
2990 smapper_bank_7 {
2991 bank_num = <0x7>;
2992 fw_window_start = <0x83300000>;
2993 fw_window_size = <0x100000>;
2994 num_entries = <64>;
2995 is_large = <0>;
2996 };
2997 smapper_bank_8 {
2998 bank_num = <0x8>;
2999 fw_window_start = <0x83400000>;
3000 fw_window_size = <0x100000>;
3001 num_entries = <64>;
3002 is_large = <0>;
3003 };
3004 smapper_bank_9 {
3005 bank_num = <0x9>;
3006 fw_window_start = <0x83500000>;
3007 fw_window_size = <0x100000>;
3008 num_entries = <64>;
3009 is_large = <0>;
3010 };
3011 smapper_bank_10 {
3012 bank_num = <0xa>;
3013 fw_window_start = <0x83600000>;
3014 fw_window_size = <0x100000>;
3015 num_entries = <64>;
3016 is_large = <0>;
3017 };
3018 };
3019 };
3020
3021 fm@14AC0000 {
3022 compatible = "samsung,exynos9610-fm";
3023 reg = <0x0 0x14AC0000 0x2000>,
3024 <0x0 0x14800800 0x10>;
3025 elna_gpio = <&gpg1 0 0x1>; /* FM_LNA_EN */
3026 pinctrl-names = "default";
3027 pinctrl-0 = <&fm_lna_en>;
3028 clocks = <&clock MUX_AUD_FM>,
3029 <&clock GATE_ABOX_QCH_FM>,
3030 <&clock DOUT_CLK_AUD_FM>; /* mux_aud_fm, qch_fm, clk_aud_fm */
3031 clock-names = "mux_aud_fm", "qch_fm", "clk_aud_fm";
3032 without_elna = <1>;
3033 samsung,syscon-phandle = <&pmu_system_controller>;
3034 samsung,power-domain = <&pd_dispaud>;
3035 status = "disabled";
3036 };
3037 };
Motorola kernel-slsi