arch/arm64/Kconfig

   1 config ARM64
   2         def_bool y
   3         select ACPI_CCA_REQUIRED if ACPI
   4         select ACPI_GENERIC_GSI if ACPI
   5         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   6         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   7         select ARCH_HAS_ELF_RANDOMIZE
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_HAS_SG_CHAIN
  10         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  11         select ARCH_USE_CMPXCHG_LOCKREF
  12         select ARCH_SUPPORTS_ATOMIC_RMW
  13         select ARCH_WANT_OPTIONAL_GPIOLIB
  14         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
  15         select ARCH_WANT_FRAME_POINTERS
  16         select ARCH_HAS_UBSAN_SANITIZE_ALL
  17         select ARM_AMBA
  18         select ARM_ARCH_TIMER
  19         select ARM_GIC
  20         select AUDIT_ARCH_COMPAT_GENERIC
  21         select ARM_GIC_V2M if PCI_MSI
  22         select ARM_GIC_V3
  23         select ARM_GIC_V3_ITS if PCI_MSI
  24         select ARM_PSCI_FW
  25         select BUILDTIME_EXTABLE_SORT
  26         select CLONE_BACKWARDS
  27         select COMMON_CLK
  28         select CPU_PM if (SUSPEND || CPU_IDLE)
  29         select DCACHE_WORD_ACCESS
  30         select EDAC_SUPPORT
  31         select FRAME_POINTER
  32         select GENERIC_ALLOCATOR
  33         select GENERIC_CLOCKEVENTS
  34         select GENERIC_CLOCKEVENTS_BROADCAST
  35         select GENERIC_CPU_AUTOPROBE
  36         select GENERIC_EARLY_IOREMAP
  37         select GENERIC_IDLE_POLL_SETUP
  38         select GENERIC_IRQ_PROBE
  39         select GENERIC_IRQ_SHOW
  40         select GENERIC_IRQ_SHOW_LEVEL
  41         select GENERIC_PCI_IOMAP
  42         select GENERIC_SCHED_CLOCK
  43         select GENERIC_SMP_IDLE_THREAD
  44         select GENERIC_STRNCPY_FROM_USER
  45         select GENERIC_STRNLEN_USER
  46         select GENERIC_TIME_VSYSCALL
  47         select HANDLE_DOMAIN_IRQ
  48         select HARDIRQS_SW_RESEND
  49         select HAVE_ALIGNED_STRUCT_PAGE if SLUB
  50         select HAVE_ARCH_AUDITSYSCALL
  51         select HAVE_ARCH_BITREVERSE
  52         select HAVE_ARCH_HARDENED_USERCOPY
  53         select HAVE_ARCH_HUGE_VMAP
  54         select HAVE_ARCH_JUMP_LABEL
  55         select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
  56         select HAVE_ARCH_KGDB
  57         select HAVE_ARCH_MMAP_RND_BITS
  58         select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
  59         select HAVE_ARCH_SECCOMP_FILTER
  60         select HAVE_ARCH_TRACEHOOK
  61         select HAVE_BPF_JIT
  62         select HAVE_C_RECORDMCOUNT
  63         select HAVE_CC_STACKPROTECTOR
  64         select HAVE_CMPXCHG_DOUBLE
  65         select HAVE_CMPXCHG_LOCAL
  66         select HAVE_DEBUG_BUGVERBOSE
  67         select HAVE_DEBUG_KMEMLEAK
  68         select HAVE_DMA_API_DEBUG
  69         select HAVE_DMA_ATTRS
  70         select HAVE_DMA_CONTIGUOUS
  71         select HAVE_DYNAMIC_FTRACE
  72         select HAVE_EFFICIENT_UNALIGNED_ACCESS
  73         select HAVE_FTRACE_MCOUNT_RECORD
  74         select HAVE_FUNCTION_TRACER
  75         select HAVE_FUNCTION_GRAPH_TRACER
  76         select HAVE_GENERIC_DMA_COHERENT
  77         select HAVE_HW_BREAKPOINT if PERF_EVENTS
  78         select HAVE_IRQ_TIME_ACCOUNTING
  79         select HAVE_MEMBLOCK
  80         select HAVE_PATA_PLATFORM
  81         select HAVE_PERF_EVENTS
  82         select HAVE_PERF_REGS
  83         select HAVE_PERF_USER_STACK_DUMP
  84         select HAVE_RCU_TABLE_FREE
  85         select HAVE_SYSCALL_TRACEPOINTS
  86         select IOMMU_DMA if IOMMU_SUPPORT
  87         select IRQ_DOMAIN
  88         select IRQ_FORCED_THREADING
  89         select MODULES_USE_ELF_RELA
  90         select NO_BOOTMEM
  91         select OF
  92         select OF_EARLY_FLATTREE
  93         select OF_RESERVED_MEM
  94         select PERF_USE_VMALLOC
  95         select POWER_RESET
  96         select POWER_SUPPLY
  97         select RTC_LIB
  98         select SPARSE_IRQ
  99         select SYSCTL_EXCEPTION_TRACE
 100         select HAVE_CONTEXT_TRACKING
 101         help
 102           ARM 64-bit (AArch64) Linux support.
 103
 104 config 64BIT
 105         def_bool y
 106
 107 config ARCH_PHYS_ADDR_T_64BIT
 108         def_bool y
 109
 110 config MMU
 111         def_bool y
 112
 113 config ARCH_MMAP_RND_BITS_MIN
 114        default 14 if ARM64_64K_PAGES
 115        default 16 if ARM64_16K_PAGES
 116        default 18
 117
 118 # max bits determined by the following formula:
 119 #  VA_BITS - PAGE_SHIFT - 3
 120 config ARCH_MMAP_RND_BITS_MAX
 121        default 19 if ARM64_VA_BITS=36
 122        default 24 if ARM64_VA_BITS=39
 123        default 27 if ARM64_VA_BITS=42
 124        default 30 if ARM64_VA_BITS=47
 125        default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 126        default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 127        default 33 if ARM64_VA_BITS=48
 128        default 14 if ARM64_64K_PAGES
 129        default 16 if ARM64_16K_PAGES
 130        default 18
 131
 132 config ARCH_MMAP_RND_COMPAT_BITS_MIN
 133        default 7 if ARM64_64K_PAGES
 134        default 9 if ARM64_16K_PAGES
 135        default 11
 136
 137 config ARCH_MMAP_RND_COMPAT_BITS_MAX
 138        default 16
 139
 140 config NO_IOPORT_MAP
 141         def_bool y if !PCI
 142
 143 config ILLEGAL_POINTER_VALUE
 144         hex
 145         default 0xdead000000000000
 146
 147 config STACKTRACE_SUPPORT
 148         def_bool y
 149
 150 config ILLEGAL_POINTER_VALUE
 151         hex
 152         default 0xdead000000000000
 153
 154 config LOCKDEP_SUPPORT
 155         def_bool y
 156
 157 config TRACE_IRQFLAGS_SUPPORT
 158         def_bool y
 159
 160 config RWSEM_XCHGADD_ALGORITHM
 161         def_bool y
 162
 163 config GENERIC_BUG
 164         def_bool y
 165         depends on BUG
 166
 167 config GENERIC_BUG_RELATIVE_POINTERS
 168         def_bool y
 169         depends on GENERIC_BUG
 170
 171 config GENERIC_HWEIGHT
 172         def_bool y
 173
 174 config GENERIC_CSUM
 175         def_bool y
 176
 177 config GENERIC_CALIBRATE_DELAY
 178         def_bool y
 179
 180 config ZONE_DMA
 181         def_bool y
 182
 183 config HAVE_GENERIC_RCU_GUP
 184         def_bool y
 185
 186 config ARCH_DMA_ADDR_T_64BIT
 187         def_bool y
 188
 189 config NEED_DMA_MAP_STATE
 190         def_bool y
 191
 192 config NEED_SG_DMA_LENGTH
 193         def_bool y
 194
 195 config SMP
 196         def_bool y
 197
 198 config SWIOTLB
 199         def_bool y
 200
 201 config IOMMU_HELPER
 202         def_bool SWIOTLB
 203
 204 config KERNEL_MODE_NEON
 205         def_bool y
 206
 207 config FIX_EARLYCON_MEM
 208         def_bool y
 209
 210 config PGTABLE_LEVELS
 211         int
 212         default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 213         default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 214         default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
 215         default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 216         default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 217         default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 218
 219 source "init/Kconfig"
 220
 221 source "kernel/Kconfig.freezer"
 222
 223 source "arch/arm64/Kconfig.platforms"
 224
 225 menu "Bus support"
 226
 227 config PCI
 228         bool "PCI support"
 229         help
 230           This feature enables support for PCI bus system. If you say Y
 231           here, the kernel will include drivers and infrastructure code
 232           to support PCI bus devices.
 233
 234 config PCI_DOMAINS
 235         def_bool PCI
 236
 237 config PCI_DOMAINS_GENERIC
 238         def_bool PCI
 239
 240 config PCI_SYSCALL
 241         def_bool PCI
 242
 243 source "drivers/pci/Kconfig"
 244 source "drivers/pci/pcie/Kconfig"
 245 source "drivers/pci/hotplug/Kconfig"
 246
 247 endmenu
 248
 249 menu "Kernel Features"
 250
 251 menu "ARM errata workarounds via the alternatives framework"
 252
 253 config ARM64_ERRATUM_826319
 254         bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 255         default y
 256         help
 257           This option adds an alternative code sequence to work around ARM
 258           erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 259           AXI master interface and an L2 cache.
 260
 261           If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 262           and is unable to accept a certain write via this interface, it will
 263           not progress on read data presented on the read data channel and the
 264           system can deadlock.
 265
 266           The workaround promotes data cache clean instructions to
 267           data cache clean-and-invalidate.
 268           Please note that this does not necessarily enable the workaround,
 269           as it depends on the alternative framework, which will only patch
 270           the kernel if an affected CPU is detected.
 271
 272           If unsure, say Y.
 273
 274 config ARM64_ERRATUM_827319
 275         bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 276         default y
 277         help
 278           This option adds an alternative code sequence to work around ARM
 279           erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 280           master interface and an L2 cache.
 281
 282           Under certain conditions this erratum can cause a clean line eviction
 283           to occur at the same time as another transaction to the same address
 284           on the AMBA 5 CHI interface, which can cause data corruption if the
 285           interconnect reorders the two transactions.
 286
 287           The workaround promotes data cache clean instructions to
 288           data cache clean-and-invalidate.
 289           Please note that this does not necessarily enable the workaround,
 290           as it depends on the alternative framework, which will only patch
 291           the kernel if an affected CPU is detected.
 292
 293           If unsure, say Y.
 294
 295 config ARM64_ERRATUM_824069
 296         bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 297         default y
 298         help
 299           This option adds an alternative code sequence to work around ARM
 300           erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 301           to a coherent interconnect.
 302
 303           If a Cortex-A53 processor is executing a store or prefetch for
 304           write instruction at the same time as a processor in another
 305           cluster is executing a cache maintenance operation to the same
 306           address, then this erratum might cause a clean cache line to be
 307           incorrectly marked as dirty.
 308
 309           The workaround promotes data cache clean instructions to
 310           data cache clean-and-invalidate.
 311           Please note that this option does not necessarily enable the
 312           workaround, as it depends on the alternative framework, which will
 313           only patch the kernel if an affected CPU is detected.
 314
 315           If unsure, say Y.
 316
 317 config ARM64_ERRATUM_819472
 318         bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 319         default y
 320         help
 321           This option adds an alternative code sequence to work around ARM
 322           erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 323           present when it is connected to a coherent interconnect.
 324
 325           If the processor is executing a load and store exclusive sequence at
 326           the same time as a processor in another cluster is executing a cache
 327           maintenance operation to the same address, then this erratum might
 328           cause data corruption.
 329
 330           The workaround promotes data cache clean instructions to
 331           data cache clean-and-invalidate.
 332           Please note that this does not necessarily enable the workaround,
 333           as it depends on the alternative framework, which will only patch
 334           the kernel if an affected CPU is detected.
 335
 336           If unsure, say Y.
 337
 338 config ARM64_ERRATUM_832075
 339         bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 340         default y
 341         help
 342           This option adds an alternative code sequence to work around ARM
 343           erratum 832075 on Cortex-A57 parts up to r1p2.
 344
 345           Affected Cortex-A57 parts might deadlock when exclusive load/store
 346           instructions to Write-Back memory are mixed with Device loads.
 347
 348           The workaround is to promote device loads to use Load-Acquire
 349           semantics.
 350           Please note that this does not necessarily enable the workaround,
 351           as it depends on the alternative framework, which will only patch
 352           the kernel if an affected CPU is detected.
 353
 354           If unsure, say Y.
 355
 356 config ARM64_ERRATUM_834220
 357         bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 358         depends on KVM
 359         default y
 360         help
 361           This option adds an alternative code sequence to work around ARM
 362           erratum 834220 on Cortex-A57 parts up to r1p2.
 363
 364           Affected Cortex-A57 parts might report a Stage 2 translation
 365           fault as the result of a Stage 1 fault for load crossing a
 366           page boundary when there is a permission or device memory
 367           alignment fault at Stage 1 and a translation fault at Stage 2.
 368
 369           The workaround is to verify that the Stage 1 translation
 370           doesn't generate a fault before handling the Stage 2 fault.
 371           Please note that this does not necessarily enable the workaround,
 372           as it depends on the alternative framework, which will only patch
 373           the kernel if an affected CPU is detected.
 374
 375           If unsure, say Y.
 376
 377 config ARM64_ERRATUM_845719
 378         bool "Cortex-A53: 845719: a load might read incorrect data"
 379         depends on COMPAT
 380         default y
 381         help
 382           This option adds an alternative code sequence to work around ARM
 383           erratum 845719 on Cortex-A53 parts up to r0p4.
 384
 385           When running a compat (AArch32) userspace on an affected Cortex-A53
 386           part, a load at EL0 from a virtual address that matches the bottom 32
 387           bits of the virtual address used by a recent load at (AArch64) EL1
 388           might return incorrect data.
 389
 390           The workaround is to write the contextidr_el1 register on exception
 391           return to a 32-bit task.
 392           Please note that this does not necessarily enable the workaround,
 393           as it depends on the alternative framework, which will only patch
 394           the kernel if an affected CPU is detected.
 395
 396           If unsure, say Y.
 397
 398 config ARM64_ERRATUM_843419
 399         bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 400         depends on MODULES
 401         default y
 402         select ARM64_MODULE_CMODEL_LARGE
 403         help
 404           This option builds kernel modules using the large memory model in
 405           order to avoid the use of the ADRP instruction, which can cause
 406           a subsequent memory access to use an incorrect address on Cortex-A53
 407           parts up to r0p4.
 408
 409           Note that the kernel itself must be linked with a version of ld
 410           which fixes potentially affected ADRP instructions through the
 411           use of veneers.
 412
 413           If unsure, say Y.
 414
 415 config CAVIUM_ERRATUM_22375
 416         bool "Cavium erratum 22375, 24313"
 417         default y
 418         help
 419           Enable workaround for erratum 22375, 24313.
 420
 421           This implements two gicv3-its errata workarounds for ThunderX. Both
 422           with small impact affecting only ITS table allocation.
 423
 424             erratum 22375: only alloc 8MB table size
 425             erratum 24313: ignore memory access type
 426
 427           The fixes are in ITS initialization and basically ignore memory access
 428           type and table size provided by the TYPER and BASER registers.
 429
 430           If unsure, say Y.
 431
 432 config CAVIUM_ERRATUM_23154
 433         bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 434         default y
 435         help
 436           The gicv3 of ThunderX requires a modified version for
 437           reading the IAR status to ensure data synchronization
 438           (access to icc_iar1_el1 is not sync'ed before and after).
 439
 440           If unsure, say Y.
 441
 442 config CAVIUM_ERRATUM_27456
 443         bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
 444         default y
 445         help
 446           On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
 447           instructions may cause the icache to become corrupted if it
 448           contains data for a non-current ASID.  The fix is to
 449           invalidate the icache when changing the mm context.
 450
 451           If unsure, say Y.
 452
 453 endmenu
 454
 455
 456 choice
 457         prompt "Page size"
 458         default ARM64_4K_PAGES
 459         help
 460           Page size (translation granule) configuration.
 461
 462 config ARM64_4K_PAGES
 463         bool "4KB"
 464         help
 465           This feature enables 4KB pages support.
 466
 467 config ARM64_16K_PAGES
 468         bool "16KB"
 469         help
 470           The system will use 16KB pages support. AArch32 emulation
 471           requires applications compiled with 16K (or a multiple of 16K)
 472           aligned segments.
 473
 474 config ARM64_64K_PAGES
 475         bool "64KB"
 476         help
 477           This feature enables 64KB pages support (4KB by default)
 478           allowing only two levels of page tables and faster TLB
 479           look-up. AArch32 emulation requires applications compiled
 480           with 64K aligned segments.
 481
 482 endchoice
 483
 484 choice
 485         prompt "Virtual address space size"
 486         default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 487         default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 488         default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 489         help
 490           Allows choosing one of multiple possible virtual address
 491           space sizes. The level of translation table is determined by
 492           a combination of page size and virtual address space size.
 493
 494 config ARM64_VA_BITS_36
 495         bool "36-bit" if EXPERT
 496         depends on ARM64_16K_PAGES
 497
 498 config ARM64_VA_BITS_39
 499         bool "39-bit"
 500         depends on ARM64_4K_PAGES
 501
 502 config ARM64_VA_BITS_42
 503         bool "42-bit"
 504         depends on ARM64_64K_PAGES
 505
 506 config ARM64_VA_BITS_47
 507         bool "47-bit"
 508         depends on ARM64_16K_PAGES
 509
 510 config ARM64_VA_BITS_48
 511         bool "48-bit"
 512
 513 endchoice
 514
 515 config ARM64_VA_BITS
 516         int
 517         default 36 if ARM64_VA_BITS_36
 518         default 39 if ARM64_VA_BITS_39
 519         default 42 if ARM64_VA_BITS_42
 520         default 47 if ARM64_VA_BITS_47
 521         default 48 if ARM64_VA_BITS_48
 522
 523 config CPU_BIG_ENDIAN
 524        bool "Build big-endian kernel"
 525        help
 526          Say Y if you plan on running a kernel in big-endian mode.
 527
 528 config SCHED_MC
 529         bool "Multi-core scheduler support"
 530         help
 531           Multi-core scheduler support improves the CPU scheduler's decision
 532           making when dealing with multi-core CPU chips at a cost of slightly
 533           increased overhead in some places. If unsure say N here.
 534
 535 config SCHED_SMT
 536         bool "SMT scheduler support"
 537         help
 538           Improves the CPU scheduler's decision making when dealing with
 539           MultiThreading at a cost of slightly increased overhead in some
 540           places. If unsure say N here.
 541
 542 config NR_CPUS
 543         int "Maximum number of CPUs (2-4096)"
 544         range 2 4096
 545         # These have to remain sorted largest to smallest
 546         default "64"
 547
 548 config HOTPLUG_CPU
 549         bool "Support for hot-pluggable CPUs"
 550         select GENERIC_IRQ_MIGRATION
 551         help
 552           Say Y here to experiment with turning CPUs off and on.  CPUs
 553           can be controlled through /sys/devices/system/cpu.
 554
 555 source kernel/Kconfig.preempt
 556 source kernel/Kconfig.hz
 557
 558 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 559         def_bool y
 560
 561 config ARCH_HAS_HOLES_MEMORYMODEL
 562         def_bool y if SPARSEMEM
 563
 564 config ARCH_SPARSEMEM_ENABLE
 565         def_bool y
 566         select SPARSEMEM_VMEMMAP_ENABLE
 567
 568 config ARCH_SPARSEMEM_DEFAULT
 569         def_bool ARCH_SPARSEMEM_ENABLE
 570
 571 config ARCH_SELECT_MEMORY_MODEL
 572         def_bool ARCH_SPARSEMEM_ENABLE
 573
 574 config HAVE_ARCH_PFN_VALID
 575         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 576
 577 config HW_PERF_EVENTS
 578         def_bool y
 579         depends on ARM_PMU
 580
 581 config SYS_SUPPORTS_HUGETLBFS
 582         def_bool y
 583
 584 config ARCH_WANT_HUGE_PMD_SHARE
 585         def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
 586
 587 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
 588         def_bool y
 589
 590 config ARCH_HAS_CACHE_LINE_SIZE
 591         def_bool y
 592
 593 source "mm/Kconfig"
 594
 595 config SECCOMP
 596         bool "Enable seccomp to safely compute untrusted bytecode"
 597         ---help---
 598           This kernel feature is useful for number crunching applications
 599           that may need to compute untrusted bytecode during their
 600           execution. By using pipes or other transports made available to
 601           the process as file descriptors supporting the read/write
 602           syscalls, it's possible to isolate those applications in
 603           their own address space using seccomp. Once seccomp is
 604           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
 605           and the task is only allowed to execute a few safe syscalls
 606           defined by each seccomp mode.
 607
 608 config XEN_DOM0
 609         def_bool y
 610         depends on XEN
 611
 612 config XEN
 613         bool "Xen guest support on ARM64"
 614         depends on ARM64 && OF
 615         select SWIOTLB_XEN
 616         help
 617           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
 618
 619 config FORCE_MAX_ZONEORDER
 620         int
 621         default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
 622         default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
 623         default "11"
 624         help
 625           The kernel memory allocator divides physically contiguous memory
 626           blocks into "zones", where each zone is a power of two number of
 627           pages.  This option selects the largest power of two that the kernel
 628           keeps in the memory allocator.  If you need to allocate very large
 629           blocks of physically contiguous memory, then you may need to
 630           increase this value.
 631
 632           This config option is actually maximum order plus one. For example,
 633           a value of 11 means that the largest free memory block is 2^10 pages.
 634
 635           We make sure that we can allocate upto a HugePage size for each configuration.
 636           Hence we have :
 637                 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
 638
 639           However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
 640           4M allocations matching the default size used by generic code.
 641
 642 menuconfig ARMV8_DEPRECATED
 643         bool "Emulate deprecated/obsolete ARMv8 instructions"
 644         depends on COMPAT
 645         help
 646           Legacy software support may require certain instructions
 647           that have been deprecated or obsoleted in the architecture.
 648
 649           Enable this config to enable selective emulation of these
 650           features.
 651
 652           If unsure, say Y
 653
 654 if ARMV8_DEPRECATED
 655
 656 config SWP_EMULATION
 657         bool "Emulate SWP/SWPB instructions"
 658         help
 659           ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
 660           they are always undefined. Say Y here to enable software
 661           emulation of these instructions for userspace using LDXR/STXR.
 662
 663           In some older versions of glibc [<=2.8] SWP is used during futex
 664           trylock() operations with the assumption that the code will not
 665           be preempted. This invalid assumption may be more likely to fail
 666           with SWP emulation enabled, leading to deadlock of the user
 667           application.
 668
 669           NOTE: when accessing uncached shared regions, LDXR/STXR rely
 670           on an external transaction monitoring block called a global
 671           monitor to maintain update atomicity. If your system does not
 672           implement a global monitor, this option can cause programs that
 673           perform SWP operations to uncached memory to deadlock.
 674
 675           If unsure, say Y
 676
 677 config CP15_BARRIER_EMULATION
 678         bool "Emulate CP15 Barrier instructions"
 679         help
 680           The CP15 barrier instructions - CP15ISB, CP15DSB, and
 681           CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
 682           strongly recommended to use the ISB, DSB, and DMB
 683           instructions instead.
 684
 685           Say Y here to enable software emulation of these
 686           instructions for AArch32 userspace code. When this option is
 687           enabled, CP15 barrier usage is traced which can help
 688           identify software that needs updating.
 689
 690           If unsure, say Y
 691
 692 config SETEND_EMULATION
 693         bool "Emulate SETEND instruction"
 694         help
 695           The SETEND instruction alters the data-endianness of the
 696           AArch32 EL0, and is deprecated in ARMv8.
 697
 698           Say Y here to enable software emulation of the instruction
 699           for AArch32 userspace code.
 700
 701           Note: All the cpus on the system must have mixed endian support at EL0
 702           for this feature to be enabled. If a new CPU - which doesn't support mixed
 703           endian - is hotplugged in after this feature has been enabled, there could
 704           be unexpected results in the applications.
 705
 706           If unsure, say Y
 707 endif
 708
 709 config ARM64_SW_TTBR0_PAN
 710         bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
 711         help
 712           Enabling this option prevents the kernel from accessing
 713           user-space memory directly by pointing TTBR0_EL1 to a reserved
 714           zeroed area and reserved ASID. The user access routines
 715           restore the valid TTBR0_EL1 temporarily.
 716
 717 menu "ARMv8.1 architectural features"
 718
 719 config ARM64_HW_AFDBM
 720         bool "Support for hardware updates of the Access and Dirty page flags"
 721         default y
 722         help
 723           The ARMv8.1 architecture extensions introduce support for
 724           hardware updates of the access and dirty information in page
 725           table entries. When enabled in TCR_EL1 (HA and HD bits) on
 726           capable processors, accesses to pages with PTE_AF cleared will
 727           set this bit instead of raising an access flag fault.
 728           Similarly, writes to read-only pages with the DBM bit set will
 729           clear the read-only bit (AP[2]) instead of raising a
 730           permission fault.
 731
 732           Kernels built with this configuration option enabled continue
 733           to work on pre-ARMv8.1 hardware and the performance impact is
 734           minimal. If unsure, say Y.
 735
 736 config ARM64_PAN
 737         bool "Enable support for Privileged Access Never (PAN)"
 738         default y
 739         help
 740          Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
 741          prevents the kernel or hypervisor from accessing user-space (EL0)
 742          memory directly.
 743
 744          Choosing this option will cause any unprotected (not using
 745          copy_to_user et al) memory access to fail with a permission fault.
 746
 747          The feature is detected at runtime, and will remain as a 'nop'
 748          instruction if the cpu does not implement the feature.
 749
 750 config ARM64_LSE_ATOMICS
 751         bool "Atomic instructions"
 752         help
 753           As part of the Large System Extensions, ARMv8.1 introduces new
 754           atomic instructions that are designed specifically to scale in
 755           very large systems.
 756
 757           Say Y here to make use of these instructions for the in-kernel
 758           atomic routines. This incurs a small overhead on CPUs that do
 759           not support these instructions and requires the kernel to be
 760           built with binutils >= 2.25.
 761
 762 endmenu
 763
 764 config ARM64_UAO
 765         bool "Enable support for User Access Override (UAO)"
 766         default y
 767         help
 768           User Access Override (UAO; part of the ARMv8.2 Extensions)
 769           causes the 'unprivileged' variant of the load/store instructions to
 770           be overriden to be privileged.
 771
 772           This option changes get_user() and friends to use the 'unprivileged'
 773           variant of the load/store instructions. This ensures that user-space
 774           really did have access to the supplied memory. When addr_limit is
 775           set to kernel memory the UAO bit will be set, allowing privileged
 776           access to kernel memory.
 777
 778           Choosing this option will cause copy_to_user() et al to use user-space
 779           memory permissions.
 780
 781           The feature is detected at runtime, the kernel will use the
 782           regular load/store instructions if the cpu does not implement the
 783           feature.
 784
 785 config ARM64_MODULE_CMODEL_LARGE
 786         bool
 787
 788 config ARM64_MODULE_PLTS
 789         bool
 790         select ARM64_MODULE_CMODEL_LARGE
 791         select HAVE_MOD_ARCH_SPECIFIC
 792
 793 config RELOCATABLE
 794         bool
 795         help
 796           This builds the kernel as a Position Independent Executable (PIE),
 797           which retains all relocation metadata required to relocate the
 798           kernel binary at runtime to a different virtual address than the
 799           address it was linked at.
 800           Since AArch64 uses the RELA relocation format, this requires a
 801           relocation pass at runtime even if the kernel is loaded at the
 802           same address it was linked at.
 803
 804 config RANDOMIZE_BASE
 805         bool "Randomize the address of the kernel image"
 806         select ARM64_MODULE_PLTS if MODULES
 807         select RELOCATABLE
 808         help
 809           Randomizes the virtual address at which the kernel image is
 810           loaded, as a security feature that deters exploit attempts
 811           relying on knowledge of the location of kernel internals.
 812
 813           It is the bootloader's job to provide entropy, by passing a
 814           random u64 value in /chosen/kaslr-seed at kernel entry.
 815
 816           When booting via the UEFI stub, it will invoke the firmware's
 817           EFI_RNG_PROTOCOL implementation (if available) to supply entropy
 818           to the kernel proper. In addition, it will randomise the physical
 819           location of the kernel Image as well.
 820
 821           If unsure, say N.
 822
 823 config RANDOMIZE_MODULE_REGION_FULL
 824         bool "Randomize the module region independently from the core kernel"
 825         depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
 826         default y
 827         help
 828           Randomizes the location of the module region without considering the
 829           location of the core kernel. This way, it is impossible for modules
 830           to leak information about the location of core kernel data structures
 831           but it does imply that function calls between modules and the core
 832           kernel will need to be resolved via veneers in the module PLT.
 833
 834           When this option is not set, the module region will be randomized over
 835           a limited range that contains the [_stext, _etext] interval of the
 836           core kernel, so branch relocations are always in range.
 837
 838 endmenu
 839
 840 menu "Boot options"
 841
 842 config ARM64_ACPI_PARKING_PROTOCOL
 843         bool "Enable support for the ARM64 ACPI parking protocol"
 844         depends on ACPI
 845         help
 846           Enable support for the ARM64 ACPI parking protocol. If disabled
 847           the kernel will not allow booting through the ARM64 ACPI parking
 848           protocol even if the corresponding data is present in the ACPI
 849           MADT table.
 850
 851 config CMDLINE
 852         string "Default kernel command string"
 853         default ""
 854         help
 855           Provide a set of default command-line options at build time by
 856           entering them here. As a minimum, you should specify the the
 857           root device (e.g. root=/dev/nfs).
 858
 859 choice
 860         prompt "Kernel command line type" if CMDLINE != ""
 861         default CMDLINE_FROM_BOOTLOADER
 862
 863 config CMDLINE_FROM_BOOTLOADER
 864         bool "Use bootloader kernel arguments if available"
 865         help
 866           Uses the command-line options passed by the boot loader. If
 867           the boot loader doesn't provide any, the default kernel command
 868           string provided in CMDLINE will be used.
 869
 870 config CMDLINE_EXTEND
 871         bool "Extend bootloader kernel arguments"
 872         help
 873           The command-line arguments provided by the boot loader will be
 874           appended to the default kernel command string.
 875
 876 config CMDLINE_FORCE
 877         bool "Always use the default kernel command string"
 878         help
 879           Always use the default kernel command string, even if the boot
 880           loader passes other arguments to the kernel.
 881           This is useful if you cannot or don't want to change the
 882           command-line options your boot loader passes to the kernel.
 883 endchoice
 884
 885 config EFI_STUB
 886         bool
 887
 888 config EFI
 889         bool "UEFI runtime support"
 890         depends on OF && !CPU_BIG_ENDIAN
 891         select LIBFDT
 892         select UCS2_STRING
 893         select EFI_PARAMS_FROM_FDT
 894         select EFI_RUNTIME_WRAPPERS
 895         select EFI_STUB
 896         select EFI_ARMSTUB
 897         default y
 898         help
 899           This option provides support for runtime services provided
 900           by UEFI firmware (such as non-volatile variables, realtime
 901           clock, and platform reset). A UEFI stub is also provided to
 902           allow the kernel to be booted as an EFI application. This
 903           is only useful on systems that have UEFI firmware.
 904
 905 config DMI
 906         bool "Enable support for SMBIOS (DMI) tables"
 907         depends on EFI
 908         default y
 909         help
 910           This enables SMBIOS/DMI feature for systems.
 911
 912           This option is only useful on systems that have UEFI firmware.
 913           However, even with this option, the resultant kernel should
 914           continue to boot on existing non-UEFI platforms.
 915
 916 config BUILD_ARM64_APPENDED_DTB_IMAGE
 917         bool "Build a concatenated Image.gz/dtb by default"
 918         depends on OF
 919         help
 920           Enabling this option will cause a concatenated Image.gz and list of
 921           DTBs to be built by default (instead of a standalone Image.gz.)
 922           The image will built in arch/arm64/boot/Image.gz-dtb
 923
 924 config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
 925         string "Default dtb names"
 926         depends on BUILD_ARM64_APPENDED_DTB_IMAGE
 927         help
 928           Space separated list of names of dtbs to append when
 929           building a concatenated Image.gz-dtb.
 930
 931 endmenu
 932
 933 menu "Userspace binary formats"
 934
 935 source "fs/Kconfig.binfmt"
 936
 937 config COMPAT
 938         bool "Kernel support for 32-bit EL0"
 939         depends on ARM64_4K_PAGES || EXPERT
 940         select COMPAT_BINFMT_ELF
 941         select HAVE_UID16
 942         select OLD_SIGSUSPEND3
 943         select COMPAT_OLD_SIGACTION
 944         help
 945           This option enables support for a 32-bit EL0 running under a 64-bit
 946           kernel at EL1. AArch32-specific components such as system calls,
 947           the user helper functions, VFP support and the ptrace interface are
 948           handled appropriately by the kernel.
 949
 950           If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
 951           that you will only be able to execute AArch32 binaries that were compiled
 952           with page size aligned segments.
 953
 954           If you want to execute 32-bit userspace applications, say Y.
 955
 956 config SYSVIPC_COMPAT
 957         def_bool y
 958         depends on COMPAT && SYSVIPC
 959
 960 endmenu
 961
 962 menu "Power management options"
 963
 964 source "kernel/power/Kconfig"
 965
 966 config ARCH_SUSPEND_POSSIBLE
 967         def_bool y
 968
 969 endmenu
 970
 971 menu "CPU Power Management"
 972
 973 source "drivers/cpuidle/Kconfig"
 974
 975 source "drivers/cpufreq/Kconfig"
 976
 977 endmenu
 978
 979 source "net/Kconfig"
 980
 981 source "drivers/Kconfig"
 982
 983 source "drivers/firmware/Kconfig"
 984
 985 source "drivers/acpi/Kconfig"
 986
 987 source "fs/Kconfig"
 988
 989 source "arch/arm64/kvm/Kconfig"
 990
 991 source "arch/arm64/Kconfig.debug"
 992
 993 source "security/Kconfig"
 994
 995 source "crypto/Kconfig"
 996 if CRYPTO
 997 source "arch/arm64/crypto/Kconfig"
 998 endif
 999
1000 source "lib/Kconfig"