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ARM: S3C64XX: Add usb otg phy control
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / arch / arm / plat-samsung / devs.c
1 /* linux/arch/arm/plat-samsung/devs.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Base SAMSUNG platform device definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/serial_core.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/fb.h>
26 #include <linux/gfp.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/onenand.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/mmc/host.h>
31 #include <linux/ioport.h>
32 #include <linux/platform_data/s3c-hsudc.h>
33
34 #include <asm/irq.h>
35 #include <asm/pmu.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
39
40 #include <mach/hardware.h>
41 #include <mach/dma.h>
42 #include <mach/irqs.h>
43 #include <mach/map.h>
44
45 #include <plat/cpu.h>
46 #include <plat/devs.h>
47 #include <plat/adc.h>
48 #include <plat/ata.h>
49 #include <plat/ehci.h>
50 #include <plat/fb.h>
51 #include <plat/fb-s3c2410.h>
52 #include <plat/hwmon.h>
53 #include <plat/iic.h>
54 #include <plat/keypad.h>
55 #include <plat/mci.h>
56 #include <plat/nand.h>
57 #include <plat/sdhci.h>
58 #include <plat/ts.h>
59 #include <plat/udc.h>
60 #include <plat/udc-hs.h>
61 #include <plat/usb-control.h>
62 #include <plat/usb-phy.h>
63 #include <plat/regs-iic.h>
64 #include <plat/regs-serial.h>
65 #include <plat/regs-spi.h>
66 #include <plat/s3c64xx-spi.h>
67
68 static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
69
70 /* AC97 */
71 #ifdef CONFIG_CPU_S3C2440
72 static struct resource s3c_ac97_resource[] = {
73 [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
74 [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
75 [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
76 [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
77 [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
78 };
79
80 struct platform_device s3c_device_ac97 = {
81 .name = "samsung-ac97",
82 .id = -1,
83 .num_resources = ARRAY_SIZE(s3c_ac97_resource),
84 .resource = s3c_ac97_resource,
85 .dev = {
86 .dma_mask = &samsung_device_dma_mask,
87 .coherent_dma_mask = DMA_BIT_MASK(32),
88 }
89 };
90 #endif /* CONFIG_CPU_S3C2440 */
91
92 /* ADC */
93
94 #ifdef CONFIG_PLAT_S3C24XX
95 static struct resource s3c_adc_resource[] = {
96 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
97 [1] = DEFINE_RES_IRQ(IRQ_TC),
98 [2] = DEFINE_RES_IRQ(IRQ_ADC),
99 };
100
101 struct platform_device s3c_device_adc = {
102 .name = "s3c24xx-adc",
103 .id = -1,
104 .num_resources = ARRAY_SIZE(s3c_adc_resource),
105 .resource = s3c_adc_resource,
106 };
107 #endif /* CONFIG_PLAT_S3C24XX */
108
109 #if defined(CONFIG_SAMSUNG_DEV_ADC)
110 static struct resource s3c_adc_resource[] = {
111 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
112 [1] = DEFINE_RES_IRQ(IRQ_TC),
113 [2] = DEFINE_RES_IRQ(IRQ_ADC),
114 };
115
116 struct platform_device s3c_device_adc = {
117 .name = "samsung-adc",
118 .id = -1,
119 .num_resources = ARRAY_SIZE(s3c_adc_resource),
120 .resource = s3c_adc_resource,
121 };
122 #endif /* CONFIG_SAMSUNG_DEV_ADC */
123
124 /* Camif Controller */
125
126 #ifdef CONFIG_CPU_S3C2440
127 static struct resource s3c_camif_resource[] = {
128 [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
129 [1] = DEFINE_RES_IRQ(IRQ_CAM),
130 };
131
132 struct platform_device s3c_device_camif = {
133 .name = "s3c2440-camif",
134 .id = -1,
135 .num_resources = ARRAY_SIZE(s3c_camif_resource),
136 .resource = s3c_camif_resource,
137 .dev = {
138 .dma_mask = &samsung_device_dma_mask,
139 .coherent_dma_mask = DMA_BIT_MASK(32),
140 }
141 };
142 #endif /* CONFIG_CPU_S3C2440 */
143
144 /* ASOC DMA */
145
146 struct platform_device samsung_asoc_dma = {
147 .name = "samsung-audio",
148 .id = -1,
149 .dev = {
150 .dma_mask = &samsung_device_dma_mask,
151 .coherent_dma_mask = DMA_BIT_MASK(32),
152 }
153 };
154
155 struct platform_device samsung_asoc_idma = {
156 .name = "samsung-idma",
157 .id = -1,
158 .dev = {
159 .dma_mask = &samsung_device_dma_mask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
161 }
162 };
163
164 /* FB */
165
166 #ifdef CONFIG_S3C_DEV_FB
167 static struct resource s3c_fb_resource[] = {
168 [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
169 [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
170 [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
171 [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
172 };
173
174 struct platform_device s3c_device_fb = {
175 .name = "s3c-fb",
176 .id = -1,
177 .num_resources = ARRAY_SIZE(s3c_fb_resource),
178 .resource = s3c_fb_resource,
179 .dev = {
180 .dma_mask = &samsung_device_dma_mask,
181 .coherent_dma_mask = DMA_BIT_MASK(32),
182 },
183 };
184
185 void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
186 {
187 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
188 &s3c_device_fb);
189 }
190 #endif /* CONFIG_S3C_DEV_FB */
191
192 /* FIMC */
193
194 #ifdef CONFIG_S5P_DEV_FIMC0
195 static struct resource s5p_fimc0_resource[] = {
196 [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
197 [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
198 };
199
200 struct platform_device s5p_device_fimc0 = {
201 .name = "s5p-fimc",
202 .id = 0,
203 .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
204 .resource = s5p_fimc0_resource,
205 .dev = {
206 .dma_mask = &samsung_device_dma_mask,
207 .coherent_dma_mask = DMA_BIT_MASK(32),
208 },
209 };
210
211 struct platform_device s5p_device_fimc_md = {
212 .name = "s5p-fimc-md",
213 .id = -1,
214 };
215 #endif /* CONFIG_S5P_DEV_FIMC0 */
216
217 #ifdef CONFIG_S5P_DEV_FIMC1
218 static struct resource s5p_fimc1_resource[] = {
219 [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
220 [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
221 };
222
223 struct platform_device s5p_device_fimc1 = {
224 .name = "s5p-fimc",
225 .id = 1,
226 .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
227 .resource = s5p_fimc1_resource,
228 .dev = {
229 .dma_mask = &samsung_device_dma_mask,
230 .coherent_dma_mask = DMA_BIT_MASK(32),
231 },
232 };
233 #endif /* CONFIG_S5P_DEV_FIMC1 */
234
235 #ifdef CONFIG_S5P_DEV_FIMC2
236 static struct resource s5p_fimc2_resource[] = {
237 [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
238 [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
239 };
240
241 struct platform_device s5p_device_fimc2 = {
242 .name = "s5p-fimc",
243 .id = 2,
244 .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
245 .resource = s5p_fimc2_resource,
246 .dev = {
247 .dma_mask = &samsung_device_dma_mask,
248 .coherent_dma_mask = DMA_BIT_MASK(32),
249 },
250 };
251 #endif /* CONFIG_S5P_DEV_FIMC2 */
252
253 #ifdef CONFIG_S5P_DEV_FIMC3
254 static struct resource s5p_fimc3_resource[] = {
255 [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
256 [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
257 };
258
259 struct platform_device s5p_device_fimc3 = {
260 .name = "s5p-fimc",
261 .id = 3,
262 .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
263 .resource = s5p_fimc3_resource,
264 .dev = {
265 .dma_mask = &samsung_device_dma_mask,
266 .coherent_dma_mask = DMA_BIT_MASK(32),
267 },
268 };
269 #endif /* CONFIG_S5P_DEV_FIMC3 */
270
271 /* G2D */
272
273 #ifdef CONFIG_S5P_DEV_G2D
274 static struct resource s5p_g2d_resource[] = {
275 [0] = {
276 .start = S5P_PA_G2D,
277 .end = S5P_PA_G2D + SZ_4K - 1,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = IRQ_2D,
282 .end = IRQ_2D,
283 .flags = IORESOURCE_IRQ,
284 },
285 };
286
287 struct platform_device s5p_device_g2d = {
288 .name = "s5p-g2d",
289 .id = 0,
290 .num_resources = ARRAY_SIZE(s5p_g2d_resource),
291 .resource = s5p_g2d_resource,
292 .dev = {
293 .dma_mask = &samsung_device_dma_mask,
294 .coherent_dma_mask = DMA_BIT_MASK(32),
295 },
296 };
297 #endif /* CONFIG_S5P_DEV_G2D */
298
299 /* FIMD0 */
300
301 #ifdef CONFIG_S5P_DEV_FIMD0
302 static struct resource s5p_fimd0_resource[] = {
303 [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
304 [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
305 [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
306 [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
307 };
308
309 struct platform_device s5p_device_fimd0 = {
310 .name = "s5p-fb",
311 .id = 0,
312 .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
313 .resource = s5p_fimd0_resource,
314 .dev = {
315 .dma_mask = &samsung_device_dma_mask,
316 .coherent_dma_mask = DMA_BIT_MASK(32),
317 },
318 };
319
320 void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
321 {
322 s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
323 &s5p_device_fimd0);
324 }
325 #endif /* CONFIG_S5P_DEV_FIMD0 */
326
327 /* HWMON */
328
329 #ifdef CONFIG_S3C_DEV_HWMON
330 struct platform_device s3c_device_hwmon = {
331 .name = "s3c-hwmon",
332 .id = -1,
333 .dev.parent = &s3c_device_adc.dev,
334 };
335
336 void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
337 {
338 s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
339 &s3c_device_hwmon);
340 }
341 #endif /* CONFIG_S3C_DEV_HWMON */
342
343 /* HSMMC */
344
345 #ifdef CONFIG_S3C_DEV_HSMMC
346 static struct resource s3c_hsmmc_resource[] = {
347 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
348 [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
349 };
350
351 struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
352 .max_width = 4,
353 .host_caps = (MMC_CAP_4_BIT_DATA |
354 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
355 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
356 };
357
358 struct platform_device s3c_device_hsmmc0 = {
359 .name = "s3c-sdhci",
360 .id = 0,
361 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
362 .resource = s3c_hsmmc_resource,
363 .dev = {
364 .dma_mask = &samsung_device_dma_mask,
365 .coherent_dma_mask = DMA_BIT_MASK(32),
366 .platform_data = &s3c_hsmmc0_def_platdata,
367 },
368 };
369
370 void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
371 {
372 s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
373 }
374 #endif /* CONFIG_S3C_DEV_HSMMC */
375
376 #ifdef CONFIG_S3C_DEV_HSMMC1
377 static struct resource s3c_hsmmc1_resource[] = {
378 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
379 [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
380 };
381
382 struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
383 .max_width = 4,
384 .host_caps = (MMC_CAP_4_BIT_DATA |
385 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
386 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
387 };
388
389 struct platform_device s3c_device_hsmmc1 = {
390 .name = "s3c-sdhci",
391 .id = 1,
392 .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
393 .resource = s3c_hsmmc1_resource,
394 .dev = {
395 .dma_mask = &samsung_device_dma_mask,
396 .coherent_dma_mask = DMA_BIT_MASK(32),
397 .platform_data = &s3c_hsmmc1_def_platdata,
398 },
399 };
400
401 void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
402 {
403 s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
404 }
405 #endif /* CONFIG_S3C_DEV_HSMMC1 */
406
407 /* HSMMC2 */
408
409 #ifdef CONFIG_S3C_DEV_HSMMC2
410 static struct resource s3c_hsmmc2_resource[] = {
411 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
412 [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
413 };
414
415 struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
416 .max_width = 4,
417 .host_caps = (MMC_CAP_4_BIT_DATA |
418 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
419 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
420 };
421
422 struct platform_device s3c_device_hsmmc2 = {
423 .name = "s3c-sdhci",
424 .id = 2,
425 .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
426 .resource = s3c_hsmmc2_resource,
427 .dev = {
428 .dma_mask = &samsung_device_dma_mask,
429 .coherent_dma_mask = DMA_BIT_MASK(32),
430 .platform_data = &s3c_hsmmc2_def_platdata,
431 },
432 };
433
434 void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
435 {
436 s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
437 }
438 #endif /* CONFIG_S3C_DEV_HSMMC2 */
439
440 #ifdef CONFIG_S3C_DEV_HSMMC3
441 static struct resource s3c_hsmmc3_resource[] = {
442 [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
443 [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
444 };
445
446 struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
447 .max_width = 4,
448 .host_caps = (MMC_CAP_4_BIT_DATA |
449 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
450 .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL,
451 };
452
453 struct platform_device s3c_device_hsmmc3 = {
454 .name = "s3c-sdhci",
455 .id = 3,
456 .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
457 .resource = s3c_hsmmc3_resource,
458 .dev = {
459 .dma_mask = &samsung_device_dma_mask,
460 .coherent_dma_mask = DMA_BIT_MASK(32),
461 .platform_data = &s3c_hsmmc3_def_platdata,
462 },
463 };
464
465 void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
466 {
467 s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
468 }
469 #endif /* CONFIG_S3C_DEV_HSMMC3 */
470
471 /* I2C */
472
473 static struct resource s3c_i2c0_resource[] = {
474 [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
475 [1] = DEFINE_RES_IRQ(IRQ_IIC),
476 };
477
478 struct platform_device s3c_device_i2c0 = {
479 .name = "s3c2410-i2c",
480 #ifdef CONFIG_S3C_DEV_I2C1
481 .id = 0,
482 #else
483 .id = -1,
484 #endif
485 .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
486 .resource = s3c_i2c0_resource,
487 };
488
489 struct s3c2410_platform_i2c default_i2c_data __initdata = {
490 .flags = 0,
491 .slave_addr = 0x10,
492 .frequency = 100*1000,
493 .sda_delay = 100,
494 };
495
496 void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
497 {
498 struct s3c2410_platform_i2c *npd;
499
500 if (!pd)
501 pd = &default_i2c_data;
502
503 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
504 &s3c_device_i2c0);
505
506 if (!npd->cfg_gpio)
507 npd->cfg_gpio = s3c_i2c0_cfg_gpio;
508 }
509
510 #ifdef CONFIG_S3C_DEV_I2C1
511 static struct resource s3c_i2c1_resource[] = {
512 [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
513 [1] = DEFINE_RES_IRQ(IRQ_IIC1),
514 };
515
516 struct platform_device s3c_device_i2c1 = {
517 .name = "s3c2410-i2c",
518 .id = 1,
519 .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
520 .resource = s3c_i2c1_resource,
521 };
522
523 void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
524 {
525 struct s3c2410_platform_i2c *npd;
526
527 if (!pd) {
528 pd = &default_i2c_data;
529 pd->bus_num = 1;
530 }
531
532 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
533 &s3c_device_i2c1);
534
535 if (!npd->cfg_gpio)
536 npd->cfg_gpio = s3c_i2c1_cfg_gpio;
537 }
538 #endif /* CONFIG_S3C_DEV_I2C1 */
539
540 #ifdef CONFIG_S3C_DEV_I2C2
541 static struct resource s3c_i2c2_resource[] = {
542 [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
543 [1] = DEFINE_RES_IRQ(IRQ_IIC2),
544 };
545
546 struct platform_device s3c_device_i2c2 = {
547 .name = "s3c2410-i2c",
548 .id = 2,
549 .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
550 .resource = s3c_i2c2_resource,
551 };
552
553 void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
554 {
555 struct s3c2410_platform_i2c *npd;
556
557 if (!pd) {
558 pd = &default_i2c_data;
559 pd->bus_num = 2;
560 }
561
562 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
563 &s3c_device_i2c2);
564
565 if (!npd->cfg_gpio)
566 npd->cfg_gpio = s3c_i2c2_cfg_gpio;
567 }
568 #endif /* CONFIG_S3C_DEV_I2C2 */
569
570 #ifdef CONFIG_S3C_DEV_I2C3
571 static struct resource s3c_i2c3_resource[] = {
572 [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
573 [1] = DEFINE_RES_IRQ(IRQ_IIC3),
574 };
575
576 struct platform_device s3c_device_i2c3 = {
577 .name = "s3c2440-i2c",
578 .id = 3,
579 .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
580 .resource = s3c_i2c3_resource,
581 };
582
583 void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
584 {
585 struct s3c2410_platform_i2c *npd;
586
587 if (!pd) {
588 pd = &default_i2c_data;
589 pd->bus_num = 3;
590 }
591
592 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
593 &s3c_device_i2c3);
594
595 if (!npd->cfg_gpio)
596 npd->cfg_gpio = s3c_i2c3_cfg_gpio;
597 }
598 #endif /*CONFIG_S3C_DEV_I2C3 */
599
600 #ifdef CONFIG_S3C_DEV_I2C4
601 static struct resource s3c_i2c4_resource[] = {
602 [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
603 [1] = DEFINE_RES_IRQ(IRQ_IIC4),
604 };
605
606 struct platform_device s3c_device_i2c4 = {
607 .name = "s3c2440-i2c",
608 .id = 4,
609 .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
610 .resource = s3c_i2c4_resource,
611 };
612
613 void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
614 {
615 struct s3c2410_platform_i2c *npd;
616
617 if (!pd) {
618 pd = &default_i2c_data;
619 pd->bus_num = 4;
620 }
621
622 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
623 &s3c_device_i2c4);
624
625 if (!npd->cfg_gpio)
626 npd->cfg_gpio = s3c_i2c4_cfg_gpio;
627 }
628 #endif /*CONFIG_S3C_DEV_I2C4 */
629
630 #ifdef CONFIG_S3C_DEV_I2C5
631 static struct resource s3c_i2c5_resource[] = {
632 [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
633 [1] = DEFINE_RES_IRQ(IRQ_IIC5),
634 };
635
636 struct platform_device s3c_device_i2c5 = {
637 .name = "s3c2440-i2c",
638 .id = 5,
639 .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
640 .resource = s3c_i2c5_resource,
641 };
642
643 void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
644 {
645 struct s3c2410_platform_i2c *npd;
646
647 if (!pd) {
648 pd = &default_i2c_data;
649 pd->bus_num = 5;
650 }
651
652 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
653 &s3c_device_i2c5);
654
655 if (!npd->cfg_gpio)
656 npd->cfg_gpio = s3c_i2c5_cfg_gpio;
657 }
658 #endif /*CONFIG_S3C_DEV_I2C5 */
659
660 #ifdef CONFIG_S3C_DEV_I2C6
661 static struct resource s3c_i2c6_resource[] = {
662 [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
663 [1] = DEFINE_RES_IRQ(IRQ_IIC6),
664 };
665
666 struct platform_device s3c_device_i2c6 = {
667 .name = "s3c2440-i2c",
668 .id = 6,
669 .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
670 .resource = s3c_i2c6_resource,
671 };
672
673 void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
674 {
675 struct s3c2410_platform_i2c *npd;
676
677 if (!pd) {
678 pd = &default_i2c_data;
679 pd->bus_num = 6;
680 }
681
682 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
683 &s3c_device_i2c6);
684
685 if (!npd->cfg_gpio)
686 npd->cfg_gpio = s3c_i2c6_cfg_gpio;
687 }
688 #endif /* CONFIG_S3C_DEV_I2C6 */
689
690 #ifdef CONFIG_S3C_DEV_I2C7
691 static struct resource s3c_i2c7_resource[] = {
692 [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
693 [1] = DEFINE_RES_IRQ(IRQ_IIC7),
694 };
695
696 struct platform_device s3c_device_i2c7 = {
697 .name = "s3c2440-i2c",
698 .id = 7,
699 .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
700 .resource = s3c_i2c7_resource,
701 };
702
703 void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
704 {
705 struct s3c2410_platform_i2c *npd;
706
707 if (!pd) {
708 pd = &default_i2c_data;
709 pd->bus_num = 7;
710 }
711
712 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
713 &s3c_device_i2c7);
714
715 if (!npd->cfg_gpio)
716 npd->cfg_gpio = s3c_i2c7_cfg_gpio;
717 }
718 #endif /* CONFIG_S3C_DEV_I2C7 */
719
720 /* I2C HDMIPHY */
721
722 #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
723 static struct resource s5p_i2c_resource[] = {
724 [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
725 [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
726 };
727
728 struct platform_device s5p_device_i2c_hdmiphy = {
729 .name = "s3c2440-hdmiphy-i2c",
730 .id = -1,
731 .num_resources = ARRAY_SIZE(s5p_i2c_resource),
732 .resource = s5p_i2c_resource,
733 };
734
735 void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
736 {
737 struct s3c2410_platform_i2c *npd;
738
739 if (!pd) {
740 pd = &default_i2c_data;
741
742 if (soc_is_exynos4210())
743 pd->bus_num = 8;
744 else if (soc_is_s5pv210())
745 pd->bus_num = 3;
746 else
747 pd->bus_num = 0;
748 }
749
750 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
751 &s5p_device_i2c_hdmiphy);
752 }
753 #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
754
755 /* I2S */
756
757 #ifdef CONFIG_PLAT_S3C24XX
758 static struct resource s3c_iis_resource[] = {
759 [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
760 };
761
762 struct platform_device s3c_device_iis = {
763 .name = "s3c24xx-iis",
764 .id = -1,
765 .num_resources = ARRAY_SIZE(s3c_iis_resource),
766 .resource = s3c_iis_resource,
767 .dev = {
768 .dma_mask = &samsung_device_dma_mask,
769 .coherent_dma_mask = DMA_BIT_MASK(32),
770 }
771 };
772 #endif /* CONFIG_PLAT_S3C24XX */
773
774 #ifdef CONFIG_CPU_S3C2440
775 struct platform_device s3c2412_device_iis = {
776 .name = "s3c2412-iis",
777 .id = -1,
778 .dev = {
779 .dma_mask = &samsung_device_dma_mask,
780 .coherent_dma_mask = DMA_BIT_MASK(32),
781 }
782 };
783 #endif /* CONFIG_CPU_S3C2440 */
784
785 /* IDE CFCON */
786
787 #ifdef CONFIG_SAMSUNG_DEV_IDE
788 static struct resource s3c_cfcon_resource[] = {
789 [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
790 [1] = DEFINE_RES_IRQ(IRQ_CFCON),
791 };
792
793 struct platform_device s3c_device_cfcon = {
794 .id = 0,
795 .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
796 .resource = s3c_cfcon_resource,
797 };
798
799 void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
800 {
801 s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
802 &s3c_device_cfcon);
803 }
804 #endif /* CONFIG_SAMSUNG_DEV_IDE */
805
806 /* KEYPAD */
807
808 #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
809 static struct resource samsung_keypad_resources[] = {
810 [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
811 [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
812 };
813
814 struct platform_device samsung_device_keypad = {
815 .name = "samsung-keypad",
816 .id = -1,
817 .num_resources = ARRAY_SIZE(samsung_keypad_resources),
818 .resource = samsung_keypad_resources,
819 };
820
821 void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
822 {
823 struct samsung_keypad_platdata *npd;
824
825 npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
826 &samsung_device_keypad);
827
828 if (!npd->cfg_gpio)
829 npd->cfg_gpio = samsung_keypad_cfg_gpio;
830 }
831 #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
832
833 /* LCD Controller */
834
835 #ifdef CONFIG_PLAT_S3C24XX
836 static struct resource s3c_lcd_resource[] = {
837 [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
838 [1] = DEFINE_RES_IRQ(IRQ_LCD),
839 };
840
841 struct platform_device s3c_device_lcd = {
842 .name = "s3c2410-lcd",
843 .id = -1,
844 .num_resources = ARRAY_SIZE(s3c_lcd_resource),
845 .resource = s3c_lcd_resource,
846 .dev = {
847 .dma_mask = &samsung_device_dma_mask,
848 .coherent_dma_mask = DMA_BIT_MASK(32),
849 }
850 };
851
852 void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
853 {
854 struct s3c2410fb_mach_info *npd;
855
856 npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
857 if (npd) {
858 npd->displays = kmemdup(pd->displays,
859 sizeof(struct s3c2410fb_display) * npd->num_displays,
860 GFP_KERNEL);
861 if (!npd->displays)
862 printk(KERN_ERR "no memory for LCD display data\n");
863 } else {
864 printk(KERN_ERR "no memory for LCD platform data\n");
865 }
866 }
867 #endif /* CONFIG_PLAT_S3C24XX */
868
869 /* MFC */
870
871 #ifdef CONFIG_S5P_DEV_MFC
872 static struct resource s5p_mfc_resource[] = {
873 [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
874 [1] = DEFINE_RES_IRQ(IRQ_MFC),
875 };
876
877 struct platform_device s5p_device_mfc = {
878 .name = "s5p-mfc",
879 .id = -1,
880 .num_resources = ARRAY_SIZE(s5p_mfc_resource),
881 .resource = s5p_mfc_resource,
882 };
883
884 /*
885 * MFC hardware has 2 memory interfaces which are modelled as two separate
886 * platform devices to let dma-mapping distinguish between them.
887 *
888 * MFC parent device (s5p_device_mfc) must be registered before memory
889 * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
890 */
891
892 struct platform_device s5p_device_mfc_l = {
893 .name = "s5p-mfc-l",
894 .id = -1,
895 .dev = {
896 .parent = &s5p_device_mfc.dev,
897 .dma_mask = &samsung_device_dma_mask,
898 .coherent_dma_mask = DMA_BIT_MASK(32),
899 },
900 };
901
902 struct platform_device s5p_device_mfc_r = {
903 .name = "s5p-mfc-r",
904 .id = -1,
905 .dev = {
906 .parent = &s5p_device_mfc.dev,
907 .dma_mask = &samsung_device_dma_mask,
908 .coherent_dma_mask = DMA_BIT_MASK(32),
909 },
910 };
911 #endif /* CONFIG_S5P_DEV_MFC */
912
913 /* MIPI CSIS */
914
915 #ifdef CONFIG_S5P_DEV_CSIS0
916 static struct resource s5p_mipi_csis0_resource[] = {
917 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_4K),
918 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
919 };
920
921 struct platform_device s5p_device_mipi_csis0 = {
922 .name = "s5p-mipi-csis",
923 .id = 0,
924 .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
925 .resource = s5p_mipi_csis0_resource,
926 };
927 #endif /* CONFIG_S5P_DEV_CSIS0 */
928
929 #ifdef CONFIG_S5P_DEV_CSIS1
930 static struct resource s5p_mipi_csis1_resource[] = {
931 [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_4K),
932 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
933 };
934
935 struct platform_device s5p_device_mipi_csis1 = {
936 .name = "s5p-mipi-csis",
937 .id = 1,
938 .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
939 .resource = s5p_mipi_csis1_resource,
940 };
941 #endif
942
943 /* NAND */
944
945 #ifdef CONFIG_S3C_DEV_NAND
946 static struct resource s3c_nand_resource[] = {
947 [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
948 };
949
950 struct platform_device s3c_device_nand = {
951 .name = "s3c2410-nand",
952 .id = -1,
953 .num_resources = ARRAY_SIZE(s3c_nand_resource),
954 .resource = s3c_nand_resource,
955 };
956
957 /*
958 * s3c_nand_copy_set() - copy nand set data
959 * @set: The new structure, directly copied from the old.
960 *
961 * Copy all the fields from the NAND set field from what is probably __initdata
962 * to new kernel memory. The code returns 0 if the copy happened correctly or
963 * an error code for the calling function to display.
964 *
965 * Note, we currently do not try and look to see if we've already copied the
966 * data in a previous set.
967 */
968 static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
969 {
970 void *ptr;
971 int size;
972
973 size = sizeof(struct mtd_partition) * set->nr_partitions;
974 if (size) {
975 ptr = kmemdup(set->partitions, size, GFP_KERNEL);
976 set->partitions = ptr;
977
978 if (!ptr)
979 return -ENOMEM;
980 }
981
982 if (set->nr_map && set->nr_chips) {
983 size = sizeof(int) * set->nr_chips;
984 ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
985 set->nr_map = ptr;
986
987 if (!ptr)
988 return -ENOMEM;
989 }
990
991 if (set->ecc_layout) {
992 ptr = kmemdup(set->ecc_layout,
993 sizeof(struct nand_ecclayout), GFP_KERNEL);
994 set->ecc_layout = ptr;
995
996 if (!ptr)
997 return -ENOMEM;
998 }
999
1000 return 0;
1001 }
1002
1003 void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
1004 {
1005 struct s3c2410_platform_nand *npd;
1006 int size;
1007 int ret;
1008
1009 /* note, if we get a failure in allocation, we simply drop out of the
1010 * function. If there is so little memory available at initialisation
1011 * time then there is little chance the system is going to run.
1012 */
1013
1014 npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
1015 &s3c_device_nand);
1016 if (!npd)
1017 return;
1018
1019 /* now see if we need to copy any of the nand set data */
1020
1021 size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
1022 if (size) {
1023 struct s3c2410_nand_set *from = npd->sets;
1024 struct s3c2410_nand_set *to;
1025 int i;
1026
1027 to = kmemdup(from, size, GFP_KERNEL);
1028 npd->sets = to; /* set, even if we failed */
1029
1030 if (!to) {
1031 printk(KERN_ERR "%s: no memory for sets\n", __func__);
1032 return;
1033 }
1034
1035 for (i = 0; i < npd->nr_sets; i++) {
1036 ret = s3c_nand_copy_set(to);
1037 if (ret) {
1038 printk(KERN_ERR "%s: failed to copy set %d\n",
1039 __func__, i);
1040 return;
1041 }
1042 to++;
1043 }
1044 }
1045 }
1046 #endif /* CONFIG_S3C_DEV_NAND */
1047
1048 /* ONENAND */
1049
1050 #ifdef CONFIG_S3C_DEV_ONENAND
1051 static struct resource s3c_onenand_resources[] = {
1052 [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
1053 [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
1054 [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
1055 };
1056
1057 struct platform_device s3c_device_onenand = {
1058 .name = "samsung-onenand",
1059 .id = 0,
1060 .num_resources = ARRAY_SIZE(s3c_onenand_resources),
1061 .resource = s3c_onenand_resources,
1062 };
1063 #endif /* CONFIG_S3C_DEV_ONENAND */
1064
1065 #ifdef CONFIG_S3C64XX_DEV_ONENAND1
1066 static struct resource s3c64xx_onenand1_resources[] = {
1067 [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
1068 [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
1069 [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
1070 };
1071
1072 struct platform_device s3c64xx_device_onenand1 = {
1073 .name = "samsung-onenand",
1074 .id = 1,
1075 .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
1076 .resource = s3c64xx_onenand1_resources,
1077 };
1078
1079 void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
1080 {
1081 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
1082 &s3c64xx_device_onenand1);
1083 }
1084 #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
1085
1086 #ifdef CONFIG_S5P_DEV_ONENAND
1087 static struct resource s5p_onenand_resources[] = {
1088 [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
1089 [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
1090 [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
1091 };
1092
1093 struct platform_device s5p_device_onenand = {
1094 .name = "s5pc110-onenand",
1095 .id = -1,
1096 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
1097 .resource = s5p_onenand_resources,
1098 };
1099 #endif /* CONFIG_S5P_DEV_ONENAND */
1100
1101 /* PMU */
1102
1103 #ifdef CONFIG_PLAT_S5P
1104 static struct resource s5p_pmu_resource[] = {
1105 DEFINE_RES_IRQ(IRQ_PMU)
1106 };
1107
1108 struct platform_device s5p_device_pmu = {
1109 .name = "arm-pmu",
1110 .id = ARM_PMU_DEVICE_CPU,
1111 .num_resources = ARRAY_SIZE(s5p_pmu_resource),
1112 .resource = s5p_pmu_resource,
1113 };
1114
1115 static int __init s5p_pmu_init(void)
1116 {
1117 platform_device_register(&s5p_device_pmu);
1118 return 0;
1119 }
1120 arch_initcall(s5p_pmu_init);
1121 #endif /* CONFIG_PLAT_S5P */
1122
1123 /* PWM Timer */
1124
1125 #ifdef CONFIG_SAMSUNG_DEV_PWM
1126
1127 #define TIMER_RESOURCE_SIZE (1)
1128
1129 #define TIMER_RESOURCE(_tmr, _irq) \
1130 (struct resource [TIMER_RESOURCE_SIZE]) { \
1131 [0] = { \
1132 .start = _irq, \
1133 .end = _irq, \
1134 .flags = IORESOURCE_IRQ \
1135 } \
1136 }
1137
1138 #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
1139 .name = "s3c24xx-pwm", \
1140 .id = _tmr_no, \
1141 .num_resources = TIMER_RESOURCE_SIZE, \
1142 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
1143
1144 /*
1145 * since we already have an static mapping for the timer,
1146 * we do not bother setting any IO resource for the base.
1147 */
1148
1149 struct platform_device s3c_device_timer[] = {
1150 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
1151 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
1152 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
1153 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
1154 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
1155 };
1156 #endif /* CONFIG_SAMSUNG_DEV_PWM */
1157
1158 /* RTC */
1159
1160 #ifdef CONFIG_PLAT_S3C24XX
1161 static struct resource s3c_rtc_resource[] = {
1162 [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
1163 [1] = DEFINE_RES_IRQ(IRQ_RTC),
1164 [2] = DEFINE_RES_IRQ(IRQ_TICK),
1165 };
1166
1167 struct platform_device s3c_device_rtc = {
1168 .name = "s3c2410-rtc",
1169 .id = -1,
1170 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1171 .resource = s3c_rtc_resource,
1172 };
1173 #endif /* CONFIG_PLAT_S3C24XX */
1174
1175 #ifdef CONFIG_S3C_DEV_RTC
1176 static struct resource s3c_rtc_resource[] = {
1177 [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
1178 [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
1179 [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
1180 };
1181
1182 struct platform_device s3c_device_rtc = {
1183 .name = "s3c64xx-rtc",
1184 .id = -1,
1185 .num_resources = ARRAY_SIZE(s3c_rtc_resource),
1186 .resource = s3c_rtc_resource,
1187 };
1188 #endif /* CONFIG_S3C_DEV_RTC */
1189
1190 /* SDI */
1191
1192 #ifdef CONFIG_PLAT_S3C24XX
1193 static struct resource s3c_sdi_resource[] = {
1194 [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
1195 [1] = DEFINE_RES_IRQ(IRQ_SDI),
1196 };
1197
1198 struct platform_device s3c_device_sdi = {
1199 .name = "s3c2410-sdi",
1200 .id = -1,
1201 .num_resources = ARRAY_SIZE(s3c_sdi_resource),
1202 .resource = s3c_sdi_resource,
1203 };
1204
1205 void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
1206 {
1207 s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
1208 &s3c_device_sdi);
1209 }
1210 #endif /* CONFIG_PLAT_S3C24XX */
1211
1212 /* SPI */
1213
1214 #ifdef CONFIG_PLAT_S3C24XX
1215 static struct resource s3c_spi0_resource[] = {
1216 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
1217 [1] = DEFINE_RES_IRQ(IRQ_SPI0),
1218 };
1219
1220 struct platform_device s3c_device_spi0 = {
1221 .name = "s3c2410-spi",
1222 .id = 0,
1223 .num_resources = ARRAY_SIZE(s3c_spi0_resource),
1224 .resource = s3c_spi0_resource,
1225 .dev = {
1226 .dma_mask = &samsung_device_dma_mask,
1227 .coherent_dma_mask = DMA_BIT_MASK(32),
1228 }
1229 };
1230
1231 static struct resource s3c_spi1_resource[] = {
1232 [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
1233 [1] = DEFINE_RES_IRQ(IRQ_SPI1),
1234 };
1235
1236 struct platform_device s3c_device_spi1 = {
1237 .name = "s3c2410-spi",
1238 .id = 1,
1239 .num_resources = ARRAY_SIZE(s3c_spi1_resource),
1240 .resource = s3c_spi1_resource,
1241 .dev = {
1242 .dma_mask = &samsung_device_dma_mask,
1243 .coherent_dma_mask = DMA_BIT_MASK(32),
1244 }
1245 };
1246 #endif /* CONFIG_PLAT_S3C24XX */
1247
1248 /* Touchscreen */
1249
1250 #ifdef CONFIG_PLAT_S3C24XX
1251 static struct resource s3c_ts_resource[] = {
1252 [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
1253 [1] = DEFINE_RES_IRQ(IRQ_TC),
1254 };
1255
1256 struct platform_device s3c_device_ts = {
1257 .name = "s3c2410-ts",
1258 .id = -1,
1259 .dev.parent = &s3c_device_adc.dev,
1260 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1261 .resource = s3c_ts_resource,
1262 };
1263
1264 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
1265 {
1266 s3c_set_platdata(hard_s3c2410ts_info,
1267 sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
1268 }
1269 #endif /* CONFIG_PLAT_S3C24XX */
1270
1271 #ifdef CONFIG_SAMSUNG_DEV_TS
1272 static struct resource s3c_ts_resource[] = {
1273 [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
1274 [1] = DEFINE_RES_IRQ(IRQ_TC),
1275 };
1276
1277 static struct s3c2410_ts_mach_info default_ts_data __initdata = {
1278 .delay = 10000,
1279 .presc = 49,
1280 .oversampling_shift = 2,
1281 };
1282
1283 struct platform_device s3c_device_ts = {
1284 .name = "s3c64xx-ts",
1285 .id = -1,
1286 .num_resources = ARRAY_SIZE(s3c_ts_resource),
1287 .resource = s3c_ts_resource,
1288 };
1289
1290 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
1291 {
1292 if (!pd)
1293 pd = &default_ts_data;
1294
1295 s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
1296 &s3c_device_ts);
1297 }
1298 #endif /* CONFIG_SAMSUNG_DEV_TS */
1299
1300 /* TV */
1301
1302 #ifdef CONFIG_S5P_DEV_TV
1303
1304 static struct resource s5p_hdmi_resources[] = {
1305 [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
1306 [1] = DEFINE_RES_IRQ(IRQ_HDMI),
1307 };
1308
1309 struct platform_device s5p_device_hdmi = {
1310 .name = "s5p-hdmi",
1311 .id = -1,
1312 .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
1313 .resource = s5p_hdmi_resources,
1314 };
1315
1316 static struct resource s5p_sdo_resources[] = {
1317 [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
1318 [1] = DEFINE_RES_IRQ(IRQ_SDO),
1319 };
1320
1321 struct platform_device s5p_device_sdo = {
1322 .name = "s5p-sdo",
1323 .id = -1,
1324 .num_resources = ARRAY_SIZE(s5p_sdo_resources),
1325 .resource = s5p_sdo_resources,
1326 };
1327
1328 static struct resource s5p_mixer_resources[] = {
1329 [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
1330 [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
1331 [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
1332 };
1333
1334 struct platform_device s5p_device_mixer = {
1335 .name = "s5p-mixer",
1336 .id = -1,
1337 .num_resources = ARRAY_SIZE(s5p_mixer_resources),
1338 .resource = s5p_mixer_resources,
1339 .dev = {
1340 .dma_mask = &samsung_device_dma_mask,
1341 .coherent_dma_mask = DMA_BIT_MASK(32),
1342 }
1343 };
1344 #endif /* CONFIG_S5P_DEV_TV */
1345
1346 /* USB */
1347
1348 #ifdef CONFIG_S3C_DEV_USB_HOST
1349 static struct resource s3c_usb_resource[] = {
1350 [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
1351 [1] = DEFINE_RES_IRQ(IRQ_USBH),
1352 };
1353
1354 struct platform_device s3c_device_ohci = {
1355 .name = "s3c2410-ohci",
1356 .id = -1,
1357 .num_resources = ARRAY_SIZE(s3c_usb_resource),
1358 .resource = s3c_usb_resource,
1359 .dev = {
1360 .dma_mask = &samsung_device_dma_mask,
1361 .coherent_dma_mask = DMA_BIT_MASK(32),
1362 }
1363 };
1364
1365 /*
1366 * s3c_ohci_set_platdata - initialise OHCI device platform data
1367 * @info: The platform data.
1368 *
1369 * This call copies the @info passed in and sets the device .platform_data
1370 * field to that copy. The @info is copied so that the original can be marked
1371 * __initdata.
1372 */
1373
1374 void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
1375 {
1376 s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
1377 &s3c_device_ohci);
1378 }
1379 #endif /* CONFIG_S3C_DEV_USB_HOST */
1380
1381 /* USB Device (Gadget) */
1382
1383 #ifdef CONFIG_PLAT_S3C24XX
1384 static struct resource s3c_usbgadget_resource[] = {
1385 [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
1386 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1387 };
1388
1389 struct platform_device s3c_device_usbgadget = {
1390 .name = "s3c2410-usbgadget",
1391 .id = -1,
1392 .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
1393 .resource = s3c_usbgadget_resource,
1394 };
1395
1396 void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
1397 {
1398 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
1399 }
1400 #endif /* CONFIG_PLAT_S3C24XX */
1401
1402 /* USB EHCI Host Controller */
1403
1404 #ifdef CONFIG_S5P_DEV_USB_EHCI
1405 static struct resource s5p_ehci_resource[] = {
1406 [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
1407 [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
1408 };
1409
1410 struct platform_device s5p_device_ehci = {
1411 .name = "s5p-ehci",
1412 .id = -1,
1413 .num_resources = ARRAY_SIZE(s5p_ehci_resource),
1414 .resource = s5p_ehci_resource,
1415 .dev = {
1416 .dma_mask = &samsung_device_dma_mask,
1417 .coherent_dma_mask = DMA_BIT_MASK(32),
1418 }
1419 };
1420
1421 void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
1422 {
1423 struct s5p_ehci_platdata *npd;
1424
1425 npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
1426 &s5p_device_ehci);
1427
1428 if (!npd->phy_init)
1429 npd->phy_init = s5p_usb_phy_init;
1430 if (!npd->phy_exit)
1431 npd->phy_exit = s5p_usb_phy_exit;
1432 }
1433 #endif /* CONFIG_S5P_DEV_USB_EHCI */
1434
1435 /* USB HSOTG */
1436
1437 #ifdef CONFIG_S3C_DEV_USB_HSOTG
1438 static struct resource s3c_usb_hsotg_resources[] = {
1439 [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_16K),
1440 [1] = DEFINE_RES_IRQ(IRQ_OTG),
1441 };
1442
1443 struct platform_device s3c_device_usb_hsotg = {
1444 .name = "s3c-hsotg",
1445 .id = -1,
1446 .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
1447 .resource = s3c_usb_hsotg_resources,
1448 .dev = {
1449 .dma_mask = &samsung_device_dma_mask,
1450 .coherent_dma_mask = DMA_BIT_MASK(32),
1451 },
1452 };
1453
1454 void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
1455 {
1456 struct s3c_hsotg_plat *npd;
1457
1458 npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
1459 &s3c_device_usb_hsotg);
1460
1461 if (!npd->phy_init)
1462 npd->phy_init = s5p_usb_phy_init;
1463 if (!npd->phy_exit)
1464 npd->phy_exit = s5p_usb_phy_exit;
1465 }
1466 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
1467
1468 /* USB High Spped 2.0 Device (Gadget) */
1469
1470 #ifdef CONFIG_PLAT_S3C24XX
1471 static struct resource s3c_hsudc_resource[] = {
1472 [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
1473 [1] = DEFINE_RES_IRQ(IRQ_USBD),
1474 };
1475
1476 struct platform_device s3c_device_usb_hsudc = {
1477 .name = "s3c-hsudc",
1478 .id = -1,
1479 .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
1480 .resource = s3c_hsudc_resource,
1481 .dev = {
1482 .dma_mask = &samsung_device_dma_mask,
1483 .coherent_dma_mask = DMA_BIT_MASK(32),
1484 },
1485 };
1486
1487 void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
1488 {
1489 s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
1490 }
1491 #endif /* CONFIG_PLAT_S3C24XX */
1492
1493 /* WDT */
1494
1495 #ifdef CONFIG_S3C_DEV_WDT
1496 static struct resource s3c_wdt_resource[] = {
1497 [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
1498 [1] = DEFINE_RES_IRQ(IRQ_WDT),
1499 };
1500
1501 struct platform_device s3c_device_wdt = {
1502 .name = "s3c2410-wdt",
1503 .id = -1,
1504 .num_resources = ARRAY_SIZE(s3c_wdt_resource),
1505 .resource = s3c_wdt_resource,
1506 };
1507 #endif /* CONFIG_S3C_DEV_WDT */
1508
1509 #ifdef CONFIG_S3C64XX_DEV_SPI0
1510 static struct resource s3c64xx_spi0_resource[] = {
1511 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1512 [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
1513 [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
1514 [3] = DEFINE_RES_IRQ(IRQ_SPI0),
1515 };
1516
1517 struct platform_device s3c64xx_device_spi0 = {
1518 .name = "s3c64xx-spi",
1519 .id = 0,
1520 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1521 .resource = s3c64xx_spi0_resource,
1522 .dev = {
1523 .dma_mask = &samsung_device_dma_mask,
1524 .coherent_dma_mask = DMA_BIT_MASK(32),
1525 },
1526 };
1527
1528 void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1529 int src_clk_nr, int num_cs)
1530 {
1531 if (!pd) {
1532 pr_err("%s:Need to pass platform data\n", __func__);
1533 return;
1534 }
1535
1536 /* Reject invalid configuration */
1537 if (!num_cs || src_clk_nr < 0) {
1538 pr_err("%s: Invalid SPI configuration\n", __func__);
1539 return;
1540 }
1541
1542 pd->num_cs = num_cs;
1543 pd->src_clk_nr = src_clk_nr;
1544 if (!pd->cfg_gpio)
1545 pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
1546
1547 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
1548 }
1549 #endif /* CONFIG_S3C64XX_DEV_SPI0 */
1550
1551 #ifdef CONFIG_S3C64XX_DEV_SPI1
1552 static struct resource s3c64xx_spi1_resource[] = {
1553 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1554 [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
1555 [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
1556 [3] = DEFINE_RES_IRQ(IRQ_SPI1),
1557 };
1558
1559 struct platform_device s3c64xx_device_spi1 = {
1560 .name = "s3c64xx-spi",
1561 .id = 1,
1562 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1563 .resource = s3c64xx_spi1_resource,
1564 .dev = {
1565 .dma_mask = &samsung_device_dma_mask,
1566 .coherent_dma_mask = DMA_BIT_MASK(32),
1567 },
1568 };
1569
1570 void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
1571 int src_clk_nr, int num_cs)
1572 {
1573 if (!pd) {
1574 pr_err("%s:Need to pass platform data\n", __func__);
1575 return;
1576 }
1577
1578 /* Reject invalid configuration */
1579 if (!num_cs || src_clk_nr < 0) {
1580 pr_err("%s: Invalid SPI configuration\n", __func__);
1581 return;
1582 }
1583
1584 pd->num_cs = num_cs;
1585 pd->src_clk_nr = src_clk_nr;
1586 if (!pd->cfg_gpio)
1587 pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
1588
1589 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
1590 }
1591 #endif /* CONFIG_S3C64XX_DEV_SPI1 */
1592
1593 #ifdef CONFIG_S3C64XX_DEV_SPI2
1594 static struct resource s3c64xx_spi2_resource[] = {
1595 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
1596 [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
1597 [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
1598 [3] = DEFINE_RES_IRQ(IRQ_SPI2),
1599 };
1600
1601 struct platform_device s3c64xx_device_spi2 = {
1602 .name = "s3c64xx-spi",
1603 .id = 2,
1604 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1605 .resource = s3c64xx_spi2_resource,
1606 .dev = {
1607 .dma_mask = &samsung_device_dma_mask,
1608 .coherent_dma_mask = DMA_BIT_MASK(32),
1609 },
1610 };
1611
1612 void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1613 int src_clk_nr, int num_cs)
1614 {
1615 if (!pd) {
1616 pr_err("%s:Need to pass platform data\n", __func__);
1617 return;
1618 }
1619
1620 /* Reject invalid configuration */
1621 if (!num_cs || src_clk_nr < 0) {
1622 pr_err("%s: Invalid SPI configuration\n", __func__);
1623 return;
1624 }
1625
1626 pd->num_cs = num_cs;
1627 pd->src_clk_nr = src_clk_nr;
1628 if (!pd->cfg_gpio)
1629 pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
1630
1631 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
1632 }
1633 #endif /* CONFIG_S3C64XX_DEV_SPI2 */