1 /* linux/arch/arm/plat-s3c24xx/pm.c
3 * Copyright (c) 2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C24XX Power Manager (Suspend-To-RAM) support
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * Parts based on arch/arm/mach-pxa/pm.c
26 * Thanks to Dimitry Andric for debugging
29 #include <linux/init.h>
30 #include <linux/suspend.h>
31 #include <linux/errno.h>
32 #include <linux/time.h>
33 #include <linux/interrupt.h>
34 #include <linux/crc32.h>
35 #include <linux/ioport.h>
36 #include <linux/delay.h>
37 #include <linux/serial_core.h>
40 #include <asm/cacheflush.h>
41 #include <mach/hardware.h>
43 #include <plat/regs-serial.h>
44 #include <mach/regs-clock.h>
45 #include <mach/regs-gpio.h>
46 #include <mach/regs-mem.h>
47 #include <mach/regs-irq.h>
49 #include <asm/mach/time.h>
53 /* for external use */
55 unsigned long s3c_pm_flags
;
57 #define PFX "s3c24xx-pm: "
59 static struct sleep_save core_save
[] = {
60 SAVE_ITEM(S3C2410_LOCKTIME
),
61 SAVE_ITEM(S3C2410_CLKCON
),
63 /* we restore the timings here, with the proviso that the board
64 * brings the system up in an slower, or equal frequency setting
65 * to the original system.
67 * if we cannot guarantee this, then things are going to go very
68 * wrong here, as we modify the refresh and both pll settings.
71 SAVE_ITEM(S3C2410_BWSCON
),
72 SAVE_ITEM(S3C2410_BANKCON0
),
73 SAVE_ITEM(S3C2410_BANKCON1
),
74 SAVE_ITEM(S3C2410_BANKCON2
),
75 SAVE_ITEM(S3C2410_BANKCON3
),
76 SAVE_ITEM(S3C2410_BANKCON4
),
77 SAVE_ITEM(S3C2410_BANKCON5
),
79 #ifndef CONFIG_CPU_FREQ
80 SAVE_ITEM(S3C2410_CLKDIVN
),
81 SAVE_ITEM(S3C2410_MPLLCON
),
82 SAVE_ITEM(S3C2410_REFRESH
),
84 SAVE_ITEM(S3C2410_UPLLCON
),
85 SAVE_ITEM(S3C2410_CLKSLOW
),
88 static struct gpio_sleep
{
95 .base
= S3C2410_GPACON
,
98 .base
= S3C2410_GPBCON
,
101 .base
= S3C2410_GPCCON
,
104 .base
= S3C2410_GPDCON
,
107 .base
= S3C2410_GPECON
,
110 .base
= S3C2410_GPFCON
,
113 .base
= S3C2410_GPGCON
,
116 .base
= S3C2410_GPHCON
,
120 static struct sleep_save misc_save
[] = {
121 SAVE_ITEM(S3C2410_DCLKCON
),
124 #ifdef CONFIG_S3C2410_PM_DEBUG
126 #define SAVE_UART(va) \
127 SAVE_ITEM((va) + S3C2410_ULCON), \
128 SAVE_ITEM((va) + S3C2410_UCON), \
129 SAVE_ITEM((va) + S3C2410_UFCON), \
130 SAVE_ITEM((va) + S3C2410_UMCON), \
131 SAVE_ITEM((va) + S3C2410_UBRDIV)
133 static struct sleep_save uart_save
[] = {
134 SAVE_UART(S3C24XX_VA_UART0
),
135 SAVE_UART(S3C24XX_VA_UART1
),
136 #ifndef CONFIG_CPU_S3C2400
137 SAVE_UART(S3C24XX_VA_UART2
),
143 * we send the debug to printascii() to allow it to be seen if the
144 * system never wakes up from the sleep
147 extern void printascii(const char *);
149 void pm_dbg(const char *fmt
, ...)
155 vsprintf(buff
, fmt
, va
);
161 static void s3c2410_pm_debug_init(void)
163 unsigned long tmp
= __raw_readl(S3C2410_CLKCON
);
165 /* re-start uart clocks */
166 tmp
|= S3C2410_CLKCON_UART0
;
167 tmp
|= S3C2410_CLKCON_UART1
;
168 tmp
|= S3C2410_CLKCON_UART2
;
170 __raw_writel(tmp
, S3C2410_CLKCON
);
174 #define DBG(fmt...) pm_dbg(fmt)
176 #define DBG(fmt...) printk(KERN_DEBUG fmt)
178 #define s3c2410_pm_debug_init() do { } while(0)
180 static struct sleep_save uart_save
[] = {};
183 #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
185 /* suspend checking code...
187 * this next area does a set of crc checks over all the installed
188 * memory, so the system can verify if the resume was ok.
190 * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
191 * increasing it will mean that the area corrupted will be less easy to spot,
192 * and reducing the size will cause the CRC save area to grow
195 #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
197 static u32 crc_size
; /* size needed for the crc block */
198 static u32
*crcs
; /* allocated over suspend/resume */
200 typedef u32
*(run_fn_t
)(struct resource
*ptr
, u32
*arg
);
202 /* s3c2410_pm_run_res
204 * go thorugh the given resource list, and look for system ram
207 static void s3c2410_pm_run_res(struct resource
*ptr
, run_fn_t fn
, u32
*arg
)
209 while (ptr
!= NULL
) {
210 if (ptr
->child
!= NULL
)
211 s3c2410_pm_run_res(ptr
->child
, fn
, arg
);
213 if ((ptr
->flags
& IORESOURCE_MEM
) &&
214 strcmp(ptr
->name
, "System RAM") == 0) {
215 DBG("Found system RAM at %08lx..%08lx\n",
216 ptr
->start
, ptr
->end
);
217 arg
= (fn
)(ptr
, arg
);
224 static void s3c2410_pm_run_sysram(run_fn_t fn
, u32
*arg
)
226 s3c2410_pm_run_res(&iomem_resource
, fn
, arg
);
229 static u32
*s3c2410_pm_countram(struct resource
*res
, u32
*val
)
231 u32 size
= (u32
)(res
->end
- res
->start
)+1;
233 size
+= CHECK_CHUNKSIZE
-1;
234 size
/= CHECK_CHUNKSIZE
;
236 DBG("Area %08lx..%08lx, %d blocks\n", res
->start
, res
->end
, size
);
238 *val
+= size
* sizeof(u32
);
242 /* s3c2410_pm_prepare_check
244 * prepare the necessary information for creating the CRCs. This
245 * must be done before the final save, as it will require memory
246 * allocating, and thus touching bits of the kernel we do not
250 static void s3c2410_pm_check_prepare(void)
254 s3c2410_pm_run_sysram(s3c2410_pm_countram
, &crc_size
);
256 DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size
);
258 crcs
= kmalloc(crc_size
+4, GFP_KERNEL
);
260 printk(KERN_ERR
"Cannot allocated CRC save area\n");
263 static u32
*s3c2410_pm_makecheck(struct resource
*res
, u32
*val
)
265 unsigned long addr
, left
;
267 for (addr
= res
->start
; addr
< res
->end
;
268 addr
+= CHECK_CHUNKSIZE
) {
269 left
= res
->end
- addr
;
271 if (left
> CHECK_CHUNKSIZE
)
272 left
= CHECK_CHUNKSIZE
;
274 *val
= crc32_le(~0, phys_to_virt(addr
), left
);
281 /* s3c2410_pm_check_store
283 * compute the CRC values for the memory blocks before the final
287 static void s3c2410_pm_check_store(void)
290 s3c2410_pm_run_sysram(s3c2410_pm_makecheck
, crcs
);
295 * return TRUE if the area defined by ptr..ptr+size contatins the
299 static inline int in_region(void *ptr
, int size
, void *what
, size_t whatsz
)
301 if ((what
+whatsz
) < ptr
)
304 if (what
> (ptr
+size
))
310 static u32
*s3c2410_pm_runcheck(struct resource
*res
, u32
*val
)
312 void *save_at
= phys_to_virt(s3c2410_sleep_save_phys
);
318 for (addr
= res
->start
; addr
< res
->end
;
319 addr
+= CHECK_CHUNKSIZE
) {
320 left
= res
->end
- addr
;
322 if (left
> CHECK_CHUNKSIZE
)
323 left
= CHECK_CHUNKSIZE
;
325 ptr
= phys_to_virt(addr
);
327 if (in_region(ptr
, left
, crcs
, crc_size
)) {
328 DBG("skipping %08lx, has crc block in\n", addr
);
332 if (in_region(ptr
, left
, save_at
, 32*4 )) {
333 DBG("skipping %08lx, has save block in\n", addr
);
337 /* calculate and check the checksum */
339 calc
= crc32_le(~0, ptr
, left
);
341 printk(KERN_ERR PFX
"Restore CRC error at "
342 "%08lx (%08x vs %08x)\n", addr
, calc
, *val
);
344 DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
355 /* s3c2410_pm_check_restore
357 * check the CRCs after the restore event and free the memory used
361 static void s3c2410_pm_check_restore(void)
364 s3c2410_pm_run_sysram(s3c2410_pm_runcheck
, crcs
);
372 #define s3c2410_pm_check_prepare() do { } while(0)
373 #define s3c2410_pm_check_restore() do { } while(0)
374 #define s3c2410_pm_check_store() do { } while(0)
377 /* helper functions to save and restore register state */
379 void s3c2410_pm_do_save(struct sleep_save
*ptr
, int count
)
381 for (; count
> 0; count
--, ptr
++) {
382 ptr
->val
= __raw_readl(ptr
->reg
);
383 DBG("saved %p value %08lx\n", ptr
->reg
, ptr
->val
);
387 /* s3c2410_pm_do_restore
389 * restore the system from the given list of saved registers
391 * Note, we do not use DBG() in here, as the system may not have
392 * restore the UARTs state yet
395 void s3c2410_pm_do_restore(struct sleep_save
*ptr
, int count
)
397 for (; count
> 0; count
--, ptr
++) {
398 printk(KERN_DEBUG
"restore %p (restore %08lx, was %08x)\n",
399 ptr
->reg
, ptr
->val
, __raw_readl(ptr
->reg
));
401 __raw_writel(ptr
->val
, ptr
->reg
);
405 /* s3c2410_pm_do_restore_core
407 * similar to s3c2410_pm_do_restore_core
409 * WARNING: Do not put any debug in here that may effect memory or use
410 * peripherals, as things may be changing!
413 static void s3c2410_pm_do_restore_core(struct sleep_save
*ptr
, int count
)
415 for (; count
> 0; count
--, ptr
++) {
416 __raw_writel(ptr
->val
, ptr
->reg
);
420 /* s3c2410_pm_show_resume_irqs
422 * print any IRQs asserted at resume time (ie, we woke from)
425 static void s3c2410_pm_show_resume_irqs(int start
, unsigned long which
,
432 for (i
= 0; i
<= 31; i
++) {
433 if ((which
) & (1L<<i
)) {
434 DBG("IRQ %d asserted at resume\n", start
+i
);
439 /* s3c2410_pm_check_resume_pin
441 * check to see if the pin is configured correctly for sleep mode, and
442 * make any necessary adjustments if it is not
445 static void s3c2410_pm_check_resume_pin(unsigned int pin
, unsigned int irqoffs
)
447 unsigned long irqstate
;
448 unsigned long pinstate
;
449 int irq
= s3c2410_gpio_getirq(pin
);
452 irqstate
= s3c_irqwake_intmask
& (1L<<irqoffs
);
454 irqstate
= s3c_irqwake_eintmask
& (1L<<irqoffs
);
456 pinstate
= s3c2410_gpio_getcfg(pin
);
459 if (pinstate
== S3C2410_GPIO_IRQ
)
460 DBG("Leaving IRQ %d (pin %d) enabled\n", irq
, pin
);
462 if (pinstate
== S3C2410_GPIO_IRQ
) {
463 DBG("Disabling IRQ %d (pin %d)\n", irq
, pin
);
464 s3c2410_gpio_cfgpin(pin
, S3C2410_GPIO_INPUT
);
469 /* s3c2410_pm_configure_extint
471 * configure all external interrupt pins
474 static void s3c2410_pm_configure_extint(void)
478 /* for each of the external interrupts (EINT0..EINT15) we
479 * need to check wether it is an external interrupt source,
480 * and then configure it as an input if it is not
483 for (pin
= S3C2410_GPF0
; pin
<= S3C2410_GPF7
; pin
++) {
484 s3c2410_pm_check_resume_pin(pin
, pin
- S3C2410_GPF0
);
487 for (pin
= S3C2410_GPG0
; pin
<= S3C2410_GPG7
; pin
++) {
488 s3c2410_pm_check_resume_pin(pin
, (pin
- S3C2410_GPG0
)+8);
492 /* offsets for CON/DAT/UP registers */
494 #define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
495 #define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
496 #define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
498 /* s3c2410_pm_save_gpios()
500 * Save the state of the GPIOs
503 static void s3c2410_pm_save_gpios(void)
505 struct gpio_sleep
*gps
= gpio_save
;
508 for (gpio
= 0; gpio
< ARRAY_SIZE(gpio_save
); gpio
++, gps
++) {
509 void __iomem
*base
= gps
->base
;
511 gps
->gpcon
= __raw_readl(base
+ OFFS_CON
);
512 gps
->gpdat
= __raw_readl(base
+ OFFS_DAT
);
515 gps
->gpup
= __raw_readl(base
+ OFFS_UP
);
520 /* Test whether the given masked+shifted bits of an GPIO configuration
521 * are one of the SFN (special function) modes. */
523 static inline int is_sfn(unsigned long con
)
525 return (con
== 2 || con
== 3);
528 /* Test if the given masked+shifted GPIO configuration is an input */
530 static inline int is_in(unsigned long con
)
535 /* Test if the given masked+shifted GPIO configuration is an output */
537 static inline int is_out(unsigned long con
)
542 /* s3c2410_pm_restore_gpio()
544 * Restore one of the GPIO banks that was saved during suspend. This is
545 * not as simple as once thought, due to the possibility of glitches
546 * from the order that the CON and DAT registers are set in.
548 * The three states the pin can be are {IN,OUT,SFN} which gives us 9
549 * combinations of changes to check. Three of these, if the pin stays
550 * in the same configuration can be discounted. This leaves us with
553 * { IN => OUT } Change DAT first
554 * { IN => SFN } Change CON first
555 * { OUT => SFN } Change CON first, so new data will not glitch
556 * { OUT => IN } Change CON first, so new data will not glitch
557 * { SFN => IN } Change CON first
558 * { SFN => OUT } Change DAT first, so new data will not glitch [1]
560 * We do not currently deal with the UP registers as these control
561 * weak resistors, so a small delay in change should not need to bring
562 * these into the calculations.
564 * [1] this assumes that writing to a pin DAT whilst in SFN will set the
565 * state for when it is next output.
568 static void s3c2410_pm_restore_gpio(int index
, struct gpio_sleep
*gps
)
570 void __iomem
*base
= gps
->base
;
571 unsigned long gps_gpcon
= gps
->gpcon
;
572 unsigned long gps_gpdat
= gps
->gpdat
;
573 unsigned long old_gpcon
;
574 unsigned long old_gpdat
;
575 unsigned long old_gpup
= 0x0;
579 old_gpcon
= __raw_readl(base
+ OFFS_CON
);
580 old_gpdat
= __raw_readl(base
+ OFFS_DAT
);
582 if (base
== S3C2410_GPACON
) {
583 /* GPACON only has one bit per control / data and no PULLUPs.
584 * GPACON[x] = 0 => Output, 1 => SFN */
586 /* first set all SFN bits to SFN */
588 gpcon
= old_gpcon
| gps
->gpcon
;
589 __raw_writel(gpcon
, base
+ OFFS_CON
);
591 /* now set all the other bits */
593 __raw_writel(gps_gpdat
, base
+ OFFS_DAT
);
594 __raw_writel(gps_gpcon
, base
+ OFFS_CON
);
596 unsigned long old
, new, mask
;
597 unsigned long change_mask
= 0x0;
599 old_gpup
= __raw_readl(base
+ OFFS_UP
);
601 /* Create a change_mask of all the items that need to have
602 * their CON value changed before their DAT value, so that
603 * we minimise the work between the two settings.
606 for (nr
= 0, mask
= 0x03; nr
< 32; nr
+= 2, mask
<<= 2) {
607 old
= (old_gpcon
& mask
) >> nr
;
608 new = (gps_gpcon
& mask
) >> nr
;
610 /* If there is no change, then skip */
615 /* If both are special function, then skip */
617 if (is_sfn(old
) && is_sfn(new))
620 /* Change is IN => OUT, do not change now */
622 if (is_in(old
) && is_out(new))
625 /* Change is SFN => OUT, do not change now */
627 if (is_sfn(old
) && is_out(new))
630 /* We should now be at the case of IN=>SFN,
631 * OUT=>SFN, OUT=>IN, SFN=>IN. */
636 /* Write the new CON settings */
638 gpcon
= old_gpcon
& ~change_mask
;
639 gpcon
|= gps_gpcon
& change_mask
;
641 __raw_writel(gpcon
, base
+ OFFS_CON
);
643 /* Now change any items that require DAT,CON */
645 __raw_writel(gps_gpdat
, base
+ OFFS_DAT
);
646 __raw_writel(gps_gpcon
, base
+ OFFS_CON
);
647 __raw_writel(gps
->gpup
, base
+ OFFS_UP
);
650 DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
651 index
, old_gpcon
, gps_gpcon
, old_gpdat
, gps_gpdat
);
655 /** s3c2410_pm_restore_gpios()
657 * Restore the state of the GPIOs
660 static void s3c2410_pm_restore_gpios(void)
662 struct gpio_sleep
*gps
= gpio_save
;
665 for (gpio
= 0; gpio
< ARRAY_SIZE(gpio_save
); gpio
++, gps
++) {
666 s3c2410_pm_restore_gpio(gpio
, gps
);
670 void (*pm_cpu_prep
)(void);
671 void (*pm_cpu_sleep
)(void);
673 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
677 * central control for sleep/resume process
680 static int s3c2410_pm_enter(suspend_state_t state
)
682 unsigned long regs_save
[16];
684 /* ensure the debug is initialised (if enabled) */
686 s3c2410_pm_debug_init();
688 DBG("s3c2410_pm_enter(%d)\n", state
);
690 if (pm_cpu_prep
== NULL
|| pm_cpu_sleep
== NULL
) {
691 printk(KERN_ERR PFX
"error: no cpu sleep functions set\n");
695 /* check if we have anything to wake-up with... bad things seem
696 * to happen if you suspend with no wakeup (system will often
697 * require a full power-cycle)
700 if (!any_allowed(s3c_irqwake_intmask
, s3c_irqwake_intallow
) &&
701 !any_allowed(s3c_irqwake_eintmask
, s3c_irqwake_eintallow
)) {
702 printk(KERN_ERR PFX
"No sources enabled for wake-up!\n");
703 printk(KERN_ERR PFX
"Aborting sleep\n");
707 /* prepare check area if configured */
709 s3c2410_pm_check_prepare();
711 /* store the physical address of the register recovery block */
713 s3c2410_sleep_save_phys
= virt_to_phys(regs_save
);
715 DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys
);
717 /* save all necessary core registers not covered by the drivers */
719 s3c2410_pm_save_gpios();
720 s3c2410_pm_do_save(misc_save
, ARRAY_SIZE(misc_save
));
721 s3c2410_pm_do_save(core_save
, ARRAY_SIZE(core_save
));
722 s3c2410_pm_do_save(uart_save
, ARRAY_SIZE(uart_save
));
724 /* set the irq configuration for wake */
726 s3c2410_pm_configure_extint();
728 DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
729 s3c_irqwake_intmask
, s3c_irqwake_eintmask
);
731 __raw_writel(s3c_irqwake_intmask
, S3C2410_INTMSK
);
732 __raw_writel(s3c_irqwake_eintmask
, S3C2410_EINTMASK
);
734 /* ack any outstanding external interrupts before we go to sleep */
736 __raw_writel(__raw_readl(S3C2410_EINTPEND
), S3C2410_EINTPEND
);
737 __raw_writel(__raw_readl(S3C2410_INTPND
), S3C2410_INTPND
);
738 __raw_writel(__raw_readl(S3C2410_SRCPND
), S3C2410_SRCPND
);
740 /* call cpu specific preparation */
744 /* flush cache back to ram */
748 s3c2410_pm_check_store();
750 /* send the cpu to sleep... */
752 __raw_writel(0x00, S3C2410_CLKCON
); /* turn off clocks over sleep */
754 /* s3c2410_cpu_save will also act as our return point from when
755 * we resume as it saves its own register state, so use the return
756 * code to differentiate return from save and return from sleep */
758 if (s3c2410_cpu_save(regs_save
) == 0) {
763 /* restore the cpu state */
767 /* restore the system state */
769 s3c2410_pm_do_restore_core(core_save
, ARRAY_SIZE(core_save
));
770 s3c2410_pm_do_restore(misc_save
, ARRAY_SIZE(misc_save
));
771 s3c2410_pm_do_restore(uart_save
, ARRAY_SIZE(uart_save
));
772 s3c2410_pm_restore_gpios();
774 s3c2410_pm_debug_init();
776 /* check what irq (if any) restored the system */
778 DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
779 __raw_readl(S3C2410_SRCPND
),
780 __raw_readl(S3C2410_EINTPEND
));
782 s3c2410_pm_show_resume_irqs(IRQ_EINT0
, __raw_readl(S3C2410_SRCPND
),
783 s3c_irqwake_intmask
);
785 s3c2410_pm_show_resume_irqs(IRQ_EINT4
-4, __raw_readl(S3C2410_EINTPEND
),
786 s3c_irqwake_eintmask
);
788 DBG("post sleep, preparing to return\n");
790 s3c2410_pm_check_restore();
792 /* ok, let's return from sleep */
794 DBG("S3C2410 PM Resume (post-restore)\n");
798 static struct platform_suspend_ops s3c2410_pm_ops
= {
799 .enter
= s3c2410_pm_enter
,
800 .valid
= suspend_valid_only_mem
,
805 * Attach the power management functions. This should be called
806 * from the board specific initialisation if the board supports
810 int __init
s3c2410_pm_init(void)
812 printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
814 suspend_set_ops(&s3c2410_pm_ops
);