2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE 0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE 0xfffbe400
49 #define OMAP1610_GPIO2_BASE 0xfffbec00
50 #define OMAP1610_GPIO3_BASE 0xfffbb400
51 #define OMAP1610_GPIO4_BASE 0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP7XX specific GPIO registers
73 #define OMAP7XX_GPIO1_BASE 0xfffbc000
74 #define OMAP7XX_GPIO2_BASE 0xfffbc800
75 #define OMAP7XX_GPIO3_BASE 0xfffbd000
76 #define OMAP7XX_GPIO4_BASE 0xfffbd800
77 #define OMAP7XX_GPIO5_BASE 0xfffbe000
78 #define OMAP7XX_GPIO6_BASE 0xfffbe800
79 #define OMAP7XX_GPIO_DATA_INPUT 0x00
80 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
82 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
83 #define OMAP7XX_GPIO_INT_MASK 0x10
84 #define OMAP7XX_GPIO_INT_STATUS 0x14
86 #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
89 * omap24xx specific GPIO registers
91 #define OMAP242X_GPIO1_BASE 0x48018000
92 #define OMAP242X_GPIO2_BASE 0x4801a000
93 #define OMAP242X_GPIO3_BASE 0x4801c000
94 #define OMAP242X_GPIO4_BASE 0x4801e000
96 #define OMAP243X_GPIO1_BASE 0x4900C000
97 #define OMAP243X_GPIO2_BASE 0x4900E000
98 #define OMAP243X_GPIO3_BASE 0x49010000
99 #define OMAP243X_GPIO4_BASE 0x49012000
100 #define OMAP243X_GPIO5_BASE 0x480B6000
102 #define OMAP24XX_GPIO_REVISION 0x0000
103 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
104 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
105 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
106 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
108 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
109 #define OMAP24XX_GPIO_WAKE_EN 0x0020
110 #define OMAP24XX_GPIO_CTRL 0x0030
111 #define OMAP24XX_GPIO_OE 0x0034
112 #define OMAP24XX_GPIO_DATAIN 0x0038
113 #define OMAP24XX_GPIO_DATAOUT 0x003c
114 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
117 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
118 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
120 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123 #define OMAP24XX_GPIO_SETWKUENA 0x0084
124 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
127 #define OMAP4_GPIO_REVISION 0x0000
128 #define OMAP4_GPIO_SYSCONFIG 0x0010
129 #define OMAP4_GPIO_EOI 0x0020
130 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132 #define OMAP4_GPIO_IRQSTATUS0 0x002c
133 #define OMAP4_GPIO_IRQSTATUS1 0x0030
134 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138 #define OMAP4_GPIO_IRQWAKEN0 0x0044
139 #define OMAP4_GPIO_IRQWAKEN1 0x0048
140 #define OMAP4_GPIO_SYSSTATUS 0x0104
141 #define OMAP4_GPIO_CTRL 0x0130
142 #define OMAP4_GPIO_OE 0x0134
143 #define OMAP4_GPIO_DATAIN 0x0138
144 #define OMAP4_GPIO_DATAOUT 0x013c
145 #define OMAP4_GPIO_LEVELDETECT0 0x0140
146 #define OMAP4_GPIO_LEVELDETECT1 0x0144
147 #define OMAP4_GPIO_RISINGDETECT 0x0148
148 #define OMAP4_GPIO_FALLINGDETECT 0x014c
149 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
152 #define OMAP4_GPIO_SETDATAOUT 0x0194
154 * omap34xx specific GPIO registers
157 #define OMAP34XX_GPIO1_BASE 0x48310000
158 #define OMAP34XX_GPIO2_BASE 0x49050000
159 #define OMAP34XX_GPIO3_BASE 0x49052000
160 #define OMAP34XX_GPIO4_BASE 0x49054000
161 #define OMAP34XX_GPIO5_BASE 0x49056000
162 #define OMAP34XX_GPIO6_BASE 0x49058000
165 * OMAP44XX specific GPIO registers
167 #define OMAP44XX_GPIO1_BASE 0x4a310000
168 #define OMAP44XX_GPIO2_BASE 0x48055000
169 #define OMAP44XX_GPIO3_BASE 0x48057000
170 #define OMAP44XX_GPIO4_BASE 0x48059000
171 #define OMAP44XX_GPIO5_BASE 0x4805B000
172 #define OMAP44XX_GPIO6_BASE 0x4805D000
178 u16 virtual_irq_start
;
180 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
181 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
185 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
186 defined(CONFIG_ARCH_OMAP4)
187 u32 non_wakeup_gpios
;
188 u32 enabled_non_wakeup_gpios
;
191 u32 saved_fallingdetect
;
192 u32 saved_risingdetect
;
196 struct gpio_chip chip
;
200 #define METHOD_MPUIO 0
201 #define METHOD_GPIO_1510 1
202 #define METHOD_GPIO_1610 2
203 #define METHOD_GPIO_7XX 3
204 #define METHOD_GPIO_24XX 5
206 #ifdef CONFIG_ARCH_OMAP16XX
207 static struct gpio_bank gpio_bank_1610
[5] = {
208 { OMAP1_MPUIO_VBASE
, NULL
, INT_MPUIO
, IH_MPUIO_BASE
,
210 { OMAP1610_GPIO1_BASE
, NULL
, INT_GPIO_BANK1
, IH_GPIO_BASE
,
212 { OMAP1610_GPIO2_BASE
, NULL
, INT_1610_GPIO_BANK2
, IH_GPIO_BASE
+ 16,
214 { OMAP1610_GPIO3_BASE
, NULL
, INT_1610_GPIO_BANK3
, IH_GPIO_BASE
+ 32,
216 { OMAP1610_GPIO4_BASE
, NULL
, INT_1610_GPIO_BANK4
, IH_GPIO_BASE
+ 48,
221 #ifdef CONFIG_ARCH_OMAP15XX
222 static struct gpio_bank gpio_bank_1510
[2] = {
223 { OMAP1_MPUIO_VBASE
, NULL
, INT_MPUIO
, IH_MPUIO_BASE
,
225 { OMAP1510_GPIO_BASE
, NULL
, INT_GPIO_BANK1
, IH_GPIO_BASE
,
230 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
231 static struct gpio_bank gpio_bank_7xx
[7] = {
232 { OMAP1_MPUIO_VBASE
, NULL
, INT_7XX_MPUIO
, IH_MPUIO_BASE
,
234 { OMAP7XX_GPIO1_BASE
, NULL
, INT_7XX_GPIO_BANK1
, IH_GPIO_BASE
,
236 { OMAP7XX_GPIO2_BASE
, NULL
, INT_7XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
238 { OMAP7XX_GPIO3_BASE
, NULL
, INT_7XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
240 { OMAP7XX_GPIO4_BASE
, NULL
, INT_7XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
242 { OMAP7XX_GPIO5_BASE
, NULL
, INT_7XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
244 { OMAP7XX_GPIO6_BASE
, NULL
, INT_7XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160,
249 #ifdef CONFIG_ARCH_OMAP24XX
251 static struct gpio_bank gpio_bank_242x
[4] = {
252 { OMAP242X_GPIO1_BASE
, NULL
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
,
254 { OMAP242X_GPIO2_BASE
, NULL
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
256 { OMAP242X_GPIO3_BASE
, NULL
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
258 { OMAP242X_GPIO4_BASE
, NULL
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
262 static struct gpio_bank gpio_bank_243x
[5] = {
263 { OMAP243X_GPIO1_BASE
, NULL
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
,
265 { OMAP243X_GPIO2_BASE
, NULL
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
267 { OMAP243X_GPIO3_BASE
, NULL
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
269 { OMAP243X_GPIO4_BASE
, NULL
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
271 { OMAP243X_GPIO5_BASE
, NULL
, INT_24XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
277 #ifdef CONFIG_ARCH_OMAP34XX
278 static struct gpio_bank gpio_bank_34xx
[6] = {
279 { OMAP34XX_GPIO1_BASE
, NULL
, INT_34XX_GPIO_BANK1
, IH_GPIO_BASE
,
281 { OMAP34XX_GPIO2_BASE
, NULL
, INT_34XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
283 { OMAP34XX_GPIO3_BASE
, NULL
, INT_34XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
285 { OMAP34XX_GPIO4_BASE
, NULL
, INT_34XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
287 { OMAP34XX_GPIO5_BASE
, NULL
, INT_34XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
289 { OMAP34XX_GPIO6_BASE
, NULL
, INT_34XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160,
293 struct omap3_gpio_regs
{
309 static struct omap3_gpio_regs gpio_context
[OMAP34XX_NR_GPIOS
];
312 #ifdef CONFIG_ARCH_OMAP4
313 static struct gpio_bank gpio_bank_44xx
[6] = {
314 { OMAP44XX_GPIO1_BASE
, NULL
, INT_44XX_GPIO_BANK1
, IH_GPIO_BASE
,
316 { OMAP44XX_GPIO2_BASE
, NULL
, INT_44XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32,
318 { OMAP44XX_GPIO3_BASE
, NULL
, INT_44XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64,
320 { OMAP44XX_GPIO4_BASE
, NULL
, INT_44XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96,
322 { OMAP44XX_GPIO5_BASE
, NULL
, INT_44XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128,
324 { OMAP44XX_GPIO6_BASE
, NULL
, INT_44XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160,
330 static struct gpio_bank
*gpio_bank
;
331 static int gpio_bank_count
;
333 static inline struct gpio_bank
*get_gpio_bank(int gpio
)
335 if (cpu_is_omap15xx()) {
336 if (OMAP_GPIO_IS_MPUIO(gpio
))
337 return &gpio_bank
[0];
338 return &gpio_bank
[1];
340 if (cpu_is_omap16xx()) {
341 if (OMAP_GPIO_IS_MPUIO(gpio
))
342 return &gpio_bank
[0];
343 return &gpio_bank
[1 + (gpio
>> 4)];
345 if (cpu_is_omap7xx()) {
346 if (OMAP_GPIO_IS_MPUIO(gpio
))
347 return &gpio_bank
[0];
348 return &gpio_bank
[1 + (gpio
>> 5)];
350 if (cpu_is_omap24xx())
351 return &gpio_bank
[gpio
>> 5];
352 if (cpu_is_omap34xx() || cpu_is_omap44xx())
353 return &gpio_bank
[gpio
>> 5];
358 static inline int get_gpio_index(int gpio
)
360 if (cpu_is_omap7xx())
362 if (cpu_is_omap24xx())
364 if (cpu_is_omap34xx() || cpu_is_omap44xx())
369 static inline int gpio_valid(int gpio
)
373 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio
)) {
374 if (gpio
>= OMAP_MAX_GPIO_LINES
+ 16)
378 if (cpu_is_omap15xx() && gpio
< 16)
380 if ((cpu_is_omap16xx()) && gpio
< 64)
382 if (cpu_is_omap7xx() && gpio
< 192)
384 if (cpu_is_omap24xx() && gpio
< 128)
386 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio
< 192)
391 static int check_gpio(int gpio
)
393 if (unlikely(gpio_valid(gpio
) < 0)) {
394 printk(KERN_ERR
"omap-gpio: invalid GPIO %d\n", gpio
);
401 static void _set_gpio_direction(struct gpio_bank
*bank
, int gpio
, int is_input
)
403 void __iomem
*reg
= bank
->base
;
406 switch (bank
->method
) {
407 #ifdef CONFIG_ARCH_OMAP1
409 reg
+= OMAP_MPUIO_IO_CNTL
;
412 #ifdef CONFIG_ARCH_OMAP15XX
413 case METHOD_GPIO_1510
:
414 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
417 #ifdef CONFIG_ARCH_OMAP16XX
418 case METHOD_GPIO_1610
:
419 reg
+= OMAP1610_GPIO_DIRECTION
;
422 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
423 case METHOD_GPIO_7XX
:
424 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
427 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
428 case METHOD_GPIO_24XX
:
429 reg
+= OMAP24XX_GPIO_OE
;
432 #if defined(CONFIG_ARCH_OMAP4)
433 case METHOD_GPIO_24XX
:
434 reg
+= OMAP4_GPIO_OE
;
441 l
= __raw_readl(reg
);
446 __raw_writel(l
, reg
);
449 static void _set_gpio_dataout(struct gpio_bank
*bank
, int gpio
, int enable
)
451 void __iomem
*reg
= bank
->base
;
454 switch (bank
->method
) {
455 #ifdef CONFIG_ARCH_OMAP1
457 reg
+= OMAP_MPUIO_OUTPUT
;
458 l
= __raw_readl(reg
);
465 #ifdef CONFIG_ARCH_OMAP15XX
466 case METHOD_GPIO_1510
:
467 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
468 l
= __raw_readl(reg
);
475 #ifdef CONFIG_ARCH_OMAP16XX
476 case METHOD_GPIO_1610
:
478 reg
+= OMAP1610_GPIO_SET_DATAOUT
;
480 reg
+= OMAP1610_GPIO_CLEAR_DATAOUT
;
484 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
485 case METHOD_GPIO_7XX
:
486 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
487 l
= __raw_readl(reg
);
494 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
495 case METHOD_GPIO_24XX
:
497 reg
+= OMAP24XX_GPIO_SETDATAOUT
;
499 reg
+= OMAP24XX_GPIO_CLEARDATAOUT
;
503 #ifdef CONFIG_ARCH_OMAP4
504 case METHOD_GPIO_24XX
:
506 reg
+= OMAP4_GPIO_SETDATAOUT
;
508 reg
+= OMAP4_GPIO_CLEARDATAOUT
;
516 __raw_writel(l
, reg
);
519 static int _get_gpio_datain(struct gpio_bank
*bank
, int gpio
)
523 if (check_gpio(gpio
) < 0)
526 switch (bank
->method
) {
527 #ifdef CONFIG_ARCH_OMAP1
529 reg
+= OMAP_MPUIO_INPUT_LATCH
;
532 #ifdef CONFIG_ARCH_OMAP15XX
533 case METHOD_GPIO_1510
:
534 reg
+= OMAP1510_GPIO_DATA_INPUT
;
537 #ifdef CONFIG_ARCH_OMAP16XX
538 case METHOD_GPIO_1610
:
539 reg
+= OMAP1610_GPIO_DATAIN
;
542 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
543 case METHOD_GPIO_7XX
:
544 reg
+= OMAP7XX_GPIO_DATA_INPUT
;
547 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
548 case METHOD_GPIO_24XX
:
549 reg
+= OMAP24XX_GPIO_DATAIN
;
552 #ifdef CONFIG_ARCH_OMAP4
553 case METHOD_GPIO_24XX
:
554 reg
+= OMAP4_GPIO_DATAIN
;
560 return (__raw_readl(reg
)
561 & (1 << get_gpio_index(gpio
))) != 0;
564 static int _get_gpio_dataout(struct gpio_bank
*bank
, int gpio
)
568 if (check_gpio(gpio
) < 0)
572 switch (bank
->method
) {
573 #ifdef CONFIG_ARCH_OMAP1
575 reg
+= OMAP_MPUIO_OUTPUT
;
578 #ifdef CONFIG_ARCH_OMAP15XX
579 case METHOD_GPIO_1510
:
580 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
583 #ifdef CONFIG_ARCH_OMAP16XX
584 case METHOD_GPIO_1610
:
585 reg
+= OMAP1610_GPIO_DATAOUT
;
588 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
589 case METHOD_GPIO_7XX
:
590 reg
+= OMAP7XX_GPIO_DATA_OUTPUT
;
593 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
594 defined(CONFIG_ARCH_OMAP4)
595 case METHOD_GPIO_24XX
:
596 reg
+= OMAP24XX_GPIO_DATAOUT
;
603 return (__raw_readl(reg
) & (1 << get_gpio_index(gpio
))) != 0;
606 #define MOD_REG_BIT(reg, bit_mask, set) \
608 int l = __raw_readl(base + reg); \
609 if (set) l |= bit_mask; \
610 else l &= ~bit_mask; \
611 __raw_writel(l, base + reg); \
614 void omap_set_gpio_debounce(int gpio
, int enable
)
616 struct gpio_bank
*bank
;
619 u32 val
, l
= 1 << get_gpio_index(gpio
);
621 if (cpu_class_is_omap1())
624 bank
= get_gpio_bank(gpio
);
626 #ifdef CONFIG_ARCH_OMAP4
627 reg
+= OMAP4_GPIO_DEBOUNCENABLE
;
629 reg
+= OMAP24XX_GPIO_DEBOUNCE_EN
;
632 spin_lock_irqsave(&bank
->lock
, flags
);
633 val
= __raw_readl(reg
);
635 if (enable
&& !(val
& l
))
637 else if (!enable
&& (val
& l
))
642 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
644 clk_enable(bank
->dbck
);
646 clk_disable(bank
->dbck
);
649 __raw_writel(val
, reg
);
651 spin_unlock_irqrestore(&bank
->lock
, flags
);
653 EXPORT_SYMBOL(omap_set_gpio_debounce
);
655 void omap_set_gpio_debounce_time(int gpio
, int enc_time
)
657 struct gpio_bank
*bank
;
660 if (cpu_class_is_omap1())
663 bank
= get_gpio_bank(gpio
);
667 #ifdef CONFIG_ARCH_OMAP4
668 reg
+= OMAP4_GPIO_DEBOUNCINGTIME
;
670 reg
+= OMAP24XX_GPIO_DEBOUNCE_VAL
;
672 __raw_writel(enc_time
, reg
);
674 EXPORT_SYMBOL(omap_set_gpio_debounce_time
);
676 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
677 defined(CONFIG_ARCH_OMAP4)
678 static inline void set_24xx_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
681 void __iomem
*base
= bank
->base
;
682 u32 gpio_bit
= 1 << gpio
;
685 if (cpu_is_omap44xx()) {
686 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0
, gpio_bit
,
687 trigger
& IRQ_TYPE_LEVEL_LOW
);
688 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1
, gpio_bit
,
689 trigger
& IRQ_TYPE_LEVEL_HIGH
);
690 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT
, gpio_bit
,
691 trigger
& IRQ_TYPE_EDGE_RISING
);
692 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT
, gpio_bit
,
693 trigger
& IRQ_TYPE_EDGE_FALLING
);
695 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0
, gpio_bit
,
696 trigger
& IRQ_TYPE_LEVEL_LOW
);
697 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1
, gpio_bit
,
698 trigger
& IRQ_TYPE_LEVEL_HIGH
);
699 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT
, gpio_bit
,
700 trigger
& IRQ_TYPE_EDGE_RISING
);
701 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT
, gpio_bit
,
702 trigger
& IRQ_TYPE_EDGE_FALLING
);
704 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
705 if (cpu_is_omap44xx()) {
707 __raw_writel(1 << gpio
, bank
->base
+
708 OMAP4_GPIO_IRQWAKEN0
);
710 val
= __raw_readl(bank
->base
+
711 OMAP4_GPIO_IRQWAKEN0
);
712 __raw_writel(val
& (~(1 << gpio
)), bank
->base
+
713 OMAP4_GPIO_IRQWAKEN0
);
717 __raw_writel(1 << gpio
, bank
->base
718 + OMAP24XX_GPIO_SETWKUENA
);
720 __raw_writel(1 << gpio
, bank
->base
721 + OMAP24XX_GPIO_CLEARWKUENA
);
725 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
727 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
730 if (cpu_is_omap44xx()) {
732 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT0
) |
733 __raw_readl(bank
->base
+ OMAP4_GPIO_LEVELDETECT1
);
736 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
) |
737 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
742 static int _set_gpio_triggering(struct gpio_bank
*bank
, int gpio
, int trigger
)
744 void __iomem
*reg
= bank
->base
;
747 switch (bank
->method
) {
748 #ifdef CONFIG_ARCH_OMAP1
750 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
;
751 l
= __raw_readl(reg
);
752 if (trigger
& IRQ_TYPE_EDGE_RISING
)
754 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
760 #ifdef CONFIG_ARCH_OMAP15XX
761 case METHOD_GPIO_1510
:
762 reg
+= OMAP1510_GPIO_INT_CONTROL
;
763 l
= __raw_readl(reg
);
764 if (trigger
& IRQ_TYPE_EDGE_RISING
)
766 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
772 #ifdef CONFIG_ARCH_OMAP16XX
773 case METHOD_GPIO_1610
:
775 reg
+= OMAP1610_GPIO_EDGE_CTRL2
;
777 reg
+= OMAP1610_GPIO_EDGE_CTRL1
;
779 l
= __raw_readl(reg
);
780 l
&= ~(3 << (gpio
<< 1));
781 if (trigger
& IRQ_TYPE_EDGE_RISING
)
782 l
|= 2 << (gpio
<< 1);
783 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
784 l
|= 1 << (gpio
<< 1);
786 /* Enable wake-up during idle for dynamic tick */
787 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
);
789 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
);
792 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
793 case METHOD_GPIO_7XX
:
794 reg
+= OMAP7XX_GPIO_INT_CONTROL
;
795 l
= __raw_readl(reg
);
796 if (trigger
& IRQ_TYPE_EDGE_RISING
)
798 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
804 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
805 defined(CONFIG_ARCH_OMAP4)
806 case METHOD_GPIO_24XX
:
807 set_24xx_gpio_triggering(bank
, gpio
, trigger
);
813 __raw_writel(l
, reg
);
819 static int gpio_irq_type(unsigned irq
, unsigned type
)
821 struct gpio_bank
*bank
;
826 if (!cpu_class_is_omap2() && irq
> IH_MPUIO_BASE
)
827 gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
829 gpio
= irq
- IH_GPIO_BASE
;
831 if (check_gpio(gpio
) < 0)
834 if (type
& ~IRQ_TYPE_SENSE_MASK
)
837 /* OMAP1 allows only only edge triggering */
838 if (!cpu_class_is_omap2()
839 && (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
842 bank
= get_irq_chip_data(irq
);
843 spin_lock_irqsave(&bank
->lock
, flags
);
844 retval
= _set_gpio_triggering(bank
, get_gpio_index(gpio
), type
);
846 irq_desc
[irq
].status
&= ~IRQ_TYPE_SENSE_MASK
;
847 irq_desc
[irq
].status
|= type
;
849 spin_unlock_irqrestore(&bank
->lock
, flags
);
851 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
852 __set_irq_handler_unlocked(irq
, handle_level_irq
);
853 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
854 __set_irq_handler_unlocked(irq
, handle_edge_irq
);
859 static void _clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
861 void __iomem
*reg
= bank
->base
;
863 switch (bank
->method
) {
864 #ifdef CONFIG_ARCH_OMAP1
866 /* MPUIO irqstatus is reset by reading the status register,
867 * so do nothing here */
870 #ifdef CONFIG_ARCH_OMAP15XX
871 case METHOD_GPIO_1510
:
872 reg
+= OMAP1510_GPIO_INT_STATUS
;
875 #ifdef CONFIG_ARCH_OMAP16XX
876 case METHOD_GPIO_1610
:
877 reg
+= OMAP1610_GPIO_IRQSTATUS1
;
880 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
881 case METHOD_GPIO_7XX
:
882 reg
+= OMAP7XX_GPIO_INT_STATUS
;
885 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
886 case METHOD_GPIO_24XX
:
887 reg
+= OMAP24XX_GPIO_IRQSTATUS1
;
890 #if defined(CONFIG_ARCH_OMAP4)
891 case METHOD_GPIO_24XX
:
892 reg
+= OMAP4_GPIO_IRQSTATUS0
;
899 __raw_writel(gpio_mask
, reg
);
901 /* Workaround for clearing DSP GPIO interrupts to allow retention */
902 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
903 reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS2
;
905 #if defined(CONFIG_ARCH_OMAP4)
906 reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS1
;
908 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
909 __raw_writel(gpio_mask
, reg
);
911 /* Flush posted write for the irq status to avoid spurious interrupts */
916 static inline void _clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
918 _clear_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
));
921 static u32
_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
923 void __iomem
*reg
= bank
->base
;
928 switch (bank
->method
) {
929 #ifdef CONFIG_ARCH_OMAP1
931 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
936 #ifdef CONFIG_ARCH_OMAP15XX
937 case METHOD_GPIO_1510
:
938 reg
+= OMAP1510_GPIO_INT_MASK
;
943 #ifdef CONFIG_ARCH_OMAP16XX
944 case METHOD_GPIO_1610
:
945 reg
+= OMAP1610_GPIO_IRQENABLE1
;
949 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
950 case METHOD_GPIO_7XX
:
951 reg
+= OMAP7XX_GPIO_INT_MASK
;
956 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
957 case METHOD_GPIO_24XX
:
958 reg
+= OMAP24XX_GPIO_IRQENABLE1
;
962 #if defined(CONFIG_ARCH_OMAP4)
963 case METHOD_GPIO_24XX
:
964 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
973 l
= __raw_readl(reg
);
980 static void _enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
, int enable
)
982 void __iomem
*reg
= bank
->base
;
985 switch (bank
->method
) {
986 #ifdef CONFIG_ARCH_OMAP1
988 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
989 l
= __raw_readl(reg
);
996 #ifdef CONFIG_ARCH_OMAP15XX
997 case METHOD_GPIO_1510
:
998 reg
+= OMAP1510_GPIO_INT_MASK
;
999 l
= __raw_readl(reg
);
1006 #ifdef CONFIG_ARCH_OMAP16XX
1007 case METHOD_GPIO_1610
:
1009 reg
+= OMAP1610_GPIO_SET_IRQENABLE1
;
1011 reg
+= OMAP1610_GPIO_CLEAR_IRQENABLE1
;
1015 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1016 case METHOD_GPIO_7XX
:
1017 reg
+= OMAP7XX_GPIO_INT_MASK
;
1018 l
= __raw_readl(reg
);
1025 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1026 case METHOD_GPIO_24XX
:
1028 reg
+= OMAP24XX_GPIO_SETIRQENABLE1
;
1030 reg
+= OMAP24XX_GPIO_CLEARIRQENABLE1
;
1034 #ifdef CONFIG_ARCH_OMAP4
1035 case METHOD_GPIO_24XX
:
1037 reg
+= OMAP4_GPIO_IRQSTATUSSET0
;
1039 reg
+= OMAP4_GPIO_IRQSTATUSCLR0
;
1047 __raw_writel(l
, reg
);
1050 static inline void _set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
, int enable
)
1052 _enable_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
), enable
);
1056 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1057 * 1510 does not seem to have a wake-up register. If JTAG is connected
1058 * to the target, system will wake up always on GPIO events. While
1059 * system is running all registered GPIO interrupts need to have wake-up
1060 * enabled. When system is suspended, only selected GPIO interrupts need
1061 * to have wake-up enabled.
1063 static int _set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
1065 unsigned long flags
;
1067 switch (bank
->method
) {
1068 #ifdef CONFIG_ARCH_OMAP16XX
1070 case METHOD_GPIO_1610
:
1071 spin_lock_irqsave(&bank
->lock
, flags
);
1073 bank
->suspend_wakeup
|= (1 << gpio
);
1075 bank
->suspend_wakeup
&= ~(1 << gpio
);
1076 spin_unlock_irqrestore(&bank
->lock
, flags
);
1079 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1080 defined(CONFIG_ARCH_OMAP4)
1081 case METHOD_GPIO_24XX
:
1082 if (bank
->non_wakeup_gpios
& (1 << gpio
)) {
1083 printk(KERN_ERR
"Unable to modify wakeup on "
1084 "non-wakeup GPIO%d\n",
1085 (bank
- gpio_bank
) * 32 + gpio
);
1088 spin_lock_irqsave(&bank
->lock
, flags
);
1090 bank
->suspend_wakeup
|= (1 << gpio
);
1092 bank
->suspend_wakeup
&= ~(1 << gpio
);
1093 spin_unlock_irqrestore(&bank
->lock
, flags
);
1097 printk(KERN_ERR
"Can't enable GPIO wakeup for method %i\n",
1103 static void _reset_gpio(struct gpio_bank
*bank
, int gpio
)
1105 _set_gpio_direction(bank
, get_gpio_index(gpio
), 1);
1106 _set_gpio_irqenable(bank
, gpio
, 0);
1107 _clear_gpio_irqstatus(bank
, gpio
);
1108 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
1111 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1112 static int gpio_wake_enable(unsigned int irq
, unsigned int enable
)
1114 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1115 struct gpio_bank
*bank
;
1118 if (check_gpio(gpio
) < 0)
1120 bank
= get_irq_chip_data(irq
);
1121 retval
= _set_gpio_wakeup(bank
, get_gpio_index(gpio
), enable
);
1126 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1128 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
1129 unsigned long flags
;
1131 spin_lock_irqsave(&bank
->lock
, flags
);
1133 /* Set trigger to none. You need to enable the desired trigger with
1134 * request_irq() or set_irq_type().
1136 _set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
1138 #ifdef CONFIG_ARCH_OMAP15XX
1139 if (bank
->method
== METHOD_GPIO_1510
) {
1142 /* Claim the pin for MPU */
1143 reg
= bank
->base
+ OMAP1510_GPIO_PIN_CONTROL
;
1144 __raw_writel(__raw_readl(reg
) | (1 << offset
), reg
);
1147 spin_unlock_irqrestore(&bank
->lock
, flags
);
1152 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1154 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
1155 unsigned long flags
;
1157 spin_lock_irqsave(&bank
->lock
, flags
);
1158 #ifdef CONFIG_ARCH_OMAP16XX
1159 if (bank
->method
== METHOD_GPIO_1610
) {
1160 /* Disable wake-up during idle for dynamic tick */
1161 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1162 __raw_writel(1 << offset
, reg
);
1165 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1166 defined(CONFIG_ARCH_OMAP4)
1167 if (bank
->method
== METHOD_GPIO_24XX
) {
1168 /* Disable wake-up during idle for dynamic tick */
1169 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1170 __raw_writel(1 << offset
, reg
);
1173 _reset_gpio(bank
, bank
->chip
.base
+ offset
);
1174 spin_unlock_irqrestore(&bank
->lock
, flags
);
1178 * We need to unmask the GPIO bank interrupt as soon as possible to
1179 * avoid missing GPIO interrupts for other lines in the bank.
1180 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1181 * in the bank to avoid missing nested interrupts for a GPIO line.
1182 * If we wait to unmask individual GPIO lines in the bank after the
1183 * line's interrupt handler has been run, we may miss some nested
1186 static void gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
1188 void __iomem
*isr_reg
= NULL
;
1190 unsigned int gpio_irq
;
1191 struct gpio_bank
*bank
;
1195 desc
->chip
->ack(irq
);
1197 bank
= get_irq_data(irq
);
1198 #ifdef CONFIG_ARCH_OMAP1
1199 if (bank
->method
== METHOD_MPUIO
)
1200 isr_reg
= bank
->base
+ OMAP_MPUIO_GPIO_INT
;
1202 #ifdef CONFIG_ARCH_OMAP15XX
1203 if (bank
->method
== METHOD_GPIO_1510
)
1204 isr_reg
= bank
->base
+ OMAP1510_GPIO_INT_STATUS
;
1206 #if defined(CONFIG_ARCH_OMAP16XX)
1207 if (bank
->method
== METHOD_GPIO_1610
)
1208 isr_reg
= bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
;
1210 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1211 if (bank
->method
== METHOD_GPIO_7XX
)
1212 isr_reg
= bank
->base
+ OMAP7XX_GPIO_INT_STATUS
;
1214 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1215 if (bank
->method
== METHOD_GPIO_24XX
)
1216 isr_reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
;
1218 #if defined(CONFIG_ARCH_OMAP4)
1219 if (bank
->method
== METHOD_GPIO_24XX
)
1220 isr_reg
= bank
->base
+ OMAP4_GPIO_IRQSTATUS0
;
1223 u32 isr_saved
, level_mask
= 0;
1226 enabled
= _get_gpio_irqbank_mask(bank
);
1227 isr_saved
= isr
= __raw_readl(isr_reg
) & enabled
;
1229 if (cpu_is_omap15xx() && (bank
->method
== METHOD_MPUIO
))
1232 if (cpu_class_is_omap2()) {
1233 level_mask
= bank
->level_mask
& enabled
;
1236 /* clear edge sensitive interrupts before handler(s) are
1237 called so that we don't miss any interrupt occurred while
1239 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 0);
1240 _clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
1241 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 1);
1243 /* if there is only edge sensitive GPIO pin interrupts
1244 configured, we could unmask GPIO bank interrupt immediately */
1245 if (!level_mask
&& !unmasked
) {
1247 desc
->chip
->unmask(irq
);
1255 gpio_irq
= bank
->virtual_irq_start
;
1256 for (; isr
!= 0; isr
>>= 1, gpio_irq
++) {
1260 generic_handle_irq(gpio_irq
);
1263 /* if bank has any level sensitive GPIO pin interrupt
1264 configured, we must unmask the bank interrupt only after
1265 handler(s) are executed in order to avoid spurious bank
1268 desc
->chip
->unmask(irq
);
1272 static void gpio_irq_shutdown(unsigned int irq
)
1274 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1275 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1277 _reset_gpio(bank
, gpio
);
1280 static void gpio_ack_irq(unsigned int irq
)
1282 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1283 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1285 _clear_gpio_irqstatus(bank
, gpio
);
1288 static void gpio_mask_irq(unsigned int irq
)
1290 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1291 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1293 _set_gpio_irqenable(bank
, gpio
, 0);
1294 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
1297 static void gpio_unmask_irq(unsigned int irq
)
1299 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1300 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1301 unsigned int irq_mask
= 1 << get_gpio_index(gpio
);
1302 struct irq_desc
*desc
= irq_to_desc(irq
);
1303 u32 trigger
= desc
->status
& IRQ_TYPE_SENSE_MASK
;
1306 _set_gpio_triggering(bank
, get_gpio_index(gpio
), trigger
);
1308 /* For level-triggered GPIOs, the clearing must be done after
1309 * the HW source is cleared, thus after the handler has run */
1310 if (bank
->level_mask
& irq_mask
) {
1311 _set_gpio_irqenable(bank
, gpio
, 0);
1312 _clear_gpio_irqstatus(bank
, gpio
);
1315 _set_gpio_irqenable(bank
, gpio
, 1);
1318 static struct irq_chip gpio_irq_chip
= {
1320 .shutdown
= gpio_irq_shutdown
,
1321 .ack
= gpio_ack_irq
,
1322 .mask
= gpio_mask_irq
,
1323 .unmask
= gpio_unmask_irq
,
1324 .set_type
= gpio_irq_type
,
1325 .set_wake
= gpio_wake_enable
,
1328 /*---------------------------------------------------------------------*/
1330 #ifdef CONFIG_ARCH_OMAP1
1332 /* MPUIO uses the always-on 32k clock */
1334 static void mpuio_ack_irq(unsigned int irq
)
1336 /* The ISR is reset automatically, so do nothing here. */
1339 static void mpuio_mask_irq(unsigned int irq
)
1341 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1342 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1344 _set_gpio_irqenable(bank
, gpio
, 0);
1347 static void mpuio_unmask_irq(unsigned int irq
)
1349 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1350 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1352 _set_gpio_irqenable(bank
, gpio
, 1);
1355 static struct irq_chip mpuio_irq_chip
= {
1357 .ack
= mpuio_ack_irq
,
1358 .mask
= mpuio_mask_irq
,
1359 .unmask
= mpuio_unmask_irq
,
1360 .set_type
= gpio_irq_type
,
1361 #ifdef CONFIG_ARCH_OMAP16XX
1362 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1363 .set_wake
= gpio_wake_enable
,
1368 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1371 #ifdef CONFIG_ARCH_OMAP16XX
1373 #include <linux/platform_device.h>
1375 static int omap_mpuio_suspend_noirq(struct device
*dev
)
1377 struct platform_device
*pdev
= to_platform_device(dev
);
1378 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1379 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1380 unsigned long flags
;
1382 spin_lock_irqsave(&bank
->lock
, flags
);
1383 bank
->saved_wakeup
= __raw_readl(mask_reg
);
1384 __raw_writel(0xffff & ~bank
->suspend_wakeup
, mask_reg
);
1385 spin_unlock_irqrestore(&bank
->lock
, flags
);
1390 static int omap_mpuio_resume_noirq(struct device
*dev
)
1392 struct platform_device
*pdev
= to_platform_device(dev
);
1393 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1394 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1395 unsigned long flags
;
1397 spin_lock_irqsave(&bank
->lock
, flags
);
1398 __raw_writel(bank
->saved_wakeup
, mask_reg
);
1399 spin_unlock_irqrestore(&bank
->lock
, flags
);
1404 static struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
1405 .suspend_noirq
= omap_mpuio_suspend_noirq
,
1406 .resume_noirq
= omap_mpuio_resume_noirq
,
1409 /* use platform_driver for this, now that there's no longer any
1410 * point to sys_device (other than not disturbing old code).
1412 static struct platform_driver omap_mpuio_driver
= {
1415 .pm
= &omap_mpuio_dev_pm_ops
,
1419 static struct platform_device omap_mpuio_device
= {
1423 .driver
= &omap_mpuio_driver
.driver
,
1425 /* could list the /proc/iomem resources */
1428 static inline void mpuio_init(void)
1430 platform_set_drvdata(&omap_mpuio_device
, &gpio_bank_1610
[0]);
1432 if (platform_driver_register(&omap_mpuio_driver
) == 0)
1433 (void) platform_device_register(&omap_mpuio_device
);
1437 static inline void mpuio_init(void) {}
1442 extern struct irq_chip mpuio_irq_chip
;
1444 #define bank_is_mpuio(bank) 0
1445 static inline void mpuio_init(void) {}
1449 /*---------------------------------------------------------------------*/
1451 /* REVISIT these are stupid implementations! replace by ones that
1452 * don't switch on METHOD_* and which mostly avoid spinlocks
1455 static int gpio_input(struct gpio_chip
*chip
, unsigned offset
)
1457 struct gpio_bank
*bank
;
1458 unsigned long flags
;
1460 bank
= container_of(chip
, struct gpio_bank
, chip
);
1461 spin_lock_irqsave(&bank
->lock
, flags
);
1462 _set_gpio_direction(bank
, offset
, 1);
1463 spin_unlock_irqrestore(&bank
->lock
, flags
);
1467 static int gpio_is_input(struct gpio_bank
*bank
, int mask
)
1469 void __iomem
*reg
= bank
->base
;
1471 switch (bank
->method
) {
1473 reg
+= OMAP_MPUIO_IO_CNTL
;
1475 case METHOD_GPIO_1510
:
1476 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
1478 case METHOD_GPIO_1610
:
1479 reg
+= OMAP1610_GPIO_DIRECTION
;
1481 case METHOD_GPIO_7XX
:
1482 reg
+= OMAP7XX_GPIO_DIR_CONTROL
;
1484 case METHOD_GPIO_24XX
:
1485 reg
+= OMAP24XX_GPIO_OE
;
1488 return __raw_readl(reg
) & mask
;
1491 static int gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1493 struct gpio_bank
*bank
;
1498 gpio
= chip
->base
+ offset
;
1499 bank
= get_gpio_bank(gpio
);
1501 mask
= 1 << get_gpio_index(gpio
);
1503 if (gpio_is_input(bank
, mask
))
1504 return _get_gpio_datain(bank
, gpio
);
1506 return _get_gpio_dataout(bank
, gpio
);
1509 static int gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
1511 struct gpio_bank
*bank
;
1512 unsigned long flags
;
1514 bank
= container_of(chip
, struct gpio_bank
, chip
);
1515 spin_lock_irqsave(&bank
->lock
, flags
);
1516 _set_gpio_dataout(bank
, offset
, value
);
1517 _set_gpio_direction(bank
, offset
, 0);
1518 spin_unlock_irqrestore(&bank
->lock
, flags
);
1522 static void gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1524 struct gpio_bank
*bank
;
1525 unsigned long flags
;
1527 bank
= container_of(chip
, struct gpio_bank
, chip
);
1528 spin_lock_irqsave(&bank
->lock
, flags
);
1529 _set_gpio_dataout(bank
, offset
, value
);
1530 spin_unlock_irqrestore(&bank
->lock
, flags
);
1533 static int gpio_2irq(struct gpio_chip
*chip
, unsigned offset
)
1535 struct gpio_bank
*bank
;
1537 bank
= container_of(chip
, struct gpio_bank
, chip
);
1538 return bank
->virtual_irq_start
+ offset
;
1541 /*---------------------------------------------------------------------*/
1543 static int initialized
;
1544 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1545 static struct clk
* gpio_ick
;
1548 #if defined(CONFIG_ARCH_OMAP2)
1549 static struct clk
* gpio_fck
;
1552 #if defined(CONFIG_ARCH_OMAP2430)
1553 static struct clk
* gpio5_ick
;
1554 static struct clk
* gpio5_fck
;
1557 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1558 static struct clk
*gpio_iclks
[OMAP34XX_NR_GPIOS
];
1561 static void __init
omap_gpio_show_rev(void)
1565 if (cpu_is_omap16xx())
1566 rev
= __raw_readw(gpio_bank
[1].base
+ OMAP1610_GPIO_REVISION
);
1567 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1568 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1569 else if (cpu_is_omap44xx())
1570 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP4_GPIO_REVISION
);
1574 printk(KERN_INFO
"OMAP GPIO hardware version %d.%d\n",
1575 (rev
>> 4) & 0x0f, rev
& 0x0f);
1578 /* This lock class tells lockdep that GPIO irqs are in a different
1579 * category than their parents, so it won't report false recursion.
1581 static struct lock_class_key gpio_lock_class
;
1583 static int __init
_omap_gpio_init(void)
1587 struct gpio_bank
*bank
;
1588 int bank_size
= SZ_8K
; /* Module 4KB + L4 4KB except on omap1 */
1593 #if defined(CONFIG_ARCH_OMAP1)
1594 if (cpu_is_omap15xx()) {
1595 gpio_ick
= clk_get(NULL
, "arm_gpio_ck");
1596 if (IS_ERR(gpio_ick
))
1597 printk("Could not get arm_gpio_ck\n");
1599 clk_enable(gpio_ick
);
1602 #if defined(CONFIG_ARCH_OMAP2)
1603 if (cpu_class_is_omap2()) {
1604 gpio_ick
= clk_get(NULL
, "gpios_ick");
1605 if (IS_ERR(gpio_ick
))
1606 printk("Could not get gpios_ick\n");
1608 clk_enable(gpio_ick
);
1609 gpio_fck
= clk_get(NULL
, "gpios_fck");
1610 if (IS_ERR(gpio_fck
))
1611 printk("Could not get gpios_fck\n");
1613 clk_enable(gpio_fck
);
1616 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1618 #if defined(CONFIG_ARCH_OMAP2430)
1619 if (cpu_is_omap2430()) {
1620 gpio5_ick
= clk_get(NULL
, "gpio5_ick");
1621 if (IS_ERR(gpio5_ick
))
1622 printk("Could not get gpio5_ick\n");
1624 clk_enable(gpio5_ick
);
1625 gpio5_fck
= clk_get(NULL
, "gpio5_fck");
1626 if (IS_ERR(gpio5_fck
))
1627 printk("Could not get gpio5_fck\n");
1629 clk_enable(gpio5_fck
);
1635 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1636 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1637 for (i
= 0; i
< OMAP34XX_NR_GPIOS
; i
++) {
1638 sprintf(clk_name
, "gpio%d_ick", i
+ 1);
1639 gpio_iclks
[i
] = clk_get(NULL
, clk_name
);
1640 if (IS_ERR(gpio_iclks
[i
]))
1641 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1643 clk_enable(gpio_iclks
[i
]);
1649 #ifdef CONFIG_ARCH_OMAP15XX
1650 if (cpu_is_omap15xx()) {
1651 gpio_bank_count
= 2;
1652 gpio_bank
= gpio_bank_1510
;
1656 #if defined(CONFIG_ARCH_OMAP16XX)
1657 if (cpu_is_omap16xx()) {
1658 gpio_bank_count
= 5;
1659 gpio_bank
= gpio_bank_1610
;
1663 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1664 if (cpu_is_omap7xx()) {
1665 gpio_bank_count
= 7;
1666 gpio_bank
= gpio_bank_7xx
;
1670 #ifdef CONFIG_ARCH_OMAP24XX
1671 if (cpu_is_omap242x()) {
1672 gpio_bank_count
= 4;
1673 gpio_bank
= gpio_bank_242x
;
1675 if (cpu_is_omap243x()) {
1676 gpio_bank_count
= 5;
1677 gpio_bank
= gpio_bank_243x
;
1680 #ifdef CONFIG_ARCH_OMAP34XX
1681 if (cpu_is_omap34xx()) {
1682 gpio_bank_count
= OMAP34XX_NR_GPIOS
;
1683 gpio_bank
= gpio_bank_34xx
;
1686 #ifdef CONFIG_ARCH_OMAP4
1687 if (cpu_is_omap44xx()) {
1688 gpio_bank_count
= OMAP34XX_NR_GPIOS
;
1689 gpio_bank
= gpio_bank_44xx
;
1692 for (i
= 0; i
< gpio_bank_count
; i
++) {
1693 int j
, gpio_count
= 16;
1695 bank
= &gpio_bank
[i
];
1696 spin_lock_init(&bank
->lock
);
1698 /* Static mapping, never released */
1699 bank
->base
= ioremap(bank
->pbase
, bank_size
);
1701 printk(KERN_ERR
"Could not ioremap gpio bank%i\n", i
);
1705 if (bank_is_mpuio(bank
))
1706 __raw_writew(0xffff, bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
);
1707 if (cpu_is_omap15xx() && bank
->method
== METHOD_GPIO_1510
) {
1708 __raw_writew(0xffff, bank
->base
+ OMAP1510_GPIO_INT_MASK
);
1709 __raw_writew(0x0000, bank
->base
+ OMAP1510_GPIO_INT_STATUS
);
1711 if (cpu_is_omap16xx() && bank
->method
== METHOD_GPIO_1610
) {
1712 __raw_writew(0x0000, bank
->base
+ OMAP1610_GPIO_IRQENABLE1
);
1713 __raw_writew(0xffff, bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
);
1714 __raw_writew(0x0014, bank
->base
+ OMAP1610_GPIO_SYSCONFIG
);
1716 if (cpu_is_omap7xx() && bank
->method
== METHOD_GPIO_7XX
) {
1717 __raw_writel(0xffffffff, bank
->base
+ OMAP7XX_GPIO_INT_MASK
);
1718 __raw_writel(0x00000000, bank
->base
+ OMAP7XX_GPIO_INT_STATUS
);
1720 gpio_count
= 32; /* 7xx has 32-bit GPIOs */
1723 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1724 defined(CONFIG_ARCH_OMAP4)
1725 if (bank
->method
== METHOD_GPIO_24XX
) {
1726 static const u32 non_wakeup_gpios
[] = {
1727 0xe203ffc0, 0x08700040
1729 if (cpu_is_omap44xx()) {
1730 __raw_writel(0xffffffff, bank
->base
+
1731 OMAP4_GPIO_IRQSTATUSCLR0
);
1732 __raw_writew(0x0015, bank
->base
+
1733 OMAP4_GPIO_SYSCONFIG
);
1734 __raw_writel(0x00000000, bank
->base
+
1735 OMAP4_GPIO_DEBOUNCENABLE
);
1736 /* Initialize interface clock ungated, module enabled */
1737 __raw_writel(0, bank
->base
+ OMAP4_GPIO_CTRL
);
1739 __raw_writel(0x00000000, bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
1740 __raw_writel(0xffffffff, bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
);
1741 __raw_writew(0x0015, bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
1742 __raw_writel(0x00000000, bank
->base
+ OMAP24XX_GPIO_DEBOUNCE_EN
);
1744 /* Initialize interface clock ungated, module enabled */
1745 __raw_writel(0, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1747 if (i
< ARRAY_SIZE(non_wakeup_gpios
))
1748 bank
->non_wakeup_gpios
= non_wakeup_gpios
[i
];
1752 /* REVISIT eventually switch from OMAP-specific gpio structs
1753 * over to the generic ones
1755 bank
->chip
.request
= omap_gpio_request
;
1756 bank
->chip
.free
= omap_gpio_free
;
1757 bank
->chip
.direction_input
= gpio_input
;
1758 bank
->chip
.get
= gpio_get
;
1759 bank
->chip
.direction_output
= gpio_output
;
1760 bank
->chip
.set
= gpio_set
;
1761 bank
->chip
.to_irq
= gpio_2irq
;
1762 if (bank_is_mpuio(bank
)) {
1763 bank
->chip
.label
= "mpuio";
1764 #ifdef CONFIG_ARCH_OMAP16XX
1765 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1767 bank
->chip
.base
= OMAP_MPUIO(0);
1769 bank
->chip
.label
= "gpio";
1770 bank
->chip
.base
= gpio
;
1773 bank
->chip
.ngpio
= gpio_count
;
1775 gpiochip_add(&bank
->chip
);
1777 for (j
= bank
->virtual_irq_start
;
1778 j
< bank
->virtual_irq_start
+ gpio_count
; j
++) {
1779 lockdep_set_class(&irq_desc
[j
].lock
, &gpio_lock_class
);
1780 set_irq_chip_data(j
, bank
);
1781 if (bank_is_mpuio(bank
))
1782 set_irq_chip(j
, &mpuio_irq_chip
);
1784 set_irq_chip(j
, &gpio_irq_chip
);
1785 set_irq_handler(j
, handle_simple_irq
);
1786 set_irq_flags(j
, IRQF_VALID
);
1788 set_irq_chained_handler(bank
->irq
, gpio_irq_handler
);
1789 set_irq_data(bank
->irq
, bank
);
1791 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1792 sprintf(clk_name
, "gpio%d_dbck", i
+ 1);
1793 bank
->dbck
= clk_get(NULL
, clk_name
);
1794 if (IS_ERR(bank
->dbck
))
1795 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1799 /* Enable system clock for GPIO module.
1800 * The CAM_CLK_CTRL *is* really the right place. */
1801 if (cpu_is_omap16xx())
1802 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL
) | 0x04, ULPD_CAM_CLK_CTRL
);
1804 /* Enable autoidle for the OCP interface */
1805 if (cpu_is_omap24xx())
1806 omap_writel(1 << 0, 0x48019010);
1807 if (cpu_is_omap34xx())
1808 omap_writel(1 << 0, 0x48306814);
1810 omap_gpio_show_rev();
1815 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1816 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1817 static int omap_gpio_suspend(struct sys_device
*dev
, pm_message_t mesg
)
1821 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1824 for (i
= 0; i
< gpio_bank_count
; i
++) {
1825 struct gpio_bank
*bank
= &gpio_bank
[i
];
1826 void __iomem
*wake_status
;
1827 void __iomem
*wake_clear
;
1828 void __iomem
*wake_set
;
1829 unsigned long flags
;
1831 switch (bank
->method
) {
1832 #ifdef CONFIG_ARCH_OMAP16XX
1833 case METHOD_GPIO_1610
:
1834 wake_status
= bank
->base
+ OMAP1610_GPIO_WAKEUPENABLE
;
1835 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1836 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1839 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1840 case METHOD_GPIO_24XX
:
1841 wake_status
= bank
->base
+ OMAP24XX_GPIO_WAKE_EN
;
1842 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1843 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1846 #ifdef CONFIG_ARCH_OMAP4
1847 case METHOD_GPIO_24XX
:
1848 wake_status
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1849 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1850 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1857 spin_lock_irqsave(&bank
->lock
, flags
);
1858 bank
->saved_wakeup
= __raw_readl(wake_status
);
1859 __raw_writel(0xffffffff, wake_clear
);
1860 __raw_writel(bank
->suspend_wakeup
, wake_set
);
1861 spin_unlock_irqrestore(&bank
->lock
, flags
);
1867 static int omap_gpio_resume(struct sys_device
*dev
)
1871 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1874 for (i
= 0; i
< gpio_bank_count
; i
++) {
1875 struct gpio_bank
*bank
= &gpio_bank
[i
];
1876 void __iomem
*wake_clear
;
1877 void __iomem
*wake_set
;
1878 unsigned long flags
;
1880 switch (bank
->method
) {
1881 #ifdef CONFIG_ARCH_OMAP16XX
1882 case METHOD_GPIO_1610
:
1883 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1884 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1887 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1888 case METHOD_GPIO_24XX
:
1889 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1890 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1893 #ifdef CONFIG_ARCH_OMAP4
1894 case METHOD_GPIO_24XX
:
1895 wake_clear
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1896 wake_set
= bank
->base
+ OMAP4_GPIO_IRQWAKEN0
;
1903 spin_lock_irqsave(&bank
->lock
, flags
);
1904 __raw_writel(0xffffffff, wake_clear
);
1905 __raw_writel(bank
->saved_wakeup
, wake_set
);
1906 spin_unlock_irqrestore(&bank
->lock
, flags
);
1912 static struct sysdev_class omap_gpio_sysclass
= {
1914 .suspend
= omap_gpio_suspend
,
1915 .resume
= omap_gpio_resume
,
1918 static struct sys_device omap_gpio_device
= {
1920 .cls
= &omap_gpio_sysclass
,
1925 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1926 defined(CONFIG_ARCH_OMAP4)
1928 static int workaround_enabled
;
1930 void omap2_gpio_prepare_for_retention(void)
1934 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1935 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1936 for (i
= 0; i
< gpio_bank_count
; i
++) {
1937 struct gpio_bank
*bank
= &gpio_bank
[i
];
1940 if (!(bank
->enabled_non_wakeup_gpios
))
1942 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1943 bank
->saved_datain
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
1944 l1
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1945 l2
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1947 #ifdef CONFIG_ARCH_OMAP4
1948 bank
->saved_datain
= __raw_readl(bank
->base
+
1950 l1
= __raw_readl(bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
1951 l2
= __raw_readl(bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
1953 bank
->saved_fallingdetect
= l1
;
1954 bank
->saved_risingdetect
= l2
;
1955 l1
&= ~bank
->enabled_non_wakeup_gpios
;
1956 l2
&= ~bank
->enabled_non_wakeup_gpios
;
1957 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1958 __raw_writel(l1
, bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1959 __raw_writel(l2
, bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1961 #ifdef CONFIG_ARCH_OMAP4
1962 __raw_writel(l1
, bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
1963 __raw_writel(l2
, bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
1968 workaround_enabled
= 0;
1971 workaround_enabled
= 1;
1974 void omap2_gpio_resume_after_retention(void)
1978 if (!workaround_enabled
)
1980 for (i
= 0; i
< gpio_bank_count
; i
++) {
1981 struct gpio_bank
*bank
= &gpio_bank
[i
];
1982 u32 l
, gen
, gen0
, gen1
;
1984 if (!(bank
->enabled_non_wakeup_gpios
))
1986 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1987 __raw_writel(bank
->saved_fallingdetect
,
1988 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1989 __raw_writel(bank
->saved_risingdetect
,
1990 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1991 l
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
1993 #ifdef CONFIG_ARCH_OMAP4
1994 __raw_writel(bank
->saved_fallingdetect
,
1995 bank
->base
+ OMAP4_GPIO_FALLINGDETECT
);
1996 __raw_writel(bank
->saved_risingdetect
,
1997 bank
->base
+ OMAP4_GPIO_RISINGDETECT
);
1998 l
= __raw_readl(bank
->base
+ OMAP4_GPIO_DATAIN
);
2000 /* Check if any of the non-wakeup interrupt GPIOs have changed
2001 * state. If so, generate an IRQ by software. This is
2002 * horribly racy, but it's the best we can do to work around
2003 * this silicon bug. */
2004 l
^= bank
->saved_datain
;
2005 l
&= bank
->non_wakeup_gpios
;
2008 * No need to generate IRQs for the rising edge for gpio IRQs
2009 * configured with falling edge only; and vice versa.
2011 gen0
= l
& bank
->saved_fallingdetect
;
2012 gen0
&= bank
->saved_datain
;
2014 gen1
= l
& bank
->saved_risingdetect
;
2015 gen1
&= ~(bank
->saved_datain
);
2017 /* FIXME: Consider GPIO IRQs with level detections properly! */
2018 gen
= l
& (~(bank
->saved_fallingdetect
) &
2019 ~(bank
->saved_risingdetect
));
2020 /* Consider all GPIO IRQs needed to be updated */
2025 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2026 old0
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
2027 old1
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
2028 __raw_writel(old0
| gen
, bank
->base
+
2029 OMAP24XX_GPIO_LEVELDETECT0
);
2030 __raw_writel(old1
| gen
, bank
->base
+
2031 OMAP24XX_GPIO_LEVELDETECT1
);
2032 __raw_writel(old0
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
2033 __raw_writel(old1
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
2035 #ifdef CONFIG_ARCH_OMAP4
2036 old0
= __raw_readl(bank
->base
+
2037 OMAP4_GPIO_LEVELDETECT0
);
2038 old1
= __raw_readl(bank
->base
+
2039 OMAP4_GPIO_LEVELDETECT1
);
2040 __raw_writel(old0
| l
, bank
->base
+
2041 OMAP4_GPIO_LEVELDETECT0
);
2042 __raw_writel(old1
| l
, bank
->base
+
2043 OMAP4_GPIO_LEVELDETECT1
);
2044 __raw_writel(old0
, bank
->base
+
2045 OMAP4_GPIO_LEVELDETECT0
);
2046 __raw_writel(old1
, bank
->base
+
2047 OMAP4_GPIO_LEVELDETECT1
);
2056 #ifdef CONFIG_ARCH_OMAP34XX
2057 /* save the registers of bank 2-6 */
2058 void omap_gpio_save_context(void)
2062 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2063 for (i
= 1; i
< gpio_bank_count
; i
++) {
2064 struct gpio_bank
*bank
= &gpio_bank
[i
];
2065 gpio_context
[i
].sysconfig
=
2066 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
2067 gpio_context
[i
].irqenable1
=
2068 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
2069 gpio_context
[i
].irqenable2
=
2070 __raw_readl(bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
2071 gpio_context
[i
].wake_en
=
2072 __raw_readl(bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
2073 gpio_context
[i
].ctrl
=
2074 __raw_readl(bank
->base
+ OMAP24XX_GPIO_CTRL
);
2075 gpio_context
[i
].oe
=
2076 __raw_readl(bank
->base
+ OMAP24XX_GPIO_OE
);
2077 gpio_context
[i
].leveldetect0
=
2078 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
2079 gpio_context
[i
].leveldetect1
=
2080 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
2081 gpio_context
[i
].risingdetect
=
2082 __raw_readl(bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
2083 gpio_context
[i
].fallingdetect
=
2084 __raw_readl(bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
2085 gpio_context
[i
].dataout
=
2086 __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
2087 gpio_context
[i
].setwkuena
=
2088 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SETWKUENA
);
2089 gpio_context
[i
].setdataout
=
2090 __raw_readl(bank
->base
+ OMAP24XX_GPIO_SETDATAOUT
);
2094 /* restore the required registers of bank 2-6 */
2095 void omap_gpio_restore_context(void)
2099 for (i
= 1; i
< gpio_bank_count
; i
++) {
2100 struct gpio_bank
*bank
= &gpio_bank
[i
];
2101 __raw_writel(gpio_context
[i
].sysconfig
,
2102 bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
2103 __raw_writel(gpio_context
[i
].irqenable1
,
2104 bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
2105 __raw_writel(gpio_context
[i
].irqenable2
,
2106 bank
->base
+ OMAP24XX_GPIO_IRQENABLE2
);
2107 __raw_writel(gpio_context
[i
].wake_en
,
2108 bank
->base
+ OMAP24XX_GPIO_WAKE_EN
);
2109 __raw_writel(gpio_context
[i
].ctrl
,
2110 bank
->base
+ OMAP24XX_GPIO_CTRL
);
2111 __raw_writel(gpio_context
[i
].oe
,
2112 bank
->base
+ OMAP24XX_GPIO_OE
);
2113 __raw_writel(gpio_context
[i
].leveldetect0
,
2114 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
2115 __raw_writel(gpio_context
[i
].leveldetect1
,
2116 bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
2117 __raw_writel(gpio_context
[i
].risingdetect
,
2118 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
2119 __raw_writel(gpio_context
[i
].fallingdetect
,
2120 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
2121 __raw_writel(gpio_context
[i
].dataout
,
2122 bank
->base
+ OMAP24XX_GPIO_DATAOUT
);
2123 __raw_writel(gpio_context
[i
].setwkuena
,
2124 bank
->base
+ OMAP24XX_GPIO_SETWKUENA
);
2125 __raw_writel(gpio_context
[i
].setdataout
,
2126 bank
->base
+ OMAP24XX_GPIO_SETDATAOUT
);
2132 * This may get called early from board specific init
2133 * for boards that have interrupts routed via FPGA.
2135 int __init
omap_gpio_init(void)
2138 return _omap_gpio_init();
2143 static int __init
omap_gpio_sysinit(void)
2148 ret
= _omap_gpio_init();
2152 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2153 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2154 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2156 ret
= sysdev_class_register(&omap_gpio_sysclass
);
2158 ret
= sysdev_register(&omap_gpio_device
);
2166 arch_initcall(omap_gpio_sysinit
);
2169 #ifdef CONFIG_DEBUG_FS
2171 #include <linux/debugfs.h>
2172 #include <linux/seq_file.h>
2174 static int dbg_gpio_show(struct seq_file
*s
, void *unused
)
2176 unsigned i
, j
, gpio
;
2178 for (i
= 0, gpio
= 0; i
< gpio_bank_count
; i
++) {
2179 struct gpio_bank
*bank
= gpio_bank
+ i
;
2180 unsigned bankwidth
= 16;
2183 if (bank_is_mpuio(bank
))
2184 gpio
= OMAP_MPUIO(0);
2185 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2188 for (j
= 0; j
< bankwidth
; j
++, gpio
++, mask
<<= 1) {
2189 unsigned irq
, value
, is_in
, irqstat
;
2192 label
= gpiochip_is_requested(&bank
->chip
, j
);
2196 irq
= bank
->virtual_irq_start
+ j
;
2197 value
= gpio_get_value(gpio
);
2198 is_in
= gpio_is_input(bank
, mask
);
2200 if (bank_is_mpuio(bank
))
2201 seq_printf(s
, "MPUIO %2d ", j
);
2203 seq_printf(s
, "GPIO %3d ", gpio
);
2204 seq_printf(s
, "(%-20.20s): %s %s",
2206 is_in
? "in " : "out",
2207 value
? "hi" : "lo");
2209 /* FIXME for at least omap2, show pullup/pulldown state */
2211 irqstat
= irq_desc
[irq
].status
;
2212 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2213 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2214 if (is_in
&& ((bank
->suspend_wakeup
& mask
)
2215 || irqstat
& IRQ_TYPE_SENSE_MASK
)) {
2216 char *trigger
= NULL
;
2218 switch (irqstat
& IRQ_TYPE_SENSE_MASK
) {
2219 case IRQ_TYPE_EDGE_FALLING
:
2220 trigger
= "falling";
2222 case IRQ_TYPE_EDGE_RISING
:
2225 case IRQ_TYPE_EDGE_BOTH
:
2226 trigger
= "bothedge";
2228 case IRQ_TYPE_LEVEL_LOW
:
2231 case IRQ_TYPE_LEVEL_HIGH
:
2238 seq_printf(s
, ", irq-%d %-8s%s",
2240 (bank
->suspend_wakeup
& mask
)
2244 seq_printf(s
, "\n");
2247 if (bank_is_mpuio(bank
)) {
2248 seq_printf(s
, "\n");
2255 static int dbg_gpio_open(struct inode
*inode
, struct file
*file
)
2257 return single_open(file
, dbg_gpio_show
, &inode
->i_private
);
2260 static const struct file_operations debug_fops
= {
2261 .open
= dbg_gpio_open
,
2263 .llseek
= seq_lseek
,
2264 .release
= single_release
,
2267 static int __init
omap_gpio_debuginit(void)
2269 (void) debugfs_create_file("omap_gpio", S_IRUGO
,
2270 NULL
, NULL
, &debug_fops
);
2273 late_initcall(omap_gpio_debuginit
);