arch/arm/plat-omap/counter_32k.c

   1 /*
   2  * OMAP 32ksynctimer/counter_32k-related code
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Tony Lindgren <tony@atomide.com>
   7  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/clocksource.h>
  21
  22 #include <asm/mach/time.h>
  23 #include <asm/sched_clock.h>
  24
  25 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
  26 #define OMAP2_32KSYNCNT_REV_OFF         0x0
  27 #define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
  28 #define OMAP2_32KSYNCNT_CR_OFF_LOW      0x10
  29 #define OMAP2_32KSYNCNT_CR_OFF_HIGH     0x30
  30
  31 /*
  32  * 32KHz clocksource ... always available, on pretty most chips except
  33  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
  34  * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
  35  * but systems won't necessarily want to spend resources that way.
  36  */
  37 static void __iomem *sync32k_cnt_reg;
  38
  39 static u32 notrace omap_32k_read_sched_clock(void)
  40 {
  41         return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
  42 }
  43
  44 /**
  45  * omap_read_persistent_clock -  Return time from a persistent clock.
  46  *
  47  * Reads the time from a source which isn't disabled during PM, the
  48  * 32k sync timer.  Convert the cycles elapsed since last read into
  49  * nsecs and adds to a monotonically increasing timespec.
  50  */
  51 static struct timespec persistent_ts;
  52 static cycles_t cycles;
  53 static unsigned int persistent_mult, persistent_shift;
  54 static DEFINE_SPINLOCK(read_persistent_clock_lock);
  55
  56 static void omap_read_persistent_clock(struct timespec *ts)
  57 {
  58         unsigned long long nsecs;
  59         cycles_t last_cycles;
  60         unsigned long flags;
  61
  62         spin_lock_irqsave(&read_persistent_clock_lock, flags);
  63
  64         last_cycles = cycles;
  65         cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
  66
  67         nsecs = clocksource_cyc2ns(cycles - last_cycles,
  68                                         persistent_mult, persistent_shift);
  69
  70         timespec_add_ns(&persistent_ts, nsecs);
  71
  72         *ts = persistent_ts;
  73
  74         spin_unlock_irqrestore(&read_persistent_clock_lock, flags);
  75 }
  76
  77 /**
  78  * omap_init_clocksource_32k - setup and register counter 32k as a
  79  * kernel clocksource
  80  * @pbase: base addr of counter_32k module
  81  * @size: size of counter_32k to map
  82  *
  83  * Returns 0 upon success or negative error code upon failure.
  84  *
  85  */
  86 int __init omap_init_clocksource_32k(void __iomem *vbase)
  87 {
  88         int ret;
  89
  90         /*
  91          * 32k sync Counter IP register offsets vary between the
  92          * highlander version and the legacy ones.
  93          * The 'SCHEME' bits(30-31) of the revision register is used
  94          * to identify the version.
  95          */
  96         if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
  97                                                 OMAP2_32KSYNCNT_REV_SCHEME)
  98                 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
  99         else
 100                 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
 101
 102         /*
 103          * 120000 rough estimate from the calculations in
 104          * __clocksource_updatefreq_scale.
 105          */
 106         clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
 107                         32768, NSEC_PER_SEC, 120000);
 108
 109         ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
 110                                 250, 32, clocksource_mmio_readl_up);
 111         if (ret) {
 112                 pr_err("32k_counter: can't register clocksource\n");
 113                 return ret;
 114         }
 115
 116         setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
 117         register_persistent_clock(NULL, omap_read_persistent_clock);
 118         pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
 119
 120         return 0;
 121 }